DE10206554B4 - Teletext arrangement with a programmable external program memory - Google Patents

Abstract

Teletext arrangement with a processing unit (10) and at least one of the Processing unit (10) connected first external memory (20) adapted to be processed by the processing unit (10) executable Program store, characterized in that the external Memory is preprogrammed with a loader that is suitable is to program other areas of the memory, the external one Memory (20) one coupled to the processing unit (10) Write enable input (23), so depending on a signal present at this input a memory content of the external memory (20) changeable is.

Description

The The present invention relates to a teletext arrangement having a Processing unit and at least one to the processing unit connected first external memory, which is designed to to store a program executable by the processing unit.

Such a teletext arrangement is described, for example, in "APPLICATION NOTE KITS / BOARDS, SDA 55xx TV Text Pro Evaluation Board", Edition Oct. 9, 2001, Micronas GmbH, Freiburg. The processing unit is in the known arrangement according to 1 - 1 of the publication, an IC of the type "SDA 55xx TV Text Pro" Micronas GmbH, Freiburg, and the first external memory is designed as a flash memory or EPROM (Erasable Programmable Read Only Memory).

Of the contains first external memory a program executable by the processing unit and may also Contain data after switching off the arrangement or at a loss of power should not be lost. Such data concern for example, data for Electronic programming support (EPG = Electronic Program Guide). The program stored in the first external memory is on the desired functionality of the teletext arrangement matched, this functionality is the decoding of with a Television signal transmitted Teletext data, the preparation of video program system (VPS) data and other control functions for a TV and the Displaying information on a screen (OSD = On Screen Display) may include.

This the functionality determining program memory has to be manufactured according to the wishes of the manufacturer Customers, usually the Manufacturers of TV sets, as opposed to one in such applications also used for volatile data storage, the also connected to the processing unit and the for example, to the information from teletext pages to save.

The US 5,440,632 describes a user terminal for subscription television. The terminal includes a microprocessor connected to an external EPROM memory and a memory expansion card. The microprocessor includes an internal ROM in which a BOOT program is stored which initializes the user terminal and a control program the microprocessor. This BOOT program also includes a load routine for downloading a new control program into either the EPROM, the expansion card, or both.

aim The present invention is a teletext arrangement of the type mentioned to disposal to provide, in which a flexible programming of the program memory possible is.

This The object is achieved by a device according to the features of the claim 1 reached. Advantageous embodiments are the subject of the dependent claims.

The has teletext arrangement according to the invention a processing unit and at least one to the processing unit connected first external memory, which is designed to to store a program executable by the processing unit. The external memory has one to the processing unit coupled write enable input on, so that depends from one applied to this input, by the processing unit signal provided a memory content of the external memory variable is.

Of the first memory is preferably manufacturer side with a Loader preprogrammed in one of several memory banks of the Memory is stored, and that is suitable, other of the memory banks to program the memory when it is in the processing unit accomplished becomes. The memory, for example, after switching on a Signal supplied that determines if the loader is from the processing unit accomplished and the memory should be programmed or whether one in the memory ge stores, the function of the teletext arrangement determining Program to be executed by the processing unit.

The Teletext arrangement according to the invention by the customer (the TV manufacturer) or even while a service of the TV at the end customer (the buyer of the TV) or also the seller of the TV be programmed.

The data, which are programmed in the first memory, are read by the loader via a serial interface in the processing unit. from there they are programmed in the first memory. The data with which the first memory is programmed may be any data representing, for example, executable code which are constants or which represent the contents of a table. This data can also be transmitted via the teletext channel, for example be transmitted.

at an embodiment The invention provides that the teletext arrangement has a second external memory connected to the processing unit and the write enable input coupled to the processing unit and a read enable input coupled to the processing unit having. The read enable input the second external memory is in particular to a read enable output connected to the processing unit.

In addition, points the first external memory one to a read enable output of Processing unit coupled read enable input to depending on a signal applied to the read enable input signal program code and / or data from the first memory to the processing unit read.

Of the first and second memories each have address inputs Addressing of the memory areas and data inputs / data outputs for Reading / reading data on, with this data at the first Memory in particular program data included.

at an embodiment An arrangement having first and second memories is a write enable output and a selection signal output of the processing unit, which are connected to a multiplexer, the multiplexer after proviso of the selection signal on at the write enable output of the processing unit applied signal to the write enable input of the first external Memory or the write enable input of the second external Supplies memory, to release one of the two memories for writing while the each other is locked.

Of the second external memory is preferably a volatile memory, such as a RAM memory, in particular an SRAM memory, and the first one External memory is preferably a non-volatile memory, such as a flash memory or an EEPROM.

moreover the processing unit has an internal memory, in which they needed Program sequences or data, in particular those for programming required Program sequences or in the first external memory if necessary cached program data to be stored.

The The present invention will now be described with reference to the accompanying figure illustrated embodiment explained. The figure contains the names of some signals that come with a sweep are marked to indicate that the connections are on where these signals are low-active. These sweeps are replaced by the character "/" below, which precedes the signal designation.

The figure shows a teletext arrangement with a processing unit 10 , one to the processing unit 10 connected first external memory 20 which is designed by the processing unit 10 executable program, and one to the processing unit 10 connected second external memory 30 , The processing unit may be formed, for example, as a programmable microcontroller type SDA 5550 Micronas GmbH, Freiburg, as shown in the example. The first external memory 20 is formed in the example as a flash memory with a capacity of 1M × 8 bits and an access time of less than 115 ns. The second external memory is formed as a SRAM memory having a capacity of 256k × 8 bits and an access time of less than 230ns.

The first external memory 20 is preferably designed to store data in a non-volatile manner in addition to a program that can be executed by the processing unit. Such data, for example, may include information that is next to the executable program for the operation of the processing unit 10 required are. In addition to the EPG data mentioned above, this can be any data that is transmitted via a data channel, in particular the teletext channel.

The first external memory 20 has a read enable input 26 which is connected to a read release output 16 the processing unit 10 is connected to, depending on one in the processing unit 10 generated read enable signal / PSEN output the first external memory for reading the stored program or stored data. Both the read enable output 16 as well as the read enable input are low active, that is, the first external memory is enabled for reading if that is at the read enable input 26 applied signal / RD assumes a logical low level.

The addresses of each 8-bit wide memory areas in the example, which are to be read, are supplied to the first external memory via an address signal of width 20 bits at address inputs A0-A19 and are at an output 11 the processing unit available. The data is passed through the data port during a read operation 25 read out and attached to it closed data closure 15 supplied to the processing unit.

The first external memory further has one to the processing unit 10 coupled write enable input 23 on, which is also low-active and releases the first external memory for writing upon application of a write signal / WR with a logical low level, the address information on the memory areas to be written in the address input 27 present address signal A0-A19 are included. The data will be the first external memory through the data port 25 fed, which works in this case as a data input.

The provision of a write enable input to the first external memory allows the first external memory to be used as the program memory 20 during operation or after delivery to the customer can still be programmed, with one in the external memory 20 stored program also programming this memory 20 controls, of course, only such memory areas of the first external memory 20 can be overwritten, in which this loader is not stored.

The second external memory 30 also has a read enable input 32 on, which is low-active and which is connected to a read enable output 12 the processing unit 10 is connected, this read enable output 12 in the example also low-active. In addition, the second external memory has 30 a write enable input 33 on, which is also low-active.

The second external memory 30 also has a data port 35 with a width of 8 bits on the data port 15 the processing unit 10 is coupled.

The write enable inputs 23 . 33 the first and second external memory 20 . 30 are in the embodiment via a designed as a multiplexer MUX logic circuit to a write enable output 13 the processing unit 10 connected, wherein the multiplexer additionally on at a selection output 14 the processing unit 10 applied selection signal SEL is supplied. The multiplexer MUX leads in accordance with this selection signal on at the write enable output 13 applied write enable signal WR2 either to the write enable input 23 the first external memory or the write enable input 33 the second external memory 30 to. The write enable output 13 the processing unit 10 is also low-active in the example.

The multiplexer MUX has an OR gate in the embodiment 40 , a NAND gate 41 and an inverter 43 on, wherein in each case one of the inputs of the OR gate and the NAND gate, the selection signal SEL is supplied. A second input of the OR gate 40 is the write enable signal / WR3 and a second input of the NAND gate is the inverted write enable signal / WR2 supplied. The output of the OR gate 40 is at the write enable input 33 the second external memory 30 and the output of the NAND gate is at the write enable input 23 the first external memory 20 connected.

In this internal structure of the multiplexer MUX is ensured that at a LOw level, or a logical zero of the selection signal SEL at the output of the NAND gate, a high level or a logical one is applied to the first external memory 20 whose write-enable input 23 low-active is to lock for writing. At a low level or a logical zero of the selection signal SEL is also the level of the write enable signal / WR2 via the OR gate 40 at the write enable input 33 the second external memory 30 to indicate a logic zero at the write enable output 13 the processing unit 10 the second external memory 30 whose write-enable input 33 Also low-active is to release for writing.

If the selection signal SEL assumes a logical high level, the output of the OR gate is located 41 permanently on a high level and locks the second external memory 30 for writing, while the level of the write enable signal / WR2 via the inverter 43 and NAND gates to the write enable input 23 the first external memory 20 is created.

Thus only one of the two external memories can be written to while the readings of the two memories 20 . 30 can be done independently of each other, since the reading process of the first external memory 20 via the read enable output 16 the processing unit 10 and the read operation of the second external memory 30 via the read enable output 12 the processing unit 10 is controlled.

The teletext arrangement according to the invention can be implemented in a simple manner by means of conventional components, for example the microcontroller SDA 5550 and two memory modules, wherein as an additional component only one multiplexer MUX is present, which is between the write enable output 13 the processing unit 10 and the write enable inputs 23 . 33 the external memory 20 . 30 is coupled. The write enable output 13 it can be the standard until be used only to write to a volatile external memory write enable output, while the selection output 14 to which the selection signal SEL is applied, a freely programmable output of the processing unit 10 can be.

Finally, reference is made to a special feature of the teletext arrangement shown in the figure. The processing unit 10 has a dashed-line internal memory XRAM which is simultaneous to the first external memory 20 and the second external memory 30 is described, namely, when the write signal / WR2 at the output 13 the processing unit 10 one of the two external memory 20, 30 releases for writing.

Of the For example, internal memory XRAM has a number of memory banks 16kB each, the address range of these memory banks of the internal memory XRAM the top 16kB of the memory banks of the correspond to first and second external memory, these memory banks, for example each 64kB.

Because of the simultaneous writing of the first external memory 20 and the internal memory XRAM, therefore, in the example, the first external memory can not be written in an address area (the top 16kB of a memory bank) which is also used by the internal memory. This memory area is then preferably used for hard-coded data.

To the memory area of the second external memory 30 to be able to take full advantage of one of the address bits, the address bit A15 in the example, as an enable signal at a enable input 31 for the second external memory 30 to use. At the address input 37 This memory is then applied to the address bits A0 to A14 and A16 to A18, wherein the memory is only described when the address bit A15 has a logic zero. The lowest 32kB of a 64kB memory bank of the second external memory are addressed by address bits A0-A14. For addressing the uppermost 32kB the address bit A16 is used in addition, the address bits A17-A19 are used to select the individual memory banks. Because the selection input 31 of the second external memory is low-active, the second external memory can be enabled for writing only if the address bit A15 is zero, that is, if there is no address that addresses the internal memory XRAM whose memory addresses are between C000h and FFFFh.

Table 1 summarizes the various memory accesses depending on the outputs of the processing unit 10 applied control signals for each memory bank size 64kB in the individual memories, ie in the first external memory 20 , the second external memory 30 and the internal memory XRAM. As already explained, when the write enable signal / WR2 is at the write enable output 13 the processing unit 10 is active, depending on the selection signal SEL either the first external memory 20 or the second external memory 30 described. In this case, by means of the address bits A0 to A15, the entire area of a 64kB memory bank in the first external memory 20 addressed, the higher-order address bits are used to select the individual 64kB memory banks.

In contrast, by means of the address bits A0 to A14, only one addressing of the lowermost 32kB (this corresponds to 7FFFh) of a memory bank of the second external memory takes place, since the address bit A15 is used to select the second external memory 30 is used and this memory is only described if this address bit is zero. A selection of the upper 32kB of this external memory is made using address bit A16.

A Addressing the top 16kB of a 64kB memory bank of the first external memory, i. the addresses C000h to FFFFh are activated simultaneously an access to the internal memory XRAM, so that the first external memory 20 in the upper 16kB area of a memory bank can not be used.

Simultaneously writing the second external memory 30 and the internal memory XRAM is not possible because the upper 32kB of the second external memory is selected by the address bit A16.

When reading the second external memory 30 in which the read signal / RD is at the output 12 assumes a logical zero, both become the second external memory 30 and the internal memory is enabled for reading, as explained, due to the use of the address bit A15 as the chip enable signal for the second external memory 30 the address ranges of the second external memory 30 and internal memory XRAM do not overlap.

Describing and reading the second external memory 30 and thus also the writing of the first external memory 20 is done in response to the controller command MOVX, wherein a low level of the signal / WR2 indicates the writing by means of this command and a low level of the signal / RD indicates the reading by means of this command.

Reading the first external Spei chers 30 takes place independently of the second external memory 30 and the internal memory XRAM when the read enable signal / PSEN is at the output 60 assumes a logical low level. Accordingly, the execution of instructions is one in the first external memory 20 stored program, wherein the reading of data and the execution of commands in respect to the reading mechanism of the first external memory 20 does not differentiate. The low level of the signal / PSEN indicates a read by means of the controller command MOVC.

Claims (8)

Teletext arrangement with a processing unit ( 10 ) and at least one to the processing unit ( 10 ) connected first external memory ( 20 ) adapted to be fed by the processing unit ( 10 ) program, characterized in that the external memory is preprogrammed with a loading program which is suitable for programming other areas of the memory, the external memory ( 20 ) to the processing unit ( 10 ) coupled write enable input ( 23 ), so that depending on a signal applied to this input, a memory content of the external memory ( 20 ) is changeable. Teletext arrangement according to claim 1, comprising a second external memory ( 30 ) to the processing unit ( 10 ) and the one to the processing unit ( 10 ) coupled write enable input ( 33 ) and one to the processing unit ( 10 ) coupled read enable input ( 32 ) having. Teletext arrangement according to Claim 2, in which the read enable input ( 32 ) of the second external memory ( 30 ) to a read enable output ( 12 ) of the processing unit ( 10 ) connected. Teletext arrangement according to Claim 1 or 2, in which the first external memory ( 20 ) one to a read enable output ( 16 ) of the processing unit ( 10 ) coupled read enable input ( 26 ) having. Teletext arrangement according to one of Claims 1 to 4, having a multiplexer (MAX) to which a write enable signal from a write enable output ( 13 ) of the processing unit ( 10 ) and a selection signal from the processing unit ( 10 ) is supplied and the write enable signal in accordance with the selection signal to the write enable input ( 23 . 33 ) of the first or second external memory ( 20 . 30 ) applies. Teletext arrangement according to one of claims 2 to 5, in which the second external memory is a RAM memory, in particular is an SRAM memory. Teletext arrangement according to one of the preceding claims, in the first external memory is a flash memory. Teletext arrangement according to one of the preceding claims, in of which the processing unit has an internal memory.