DE102005025167B3 - Multi-bit virtual ground NAND-memory unit, has memory cells of two adjacent groups of rows connected in common - Google Patents

Abstract

A multi-bit virtual-ground NAND-memory unit in which each memory cell (MC) has a gate connection, two-source/drain connections and two separate memory sites (SS). Each of the memory sites is adjacent to a source/drain connection and the memory cells of the columns are connected in circuit in series via the source/drain connection. Bit-lines (BL) are spaced from one another along the columns and are arranged mutually parallel to one another. The memory cells of two adjacent groups of rows are connected in common and alternating with one of the bit lines and an adjacent bit line, to form NAND-chains of memory cells of the same column and the same group of rows. Each word-line joins the gate-connections of the memory cells of a row to one another.

Description

The The present invention relates to virtual ground NAND storage devices. comprising the batch-trapping multi-bit memory cells.

Charge-trapping memory units comprising a series of memory layers of dielectric materials intended for charge trapping to program the memory cell, in particular SONOS memory cells comprising oxide-nitride-oxide layer sequences as the storage medium, are usually formed by injection of hot electrons programmed from the channel (CHE, channel hot electrons). Charge trapping memory cells may be constructed to allow the storage of two bits of data in each memory cell. In the US 5,768,192 and the US 6,011,725 There are described charge trapping memory cells of a particular type of so-called NROM cells which may be used to store data bits at both the source and drain below the respective gate edges. The programmed cell is read in the reverse direction (reverse read) to achieve a two-bit separation. The deletion is done by hot-hole injection. US 2003/0080372 A1, US 2003/0148582 A1, US 2003/0161192 A1 and US 6,324,099 B1 also describe charge-trapping multi-bit memory.

In US 2003/0185055 A1 and a corresponding publication C. C. Yeh et al., "PHINES: A Novel Low Power Program / Erase, Small Pitch, 2-Bit by Cell Flash Memory ", 2002 IEEE, is a non-volatile one Semiconductor memory cell with trapped electrons in the erase state described, which is operated as a flash memory and two bits in a conventional one Charge-trapping layer sequence, for example an ONO layer sequence, can save. When programming this memory will be electrical holes injected into the non-conductive charge-trapping layer. The injection the hot ones holes can be caused at the source or drain, ie at both ends of the channel become. This mode of operation avoids high programming currents. The deletion either happens through Fowler-Nordheim tunneling of electrons from the channel or gate electrode into the memory layer.

There the storage layer of charge-trapping memory cells electrically is insulating material, is the trapped charge in the places trapped at the trapping points located at each end of the channel. This means that the charge trapping is adjacent to each of the source / drain regions every memory cell can take place. The programming mechanism is improved when the storage layer in addition to limited areas is limited in the vicinity of the two source / drain regions. In this way, a high density of stored data can be achieved become.

A High storage density can also be achieved with a field of floating gate memory cells can be achieved in a NAND architecture. The floating gate will usually from an electrically conductive layer between a control gate electrode and the channel zone formed. The charge carriers, which are located on the floating gate electrode do not accumulate in the programmed state of the memory cell be captured, but over the floating gate is distributed so that the electric field inside of the electrical conductor disappears.

The Reducibility of 2 bit / cell batch trapping memory units is essentially limited by two restrictions. A minimal channel length is required to have a sufficiently high source / drain voltage to enable; and the arrangement of self-aligned source / drain contacts between the word lines requires sufficiently thick insulation to the required voltage to guarantee. An array of charge-trapping memory cells in a NAND field would an even higher one Storage density revealed as earlier Virtual ground fields. Therefore, in principle, a reduction would be the area the unit possible, when the memory cells are arranged in rows of memory cells could become. This is currently not possible if in the memory cell, the conventional read / write operations accomplished because the memory cells of a series only have more memory cells can be addressed which are connected in series.

task It is the object of the present invention to provide a charge tracing storage unit indicating a field of multi-bit memory cells comprising a higher Storage density as earlier Virtual ground fields enabled. Furthermore an operating mode of the memory unit should be specified, with adequate performance of the unit is achieved.

The present multi-bit memory unit comprises a field of memory cells, arranged in rows and columns and a virtual ground NAND architecture form. The memory cells are charge-trapping memory cells, each comprising two separate memory locations, wherein a the memory location is near one of the source / drain terminals and the other storage location is near the opposite Source / drain terminal is located.

The Lines of the memory cells are divided into groups of preferably the same number of lines. Along the columns are the memory cells over their Source / drain terminals connected in series. The source / drain terminals, which are the memory cells have two adjacent stanzas in common, d. H. the source / drain terminals, the between the stanzas form a special Selection of source / drain connections, which by a bit line of a plurality of bit lines are connected. The bit lines are at a distance from each other arranged along the columns parallel to each other; word lines are at a distance from each other across the bitlines the rows are arranged parallel to each other.

Along each column are the source / drain terminals of said selection, the are between the stanzas, either alternating with one of the bit lines and one adjacent to that bit line Bit line connected, or in succession with successive Bit lines. In this way, NAND chains of memory cells formed by memory cells of the same column and the same stanza between successive source / drain terminals, the belong to the selection.

each the word lines connect the gate terminals of the memory cells of a the lines. This means that each gate of the memory cells a NAND chain is connected to another word line, the Belongs to this NAND chain. The NAND chains preferably have the same length, ie they are the same Number of memory cells.

In a first preferred embodiment the bitlines are arranged along the columns, preferably substantially straight line, and each bit line is connected to the source / drain terminals have four memory cells in common, which are arranged in a square and therefore belong to two rows and two columns.

A second preferred embodiment includes bitlines arranged in zigzag along the columns are. Each bit line is alternating with source / drain terminals of Memory cells connected to one of two adjacent columns.

A another preferred embodiment includes columns of memory cells in active areas that are in Zigzag shape are arranged while the bitlines may be straight or at least mostly straight. Also in this embodiment Each bit line is alternately connected to source / drain terminals of Memory cells one of two adjacent columns.

A further preferred embodiment preferably comprises rectilinear bitlines spaced apart from one another are arranged in parallel, at a small angle to the memory cell columns. The columns therefore pass through one bit line after another. Along each column, the source / drain ports of said selection are the Connected in series with successive bit lines.

One electronic circuit for applying voltages to the Memory cells is provided to read, write and erase operations perform, is preferably provided with means for applying a write voltage to any bitline and blocking voltage to one provided to adjacent bit line, wherein the blocking voltage is suitable, a write operation in those memory cells to prevent, which belong to NAND chains, which coincide with the neighboring Bit line are connected.

preferred embodiments are equipped with select transistors that act as switches to a connection of each bit line individually with one of two enable global bitlines. In these embodiments is every other bitline in sequence through the selection transistors connected to the first global bitline, and the other bitlines are connected to the other global bitline.

It follows a more detailed description of examples of the storage units based on the figures.

1 shows a circuit diagram of an embodiment of the storage unit according to the invention.

2 shows the wiring diagram according to 1 with programming voltages of a direct method of a programming method by hot-hole injection.

3 shows a circuit diagram of another embodiment of the memory unit for the erase operation.

4 shows the wiring diagram according to 3 for the write operation.

5 shows the wiring diagram according to 3 for the read operation.

6 shows a circuit diagram according to 1 for another embodiment of the storage unit.

7 shows a circuit diagram according to 1 for still another embodiment of the storage unit.

8th is a plan view of an embodiment of the memory unit according to the circuit diagram of 4 showing the arrangement of NAND chains, bit lines and word lines.

9 is a plan view according to 8th an embodiment according to the circuit diagram of 6 ,

10 is a plan view according to 8th an embodiment according to the circuit diagram of 7 ,

11 is a plan view according to 8th a further embodiment according to the circuit diagram of 7 ,

12 shows a circuit diagram illustrating a NAND chain with a memory cell to be programmed.

13 FIG. 12 shows a schematic diagram illustrating the mirrored NAND chain that represents the NAND chain 12 equivalent.

In the present memory unit, charge trapping memory cells are arranged and connected as a virtual ground NAND field. 1 shows a circuit diagram of a portion of a first embodiment. This plan shows a number of memory cells MC that are part of the memory cell array. Each memory cell MC is a charge-trapping memory cell comprising two memory locations SS adjoining the two source / drain terminals. In 1 the memory cells are drawn on a horizontal line, which does not reflect the actual physical arrangement of the memory cells within the field. The word lines WL run along the rows of memory cells, and the bit lines along the columns, across the word lines. The in the clipping from 1 shown memory cells, which are located between the bit lines BL _m-1 and BL _m , all belong to the same memory cell column. Their sequence along the column can be deduced from their connections to the drawn word lines. The bitlines are connected to one of two global bitlines via select transistors ST. The memory cells are connected in series between the terminals on two adjacent bit lines. In this example, each NAND chain includes four memory cells. The programming is effected by injection of hot holes because the source-drain voltage of the memory cells along the series connection is unfavorably too low for conventional injection of hot electrons from the channel.

2 shows the wiring diagram according to 1 with the entered programming voltages. The memory cell and the memory location to be programmed are indicated by the arrow on the right. On the same side as the memory location to be programmed, the write voltage of 4 V is applied to the source / drain terminal at the end of the NAND chain. The other end of the NAND chain is set to 0V. The gate terminals are set to a high voltage VH of, for example, typically 5V, except for the gate terminal of the memory cell to be programmed, which is set to the programming voltage VP of, for example, typically -7V. Although the next bit line BL _{m + 1} on the other side is at a floating potential, a program disturb is expected on the cell between the programming voltage and the floating potential in the the programmed cell mirrored position is present. This problem is avoided by a special mode of operation suitable for this memory cell array and in connection with 4 is described in detail.

3 shows a circuit diagram according to 1 to another embodiment for the erase operation with registered voltages according to the special mode of operation. All wordlines WL are set to a high voltage, for example, typically 15V. When a lower voltage, in this example 0V, is applied to the bitlines and to the substrate, Fowler-Nordheim tunneling of electrons from the channel zone begins the memory layer, so that the threshold voltage of the memory transistors is locally increased. If the threshold voltage is high enough, all the memory cells are in a state that is considered as erasure.

4 shows the wiring diagram according to 3 for the write operation. The word line of the selected cell to be programmed is set to a suitable negative voltage, the programming voltage of, for example, typically -7 V. The other memory cells of this NAND chain are switched open by a suitable positive voltage, for example the high voltage of typically 5 V to get VH order a hot hole injection, must the source / drain connection at the location of the selected memory cell where you want to place the programming, for example, typically 4 V be set to a positive write voltage V _W of. Because of this, the bit line that matches the one in the 4 designated source / drain terminal A is set to 4 V, for example, if the memory location marked by the up arrow is to be programmed while the bit line connected to the other end of the NAND chain (terminal B ), is kept at moving potential. The floating potential is usually 0 V because the non-addressed bit lines are held at 0 V and the write operation is short, so that the sliding potential does not change significantly during this short time interval. In any case, the potential difference between the source / drain terminals of the memory cell to be programmed is large enough to create holes by the so-called GIDL effect. These holes are successively injected into the storage layer. This means that the threshold voltage of the selected memory cell on the corresponding page is reduced so that the state of the corresponding memory location is changed to the programmed state.

Unless countermeasures are taken, unwanted programming will occur in that memory cell which is in a mirrored position with respect to the bitline being set to the write voltage. This unwanted write operation is prevented by applying a blocking voltage V _i , typically about 2V, to, for example, the next bit line terminal C at the other end of the mirror NAND chain. In any case, the blocking voltage is chosen so that no memory cell of the NAND chains ending in terminal C is programmed. The voltage difference of 2 V between the writing voltage V _w and the blocking voltage V _i , and between the blocking voltage V _i and the sliding potential of about 0 V is too small to produce a hot-hole injection into the memory cells of those NAND chains which end at port C. The threshold voltages of these memory cells therefore remain essentially unchanged. By the blocking voltage V _i , a programming error of those memory cells that are addressed via the same word line, but should not be programmed, can be avoided. This mode of operation enables adequate operation of this memory cell architecture and thus ensures sufficient performance even in a field of extremely increased storage density.

The reading operation will follow the wiring diagram of 5 performed, which shows the appropriate voltages for this purpose. The word line, which addresses the memory cell to be read, is set to the read voltage VR of, for example, 3 volts. The other word lines of the same NRND chain are set to the high voltage VH of, for example, typically about 5V. The memory location to be read is in 5 marked by the upward pointing arrow. The bit line set to the write voltage when programming this memory location is set to a low potential, typically 0V, while the bit line at the other end of the NAND chain is set to a suitable drain voltage of, for example, typically 1.6V becomes.

by virtue of the generated space charge zone in the selected memory cell on the Side of the drain voltage is the influence of the unselected memory location this memory cell is sufficiently small. That's why the electricity is through this memory cell essentially through the selected memory location which is to be read, and can be evaluated to check the programmed state of this memory location and to read the stored data bit. In this way, the both memory locations of the charge-trapping 2-bit memory cells be distinguished in the reading operation.

The typical voltages in the write and read operations are created, are to overview shown again in the following table.

6 shows the circuit diagram for another embodiment in which the sequence of the terminals of the word lines is not symmetrical to the bit lines as in the first embodiment. The sequence of the word line connections is repeated after each connection to a bit line. Therefore, the sequence of connections from one bit line to the next is periodic. The operation modes described in connection with the first embodiment are similarly applied in this second embodiment. The applied voltages can be the same; only the position of the memory cell in which a program disturbance would occur if no blocking voltage were applied is another.

7 shows the circuit diagram for another embodiment, in which the sequence of connections of the word lines is repeated after each connection to a bit line. This embodiment differs from the embodiment according to FIG 6 which will become apparent from the following description of the plan views of exemplary structures of the device.

8th is a plan view of an embodiment of the memory unit according to the circuit diagram of 3 , It shows in the diagram the arrangement of the NAND chains, the bit lines and the word lines. The memory cells are arranged in active areas AA of the substrate, which are separated by shallow trench isolations STI. The boundaries of the shallow trench isolation are represented by the parallel dashed lines that run close together. The word lines WL run along the memory cell rows and substantially cover the channel regions. The source / drain regions are arranged on both sides of the word lines, preferably self-aligned. The source / drain regions that form the source / drain terminals of the memory cells share the memory cells that follow one another along the columns. In this way, the memory cells are arranged in series to form the NAND chains between two consecutive bit line terminals BC. The bit lines BL run along the memory cell columns and are spaced apart in parallel as straight strips. The pitch p of the memory cell array is indicated between the corresponding boundaries of two adjacent bitlines.

The bit line terminals BC are arranged in such a manner that each bit line is connected to the source / drain terminals which have four adjacent memory cells in common are arranged in a square. Along each of the columns, those source / drain terminals connected to bit lines are alternately connected to the two adjacent bit lines. Every NAND chain in the 8th The example shown comprises four memory cells, and all NAND strings belong to the same stanzas, which in this example each comprise four rows and four word lines. The ends of the NAND chains are also ends of those NAND chains that follow on both sides in the same column. Within the same stanza, the NAND chains form a sequence of NAND chains connected in series by their common source / drain terminals connected by the bitlines. This is in 8th highlighted by the hatching of a sequence of NAND chains on the left side, which is also represented by the sequence of double arrows on the right side. This sequence of double arrows corresponds to the arrangement of memory cells in the 3 to 5 are shown on a horizontal line.

9 is a plan view according to 8th for an embodiment according to the circuit diagram of 6 , The memory cell columns are arranged in active areas AA at a small angle to the even bit lines BL, which extend transversely to the word lines WL. From top to bottom along a column in 9 The successive bit line terminals BC connect the source / drain terminals of the selection associated with the corresponding column with successive ones (from left to right in the example of FIGS 9 ) Bitlines.

10 is a plan view according to 8th for an embodiment according to the circuit diagram of 7 , In this embodiment, the bit lines BL run in zigzag substantially along the columns. The bit line terminals BC along a respective bit line are alternately connected to the source / drain terminals of two adjacent memory cell columns. The sequence of NAND chains used in the 6 are shown on horizontal lines, again highlighted by the hatching. The source / drain terminals at the ends of the NAND chains of this sequence of the second embodiment do not coincide, but are electrically connected by the bit lines. This can be seen by the double arrows on the right side. The double arrows show the sequence of NAND cells along the vertical double arrows connected by portions of the bitlines highlighted by the slightly inclined double arrows. The pitch p of the memory cell array and the pitch p 'of the bit lines are in 10 as well as the longitudinal dimension L of the NAND chains along the columns, including portions of the bitline contacts on the source / drain terminals at the ends of the NRND chains.

Since p '/ L and p' / p are sine and cosine of the same angle, (p '/ L) ² + (p' / p) ² = 1 or (p * p ') ² + (L * p') ² = (p * L) ² , it follows that p = (L * p ') / (L ² -p' ² ) ^1/2 . This value of p is the pitch of the memory cell array for a given pitch p 'of the bitlines, which are preferably located at a minimum distance. In a typical example, the minimum bit line pitch p '= 120 nm and the dimension L = 110 nm + n × 140 nm, assuming that the dimension of the respective contact areas is 150 nm, the width of each of n word lines is 100 nm and each Space between word lines 40 nm. For different numbers n of cells present in each NAND chain, the following table gives the cell pitch p and the relative increase (p - p ') / p' of the area of the cell field.

These Table shows that n should be at least 3 to increase the magnification area of the field compared to the first embodiment with even bitlines keep below 5%.

11 is a plan view according to 8th for a further embodiment according to the circuit diagram of 7 , In this embodiment, the active areas AA in which the memory cell columns are located are arranged in a zigzag form while the bit lines are straight. The relative arrangement of the active areas AA, the bit lines BL and the bit line terminals BC is comparable to the embodiment of FIG 10 , It is also possible that both the active areas and the bitlines deviate from the strictly straight array to further minimize the required area of the unit, corresponding to the minimum pitch that can be realized by the processing technique.

The different resistances the electrical connections to the various memory cells lead to a larger fluctuation the threshold voltages of the programmed memory cells. This can be compensated either by the number of programming pulses, combined with a validation operation, which is time consuming, or by a local adaptation of Programming conditions. The latter possibility becomes more detailed described. This method adjusts the stresses during the Write operation to the position of the programmed memory cell within the NAND chain.

12 shows a circuit diagram illustrating a NAND chain between the terminals A and B, which in 4 are marked. The memory cells are numbered in the direction from terminal B to terminal A with the numbers 0, 1, 2, ..., n-1, n and are represented by their resistors R ₀ , R ₁ , R ₂ , ..., R _n shown. For example, when the left memory location of the memory cell number k is to be programmed with the resistor R _k , the write voltage V _w must be applied to the left source / drain terminal of the k th memory cell located on the terminal A side, and The sliding potential must be applied to the right source / drain terminal of the kth memory cell located on the terminal B side. The floating potential at terminal B can be assumed to be 0V, which is the usual bitline voltage applied to the bitlines in the periods between the write and read operations.

Since the gate of the k-th memory cell is set to a negative potential, in this example to -7 V, this memory cell has a high resistance R _k = R _write . The other memory cells of this NAND chain are turned on by their high voltage of typically 5V at their gate terminals. Therefore, all the other resistors R ₀ , R ₁ , R ₂ , ..., R _k-1 , R _{k + 1} , ..., R _{n have} low values that can be assumed to all have the same average value have, hereinafter referred to as R _average . The series of resistors in 12 In order to have the desired write voltage V _w at the designated position of the memory location to be programmed, it is necessary to apply a larger voltage c _l V _w to terminal A. The value of the constant c ₁ can be calculated according to the known laws of electrical circuits.

13 shows the mirror NAND chain between those in the 4 marked terminals A and C. The mirror memory cells are numbered in the direction from terminal C to terminal A with the numbers 0, 1, 2, ..., n-1, n and are represented by their resistors R ' ₀ , R' ₁ , R ' ₂ , ..., R' _n shown. The blocking voltage V _i must be applied to the left side of the k th mirror memory cell, which in the circuit diagram of 13 is represented by its resistance R ' _k = R _inhibit . The resistors R _'0, R' _1, R _'2, ..., R' _k-1, R _{'k + 1,} ..., R' _n of the other memory cells may _average as R are accepted. The constant c ₂ can be calculated in the manner known per se in order to find out the voltage which has to be applied to the terminal C when the voltage c _l V _{w is applied} to the terminal A and the k th memory cell of the mirror NAND chain to the blocking voltage V _i must be set.

The calculation is as follows. When R _i denotes the resistance of the memory cell No. i, counted from terminal B to terminal A, i is integer and 0 ≦ i ≦ n, and R ' _i denotes the resistance of the mirror memory cell No. i on the opposite side of the terminal A. counted in the opposite direction from port C to port A is R = R 0 + R i + R 2 + ... + R k + ... + R n-2 + R n-1 + R n . R i; j = R i + R i + 1 + R i + 2 + ... + R j-2 + R j-1 + R j . R '= R' 0 + R ' 1 + R ' 2 + ... + R ' k + ... + R ' n-2 + R ' n-1 + R ' n . and R ' i; j = R ' i + R ' i + 1 + R ' i + 2 + ... + R ' j-2 + R ' j-1 + R ' j . where i and j are integers and 0 ≤ i ≤ j ≤ n.

When cell No. k, 0 ≦ k ≦ n, is to be programmed, and V _w denotes the writing voltage and V _i denotes the blocking voltage, c ₁ = R / R _{o, k} and c ₂ = (R'-c ₀ × R '_{0; k-1} ) / R '_{k; n} with c ₀ = C ₁ · V _w / V _i With the notation R _k = R _write , R' _k = R _inhibit and the assumption R i = R ' i = R average for i ≠ k, c 1 = R write + n · R average ) / R write + k · R average ) and c 2 = (R inhibit + (n - c 0 · K) · R average ) / (R inhibit + (n - k) · R average ) This multi-bit storage device allows for an arrangement of charge-trapping flash memory cells in a virtual ground NAND field in various memory architectures. A preferred mode of operation is adapted to the structure and layout of the device. These features provide the following advantages: the combination of charge-trapping flash memory cells in a virtual-ground NAND field allows for extremely high storage density; because of the positive threshold voltages, no selection transistor is required within the NAND chains, unlike conventional NAND fields; and the low power consumption due to a hot hole injection mode of operation allows the use of this memory unit as a data memory.

A

Connection of BL _m

AA

active Area

B

Connection of BL _{m + 1}

BC

Hitleitungsanschluss

BL

bit

C

Connection of BL _m-1

L

dimension

MC

memory cell

p

Memory cells Pitch

p '

Bitleitungspitch

R

resistance

R '

resistance

SS

memory location

ST

selection transistor

STI

area grave insulation

V _i

blocking voltage

V _w

write voltage

WL

wordline

Claims (8)

Multi-bit virtual ground NAND memory unit with a field of memory cells (MC), in rows and columns are arranged, wherein the rows are divided into groups, each the memory cells have a gate terminal, two source / drain terminals and has two separate memory locations (SS), one of the storage locations is adjacent to a source / drain terminal and the other memory location is adjacent to the other source / drain terminal, the memory cells the columns over the source / drain connections are connected in series, Bit lines (BL) at a distance from each other along the columns are arranged parallel to each other, along each Column the source / drain terminals, the two Memory cells of two adjacent groups of lines are common, alternating with one of the bit lines and a bit line adjacent thereto, and thus NAND chains memory cells of the same column and the same group of rows are formed, and one word line the gate terminals of the Memory cells of a row interconnects. Multi-bit virtual ground NAND storage device after Claim 1, wherein each bit line is connected to source / drain terminals is common to four memory cells adjacent to each other, which belong to two rows and two columns. Multi-bit virtual ground NAND storage device after Claim 1, wherein Active areas (AA) in zigzag form available are arranged, the columns of memory cells in the active areas are and each bit line alternating with source / drain terminals of Memory cells from one of two adjacent columns connected is. Multi-bit virtual ground NAND storage device after Claim 1, wherein the bitlines along the columns in Zigzag shape are arranged and each bit line alternately with source / drain connections of memory cells from one of two adjacent columns connected is. Multi-bit virtual ground NAND storage unit with a field of memory cells (MC) arranged in rows and columns are, where the rows are divided into groups, each the memory cells have a gate terminal, two source / drain terminals and has two separate memory locations (SS), one of the storage locations is adjacent to a source / drain terminal and the other memory location is adjacent to the other source / drain terminal, the memory cells the columns over the source / drain connections are connected in series, Bit lines (BL) at a distance from each other arranged at an angle to the columns parallel to each other, along each column the source / drain terminals, the two memory cells two adjacent groups of rows are common, successively with in the direction of each row successive Bit lines are connected and so NAND chains of memory cells the same column and the same group of lines, and one word line each, the gate terminals of the memory cells of one row connects with each other. Multi-bit virtual ground NAND storage device after one of the claims 1 to 5, in which each of the groups of rows is the same number Includes lines. A multi-bit virtual ground NAND memory device according to any one of claims 1 to 5, wherein there is provided an electronic circuit which is adapted to supply voltages to the gate terminal and the source / drain terminals of the memory cells to apply during read, write and erase operations, and the electronic circuit comprises means for applying a write voltage to any of the bit lines and a blocking voltage to a respectively adjacent bit line, wherein the blocking voltage is suitable to a write operation to prevent the memory cells belonging to NAND chains connected to the adjacent bit line. Multi-bit virtual ground NAND storage device after Claim 7, wherein Selection transistors as switches in each Bit line are provided two global bitlines available are, every other bitline in sequence across the selection transistors connected to the first global bitline and the others Over bit lines the selection transistors are connected to the second global bit line are.