DE10010284C2 - Method for producing a semiconductor component with a capacitor - Google Patents

Description

The invention relates to a method for producing a Semiconductor component according to the preamble of the claim 1.

Conventional microelectronic semiconductor memory construction elements (DRAMs) essentially consist of a circuit transistor and a storage capacitor. The saved Information is given by the state of charge of the memory capacitor represents. Due to discharge processes the state of charge of a (volatile) DRAM memory cell are constantly renewed.

Oxide or nitride layers are usually used as capacitor dielectrics in DRAMs, which have a dielectric constant of at most about 8. In order to reduce the size of the storage capacitor and to manufacture non-volatile memories, "novel", metal oxide-containing capacitor materials (paraelectrics or ferroelectrics) with significantly higher dielectric constants are required. Known examples of ferroelectric capacitor materials are SrBi ₂ (Ta, Nb) ₂ O ₉ (SBT or SBTN), Pb (Zr, Ti) O ₃ (PZT), Bi ₄ Ti ₃ O ₁₂ (BTO), a known example of a Paraelectric high-Epsylon capacitor material is (Ba, Sr) TiO ₃ (BST).

The use of these novel capacitor materials creates technological difficulties. First of all, these new materials can no longer be combined with the traditional electrode material polycrystalline silicon. Inert electrode materials such as platinum (Pt) or conductive metal oxides (e.g. RuO ₂ ) must therefore be used. The reason for this is that the novel capacitor materials may have to be annealed ("conditioned") several times ("conditioned") after being deposited in an oxygen-containing atmosphere at temperatures of about 550-800 ° C., and only the inert electrode materials mentioned have sufficient temperature stability to achieve a to avoid an undesired chemical reaction between electrode material and capacitor material.

Another difficulty in making such Storage capacitors are based on the fact that they contain metal oxide Capacitor materials usually have high sensitivity towards hydrogen. After the formation of the Spei However, process steps must be carried out that take place in a hydrogen-containing environment. adversely is that the Pt electrodes are hydrogen are permeable and therefore no effective protection against Form hydrogen damage to the capacitor material.

Basically, there are various possible solutions for the latter problem. From material technology View can be tried to find an electrode material that is not permeable to hydrogen, or a die to find electrical material that is not compared to hydrogen is sensitive. Technologically, anyone can try the, after the formation of the storage capacitor any Pro avoid steps in hydrogen-containing vice exercise. Result in all of these solution variants in practice, however, there are further serious difficulties th.  

The problem has already been tried in the prior art by depositing a hydrogen barrier layer on the Storage capacitor to solve. In the closest U.S. Patent 5,523,595 a manufacturing process for a semiconductor device a ferroelectric storage capacitor. To the structure of the storage capacitor is above this the best hydrogen barrier layer in a CVD process generated from TiON. The barrier layer will Penetration of hydrogen through the top Pt electrode of the Storage capacitor prevented. The disadvantage, however, is that penetration of hydrogen through the lower Pt electrode and a lateral penetration of hydrogen into the ferro electrical are still possible. Complete protection of the capacitor ferroelectric against degradation there is therefore no hydrogen.

JP 9-219498 A (US 6 048 764) describes a method for producing a ferroelectric memory device described, at wel chem after making a selection transistor on a Semiconductor substrate in a planarizing insulation layer Nitrogen atoms diffused through a plasma with the aim become a protective layer against one later in the course of the Process to form etching attack with hydrofluoric acid. Above this protective layer there is a selection transi stor connected storage capacitor formed.

The invention has for its object a method for Specify manufacture of a semiconductor device, at wel chem a storage capacitor that is a ferroelectric or Paraelectric capacitor material used, sufficient is protected against the ingress of hydrogen.  

The problem underlying the invention is by the characterizing features of claim 1 ge solves.

An essential aspect of the invention is that to protect against hydrogen intrusion into the Capacitor material is deposited over the capacitor Oxide layer is doped with a barrier material. Through the Atoms introduced into the oxide layer become the doped oxide layer largely impermeable to Hydrogen.  

So the term "endowment" is not a contribution here foreign atoms to change the conductivity (so-called. p- or n-doping) but the introduction of foreign atoms to reduce the diffusibility of hydrogen (in an oxide layer).

According to the invention, a first doped oxide layer above the capacitor forms. Another improvement is remove a thin second oxide layer under the capacitor divorce and also to endow them.

In this case, a procedure is identified variant in that the first doped oxide layer and the second doped oxide layer around the capacitor on all sides conclude.

The barrier material is preferably a stick material. In this case, the doping becomes a nitride Realization of the first or second oxide layer realized. Gene However, other suitable substances, e.g. B. noble gases, can be used as a barrier material.

The oxide layers are doped (or nitrided) with the help of a plas containing the barrier material ma-discharge. The plasma discharge enables that in short Time (about 60 s) a sufficiently high barrier material concentration tration generated in the first and / or second oxide layer without a maximum substrate temperature in the loading range of 50-120 ° C must be exceeded. The plasma Doping is therefore compatible with conventional photoresist Masking techniques. Accordingly, an advantageous one is identified  Process sequence in that before the plasma Doping on the first and optionally second oxide layer Mask is applied, by means of which the doping of the O oxide layer is structured, and that subsequently an oxide Etching step is carried out. This ensures that at the oxide etching step (i.e., as in the conventional case without hydrogen barrier) only oxide layers rich must be etched. When using z. B. one TiON barrier layers, however, would have to have alternative etching procedures Ren to remove this layer in areas (to avoid this, this layer is in the one U.S. Patent above mentioned above Connection level arranged, which in turn makes their effectiveness is reduced), and when using sandwich layers (e.g. nitride oxide multilayers) would be due to the changing layer composition undercuts or over slopes in the area of the layer transitions that occur at subsequent process steps (e.g. filling one etched contact hole) are extremely disruptive.

In the case of the oxide etching of a contact hole with a previously applied (lacquer) mask an advantageous process variant in that the created structure one more time of plasma doping exposed with barrier fabric. In this process the hole walls of the contact hole are doped (e.g. nitrided). The advantage of this measure is that now too no hydrogen through through the hole walls of the contact hole can occur and diffuse to the capacitor material. This is important because especially during the subsequent filling the contact hole, for example with tungsten (W), relative large amounts of hydrogen are released.  

The plasma doping can expediently either by a PIII (plasma immersion ion implantation) procedure or brought about by a PLAD (so-called plasma doping) process become. Both of the methods mentioned enable the targeted Setting an isotropic ("plasma cloud") and ani sotropic ("ballistic implantation") doping component in Dependence on the selected process parameters. By the increase in the isotropic doping component can be for example, irregular surface topologies (e.g. Trenches, holes, etc.) evenly doped.

Further advantageous measures are in the subclaims specified.

The invention is described below with reference to exemplary embodiments play explained with reference to the drawing; in this shows:

Fig. 1 is a cross-sectional view for explaining two known in the prior art, ge suitable for the application of the inventive method construction concepts of a memory cell; and

FIGS. 2A-E Querschittsansichten a semiconductor device according to the invention according to any one of the design concepts shown in Fig. 1 in un terschiedlichen stages of the method according to the invention.

With reference to FIG. 1, two per se known design concepts are discussed for memory cells in which the erfindungsge Permitted method can be put to use, respectively. The two design concepts have in common that a switching transistor S1, S2 is formed in a lower level directly on a semiconductor substrate 1 and a storage capacitor K1, K2 is arranged in an upper level, the two levels being separated from one another by an intermediate insulation layer 4 .

According to the first design concept (“stacked cell”), the switching transistor S1 and the storage capacitor K1 are essentially arranged directly one above the other, the lower electrode 31 of the storage capacitor S1 having a contact hole 41 (“plug”) filled with a conductive material Drain region 21 of the MOS transistor S1, 2 is electrically connected through the insulation layer 4.

According to the second design concept ("offset cell"), the switching transistor S2 and the storage capacitor K2 are arranged offset from one another, the upper electrode 33 of the storage capacitor K2 being electrically connected to the drain region 21 of the MOS transistor S2, 2 through two contact holes is.

In Fig. 1, both construction concepts are shown ver for the sake of simplicity in a single component.

The following is the component structure and its manufacture explained in more detail using the "stacked cell". The Be spelling is mostly over to the "offset cell" portable. Comparable components of the "offset cell" are there marked here with the same reference numerals.  

On a semiconductor substrate 1 , the MOS transistor 2 already mentioned is first produced by forming the dram region 21 and a source region 23 by an n- or p-doping, between which there is a channel which is formed by a the channel arranged gate 22 can be controlled in its Leit ability. The gate 22 can be formed by a word line WL of the memory component or can be connected to it. The source region 23 is connected to a bit line BL of the memory component.

The MOS transistor 2 is then covered with the planarizing insulation layer 4 , for example an oxide layer.

A storage capacitor 3 is formed on the first insulation layer 4 . For this purpose, the contact hole 41 is first etched into the first insulation layer 4 and filled with a conductive material, for example polycrystalline silicon. The lower electrode 31 is then applied over the filled contact hole 41 (possibly separated from the “plug” by a barrier layer, not shown).

A dielectric layer 32 of a ferroelectric or paraelectric material, for example by MOCVD or by a sputtering method, is deposited on the lower electrode 31 . The dielectric layer 32 forms the capacitor dielectric. An upper electrode 33 is deposited over the entire surface above the dielectric layer 32 . The structure obtained is finally covered with a further planarizing insulation layer 5 , for example likewise consisting of SiO ₂ .

In the upper insulation layer 5 , a further contact hole 51 is formed through which the upper electrode 33 of the storage capacitor 3 can be connected by means of a suitable conductive material to an external electrical connection P (common capacitor plate).

Finally, the source region 23 of the MOS transistor 2 is connected to the bit line BL by forming a contact hole 45 extending through both insulation layers 4 and 5 and filling it with a conductive material.

In the "offset cell" structure shown in the right part of FIG. 1, a contact hole 46 comparable to the contact hole 45 is formed in order to cover the drain region 21 of the MOS transistor S2 by means of a conductive cross connection 8 and another to connect the upper insulation layer 5 extending contact hole 52 to the upper electrode 33 of the storage capacitor S2, 2.

With both construction concepts, it is therefore necessary to fill a plurality of contact holes 41 , 51 , 45 , 46 , 52 with an electrically conductive contact hole material. In particular with smaller structure sizes, tungsten (W) deposited in a CVD process is well suited as contact hole material. However, the problem arises that the W deposition in the CVD (chemical vapor deposition) process takes place in a hydrogen-containing atmosphere, the hydrogen can penetrate the Pt electrodes 31 , 33 and it due to the catalytic properties of the platinum can damage the capacitor material 32 .

Is z. B. SBT as a ferroelectric capacitor material, there is damage to this material by the reduction of BiO _x . Similar damage mechanisms exist for other metal oxide-containing capacitor materials, which are also due to the penetration of hydrogen and the catalytic effect of Pt (or other inert electrode materials).

2A to 2E in the following the example of the "offset cell" is reference to FIGS. Explains how through the invention Ver the plasma-assisted drive doping the penetration of hydrogen into the Kondensa can be suppressed door material 32 of one or more oxide layers. For easier explanation, nitrogen is assumed to be the barrier material and process steps which have already been explained in connection with the prior art shown in FIG. 1 are partially omitted.

After the completion of the switching transistor S2 (the word line WL and the drain region 21 thereof are shown in FIGS . 2A to 2E), the deposition of the first insulation layer 4 already explained with reference to FIG. 1 is first carried out according to FIG. 2A by means of conventional techniques. To form a flat surface, the insulation layer 4 is subsequently planarized by CMP (chemical mechanical polishing).

In a subsequent step, the insulation layer 4 is coated with egg ner lacquer mask layer, which then z. B. is structured by pho tolithographic means. This ensures that a mask structure 6 remains at the point at which the contact hole 46 is later to be formed.

The low-temperature nitriding step according to the invention is then carried out. The nitridization step takes place at a substrate temperature of 50 to a maximum of 120 ° C and is therefore compatible with the photomask technology used. The plasma nitridation has the effect that nitrogen atoms are installed in the first insulation layer 4 outside the mask structure 6 in a region near the surface. The thus created nitrided surface portion of the first insulating layer 4 is denoted by the reference numeral 7. A.

While in the "stacked cell" concept, the contact hole 41 is first formed, filled, see ver with a barrier layer and then the storage capacitor K1 is realized, the storage capacitor K2 is now immediately implemented in the exemplary embodiment of the "offset cell" concept shown here built up. For this purpose, the lower Pt electrode 31 is first applied to the nitrided surface area 7 A of the first insulation layer 4 . Then the dielectric cal, in particular para- or ferroelectric layer 32 , consisting for example of BST or other suitable Ma material such. B. SBTN, PZT, BTO etc., deposited.

The upper Pt electrode 33 is then deposited on the dielectric layer 32 and structured together with the dielectric layer 32 by photolithography and etching technology. The deposition and structuring of the dielectric layer 32 and of the upper Pt electrode 33 is preferably carried out in such a way that both layers extend at least on one side of the lower electrode 31 in a lateral direction and lie in the form of a step on the lower electrode 31 , The effective capacitor area is increased by the step area.

This structure is then layered with a thin second oxide z. B. coated with SiO ₂ .

In the following, photoresist mask structures 9.1 and 9.2 are produced on the second oxide layer at suitable locations by lithography. The mask structure 9.2 is preferably attached centrally over the storage capacitor K2. The Mas 9.1 kenstruktur layer covers a portion of the second oxide, which is located immediately above the non-nitrided region of the first nitrided oxide layer 7 A.

The thin second oxide layer is then also subjected to plasma nitridization. Depending on the layer thickness of the second oxide layer and the process parameters used during nitridization, the latter is nitrided in its entire thickness or only in a region close to the surface. The nitridized second oxide layer 7 B shown in FIG. 2B is formed, which further consists of non-nitrided oxide material below the photoresist mask structures 9.1 and 9.2 .

The planarizing upper insulation layer 5 , preferably also an SiO ₂ layer, is then deposited over the structure described. Can take place in this process, the pation under BETEI of hydrogen, the capacitor 3 is already protected by the second nitrided oxide layer 7 B ge.

The two contact holes 46 and 52 are then etched. On the basis of the structuring of the nitridized oxide layers 7 A and 7 B generated by the maskings 6 , 9.1 and 9.2 , both contact holes 46 and 52 can be formed by conventional oxide etching. It is not necessary to etch different layer materials. Consequently, the contact holes 46 and 52 have extremely dimensionally stable and flat inner wall surfaces, which favors a lateral structural reduction. The contact holes 46 , 52 can be formed together in a single etching step or in two individual etching steps.

According to Fig. 2D can now a third plasma Nitridisierungs step are performed. In this case, surface near inner wall surface areas 7 C of the two contact holes 46 and 52 and a surface area of the upper insulation layer 5 are nitrided.

The contact holes 46 and 52 are then filled with a suitable conductive material, for example W, in the manner already described. Thereafter, a CMP step to create a planar surface can be performed in a manner not shown.

Finally, an electrical connection is made between the source region 21 and the upper capacitor electrode 33 by producing the conductive cross connection 8 over the two contact holes 46 and 52 , see FIG. 2E.

The following are two ways to nitridize the different oxide layers in nitrogen plasma. Both methods are related to the n- or p-dotie tion of silicon with suitable dopants known.

The PIII procedure is usually carried out in one out of two existing system. In one chamber becomes a constantly burning nitrogen plasma of a high Generates plasma density. To check the plasma density, a magnetic field can be used.  

The substrate with the oxide layers to be nitrided is located in the other chamber. The two chambers are connected by a pinhole. A voltage is now applied to the substrate for a short time, as a result of which nitrogen ions are extracted from the plasma, accelerated through the pinhole on the substrate 1 and braked in the respective exposed oxide layer.

By setting the plasma and extraction conditions can the degree of anisotropy of nitridation to a large extent to be influenced. At a high extraction voltage occurs anisotropic ion implantation. For example, by lowering the Extraction voltage, increase in plasma density as well a change in the geometric relationships can be achieved be that the nitridization by an extensive "Plas ma cloud "is effected. In this case, an even Nitridization of the oxide layers even with irregular O surface topologies accessible and it has been shown that Contact holes with an opening ratio up to about 1:12 can be nitrided in full length without problems.

The PLAD process is usually done in a single Plasma chamber performed. The plant is similar to a sput ter system built. One is between two electrodes High frequency voltage applied and a nitrogen plasma ge ignites. The substrate is on the electrode towards which the nitrogen ions are accelerated. The System works like a reversed polarity sputter system.

The degree of anisotropy of the Nitridization through the system geometry and the configuration tion of the nitrogen plasma can be set as desired.  

A typical nitridation dose in the range from 10 ¹⁹ to 10 ²² atoms / cm ^{2 can be} set with both methods. Typical nitridation energies (kinetic energy of the accelerated nitrogen ions when they hit the oxide layers) are in the range of 1 to 12 keV. In both methods, it is also possible to successively build up a desired thickness of the nitrided oxide layer region by changing the nitridization energy during the nitridization step. The nitridation process then begins at the highest nitridation energy and ends at the lowest nitridization energy. The duration of the entire nitriding step is typically about 60 seconds at a nitriding dose of 10 ²⁰ atoms / cm ² .

Claims (10)

1. A method for producing a semiconductor device, in which
a first insulation layer ( 4 ) is created over a substrate; and
Above the first insulation layer ( 4 ), a capacitor containing a lower and an upper electrode ( 31 , 33 ) and a metal oxide-containing capacitor material layer ( 32 ) deposited between them is formed;
characterized by
that an oxide layer ( 7 B) is generated over the capacitor ( 3 ); and
that the oxide layer ( 7 B) is doped using a plasma doping method with a hydrogen diffusion barrier in the oxide layer ( 7 B) building barrier material. 2. The method according to claim 1, characterized in that before the formation of the capacitor ( 3 ) an oxide layer ( 7 A), in particular a surface layer of the first insulation layer ( 4 ), using a plasma doping process with a hydrogen diffusion barrier in the oxide layer ( 7 A) building barrier substance is doped. 3. The method according to claim 1 or 2, characterized in that the first doped oxide layer ( 7 B) and the second do oxide layer ( 7 A) close the capacitor ( 3 ) on all sides. 4. The method according to any one of the preceding claims, characterized, that the barrier material is nitrogen. 5. The method according to any one of the preceding claims, characterized in
that a mask ( 6 ; 9.1 , 9.2 ) is applied to the first ( 4 ) and / or second oxide layer before the plasma doping, by means of which the doping of the oxide layer is structured; and
that an oxide etching step is subsequently carried out. 6. The method according to claim 5, characterized in that after the oxide etching step, by means of which a contact hole ( 45 , 46 , 51 , 52 ) is generated, the structure created a further time using the plasma doping method with the Barrier material for doping the contact hole walls is doped. 7. The method according to any one of the preceding claims, characterized, that the doping is carried out by means of a PIII method leads. 8. The method according to any one of the preceding claims, characterized,  that the doping is carried out using a PLAD method leads. 9. The method according to any one of the preceding claims, characterized in that the barrier substance dose in the plasma doping of the first ( 4 ) and / or the second oxide layer is in the range from 10 ¹⁹ to 10 ²² atoms / cm ² . 10. The method according to any one of the preceding claims, characterized, that in plasma doping a barrier substance implant tion energy in the range of 1 to 12 keV is used.