CN2704927Y - 可同时具有部分空乏晶体管与完全空乏晶体管的芯片 - Google Patents

可同时具有部分空乏晶体管与完全空乏晶体管的芯片 Download PDF

Info

Publication number
CN2704927Y
CN2704927Y CNU2004200483757U CN200420048375U CN2704927Y CN 2704927 Y CN2704927 Y CN 2704927Y CN U2004200483757 U CNU2004200483757 U CN U2004200483757U CN 200420048375 U CN200420048375 U CN 200420048375U CN 2704927 Y CN2704927 Y CN 2704927Y
Authority
CN
China
Prior art keywords
mentioned
transistor
gate
chip
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNU2004200483757U
Other languages
English (en)
Inventor
杨育佳
陈豪育
黄健朝
李文钦
杨富量
胡正明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Application granted granted Critical
Publication of CN2704927Y publication Critical patent/CN2704927Y/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H01L29/7854Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners

Abstract

本实用新型主要提出两种不同型态的完全空乏晶体管,并且将完全空乏晶体管与部分空乏晶体管整合于单一芯片上。可透过调整栅极层的长度,以决定平面晶体管是完全空乏或是部分空乏。完全空乏晶体管的栅极层长度较部分空乏晶体管的栅极层长度为长。或是透过调整晶体管主动区的宽度,以决定晶体管是完全空乏或是部分空乏。完全空乏晶体管的主动区宽度较部分空乏晶体管的主动区宽度为窄。不断地减少主动区的宽度,可以形成一多重栅极晶体管,当该多重栅极晶体管的主动区宽度减少至小于空乏区宽度的两倍时,该多重栅极晶体管便是完全空乏。如此一来,在单一芯片上就可同时制备完全空乏晶体管与部分空乏晶体管。

Description

可同时具有部分空乏晶体管与完全空乏晶体管的芯片
技术领域
本实用新型是有关于一种半导体集成电路,且特别是有关于一种可同时具有部分空乏晶体管与完全空乏晶体管的芯片。
背景技术
随着半导体集积度的增加,半导体组件的尺寸必须随的缩小。而为了提供更良好的组件性能,绝缘层上覆硅(silicon on insulator;SOI)的半导体基底被提出来,绝缘层上覆硅(semiconductor on insulator;SOI)的集成电路组件是将传统的组件(active devices)设置于一绝缘层上有半导体层的晶圆(silicon on insulator wafer)上,上述晶圆例如为一绝缘层上有硅的晶圆(silicon on insulator wafer)。绝缘层上覆硅(SOI)具有以下优点(1)降低短通道效应(Short Channel Effect)(2)消除闭锁现象(Latch up Effect)(3)降低寄生汲极/源极电容(ParasiticSource/Drain Capacitance)(4)减少软错效应(Soft Error Effect)(5)降低基材漏电流(Substrate Leakage Current)(6)制程简化容易与硅晶制程兼容等等。因此,借由SOI技术可形成具有较佳速度表现、较高积集度以及较低消耗功率的集成电路组件。
绝缘层上覆硅(SOI)又可分为部分空乏绝缘层上覆硅(partially-depleted SOI)与完全空乏绝缘层上覆硅(fully-depletedSOI)两种。部分空乏金氧半导体场效应晶体管(metal-oxide-semiconductor field effect transistors;MOSFET)的通道区厚度大于最大空乏层宽度,而部分空乏金氧半导体场效应晶体管(metal-oxide-semiconductor field effect transistors;MOSFET)的通道区厚度小于最大空乏层宽度。部分空乏金氧半导体场效应晶体管(PDMOSFET)的电荷载子会累积在汲极/源极附近的通道区下方硅层基底内,造成通道区电位改变,而产生浮体效应(floating body effect),进而造成电流的突变(kink),导致组件功能退化。
改善浮体效应的方法的一为将通道区下方的硅层基底外接一电性导体,以搜集冲击离子化(impact ionization)所产生的电流,针对这方面技术已有许多方法被提出来,但仍有许多缺点有待改进。美国专利第4946799号与第6387739号都是揭示有关改善浮体效应的方法。
克服浮体效应的另一种有效方法,便是采用完全空乏金氧半导体场效应晶体管(FD MOSFET)。
美国专利第6222234号提供一种于单一基底上制作完全空乏金氧半导体场效应晶体管(FD MOSFET)与部分空乏金氧半导体场效应晶体管(PDMOSFET)的方法。
美国专利第6414355号与第6448114号都揭示有关于厚度不均匀的绝缘层上覆硅基底的半导体技术。
美国专利第6448114号更是揭示将完全空乏金氧半导体场效应晶体管(FD MOSFET)制作于一厚度较薄的硅层基底,而部分空乏金氧半导体场效应晶体管(PD MOSFET)则制作于一厚度较厚的硅层基底。
然而,完全空乏金氧半导体场效应晶体管的硅层基底厚度较薄或被施以离子掺杂。制作完全空乏金氧半导体场效应晶体管(FD MOSFET)需要选择性磊晶(selective epitaxy),技术尚未发展成熟,不仅良率不佳,并且价格昂贵,急需发展更佳的制造技术。
有鉴于此,为了解决上述问题,本实用新型主要目的在于提供一种可同时具有部分空乏晶体管与完全空乏晶体管的芯片,可适用于绝缘层上覆硅基底的单一芯片。
发明内容
本实用新型的目的之一在于提供一种可同时具有部分空乏晶体管与完全空乏晶体管的芯片,具有新的完全空乏晶体管结构,以提供良好的组件功能。
本实用新型主要提出两种不同型态的完全空乏晶体管,并且将完全空乏晶体管与部分空乏晶体管整合于单一芯片上。
本实用新型的第一主要特征在于透过调整栅极层的长度,以决定平面晶体管是完全空乏或是部分空乏。完全空乏晶体管的栅极层长度较部分空乏晶体管的栅极层长度为长。如此一来,在单一芯片上就可同时制备完全空乏晶体管与部分空乏晶体管。
为获致上述的目的,本实用新型提出一种可同时具有部分空乏晶体管与完全空乏晶体管的芯片,主要是包括:
一半导体基底;一完全空乏平面晶体管,具有一长栅极层,且设置于上述半导体基底上;以及一部分空乏平面晶体管,具有一短栅极层,且设置于上述半导体基底上;其中上述长栅极层的长度大于上述短栅极层。
如前所述,上述半导体基底可由一依序堆栈的一第一硅层、一绝缘层与一第二硅层所构成。
如前所述,上述完全空乏平面晶体管下方的上述第二硅层具有浓度大体为1016~1018cm-3的掺杂物,而上述部分空乏平面晶体管下方的上述第二硅层具有浓度大体为1018~2*1019cm-3的掺杂物。
如前所述,上述完全空乏平面晶体管的上述长栅极层的长度大于宽度,而上述部分空乏平面晶体管的上述短栅极层的宽度大于长度。
如前所述,上述第二硅层的厚度大体为10~2000。
如前所述,上述完全空乏平面晶体管的上述长栅极层的长度大体为120~1000nm,而上述部分空乏平面晶体管的上述短栅极层的长度大体为9~100nm。
如前所述,本实用新型的芯片更包括:一多重栅极晶体管,设置于上述半导体基底上方。上述多重栅极晶体管可以为完全空乏,上述多重栅极晶体管的宽度小于70nm。
本实用新型的第二主要特征在于透过调整晶体管主动区的宽度,以决定晶体管是完全空乏或是部分空乏。完全空乏晶体管的主动区宽度较部分空乏晶体管的主动区宽度为窄。不断地减少主动区的宽度,可以形成一多重栅极晶体管,当该多重栅极晶体管的主动区宽度减少至小于空乏区宽度的两倍时,该多重栅极晶体管便是完全空乏。如此一来,在单一芯片上就可同时制备完全空乏晶体管与部分空乏晶体管。
为获致上述的目的,本实用新型提出一种可同时具有部分空乏晶体管与完全空乏晶体管的芯片,主要包括:
一半导体基底;以及一多重栅极晶体管,设置于上述半导体基底上。上述多重栅极晶体管,包括:
一鳍形半导体层,位于上述半导体基底上,其中上述鳍形半导体层具有一源极、一汲极以及位于上述源极和上述汲极之间的一通道区,且上述鳍形半导体层中具有一应变;
一栅极介电层,位于上述鳍形半导体层的上述通道区表面;以及
一栅极电极,位于上述栅极介电层上,并包覆对应于上述通道区的上述鳍形半导体层的两侧壁和一顶面;其中,上述鳍形半导体层的宽度小于空乏区最大宽度的两倍。
如前所述,本实用新型的芯片包括:一平面晶体管,设置于上述半导体基底上。上述平面晶体管可以为完全空乏,也可以为部分空乏。当上述平面晶体管为完全空乏,则具有一长栅极层,且上述长栅极层的长度大于宽度,上述长栅极层的长度大体为120~1000nm。当上述平面晶体管为部分空乏,则具有一短栅极层,且上述短栅极层的长度小于宽度,上述短栅极层的长度大体为9~100nm。
根据本实用新型,上述多重栅极晶体管为完全空乏,上述鳍形半导体层的宽度小于70nm。上述鳍形半导体层的厚度大体为20~1000。
如前所述,上述多重栅极晶体管更可包括:一应力膜层,位于上述源极和上述汲极上。上述应力膜层的材质可包括氮化硅。
如前所述,上述鳍形半导体层可具有圆滑化的上部边角(roundedcorner),上述圆滑化的上部边角的半径大体为200。
如前所述,上述鳍形半导体层中的上述应变为沿上述源极至上述汲极方向的拉伸应变。上述鳍形半导体层中的上述拉伸应变量为0.1%至2%。
如前所述,上述栅极介电层的材质例如为氧化硅、氮氧化硅、或相对电容率(relative permittivity)大于5的介电材质。上述相对电容率大于5的介电材质可以为氧化铝(Al2O3)、氧化铪(HfO2)、氮氧化硅铪(HfSiNxOy)、硅化铪(HfSi4)、氧化锆(ZrO2)、硅化锆(ZrSi4)或氧化镧(La2O3)。
如前所述,上述栅极介电层的等效氧化层厚度例如为3~100。上述鳍形半导体层的侧壁的上述栅极介电层的厚度可以不同于顶部的厚度,例如:上述鳍形半导体层的侧壁的上述栅极介电层的厚度小于顶部的厚度,则上述鳍形半导体层的顶部的上述栅极介电层的等效氧化层厚度约小于20。
如前所述,上述栅极电极为一金属、一金属硅化物或一金属氮化物,其材质包括一多晶硅或一多晶锗。
如前所述,上述多重栅极晶体管更包括:一间隔物,设置于上述栅极电极沿上述汲极与上述源极方向的两侧壁上。上述间隔物沿着上述汲极与上述源极的延伸宽度大体为500。
如前所述,上述栅极电极的栅极长度小于65nm。
如前所述,本实用新型的芯片更包括:一隔离区,包围于上述多重栅极晶体管周围,以提供电性隔离。上述隔离区是可以由一绝缘物所构成,则上述鳍形半导体层表面与上述隔离区表面的高度差大体为200~400。上述隔离区也可以借由一平台式隔离达成电性隔离,则上述鳍形半导体层表面与上述平台式隔离表面的高度差大体为200~400。
合并前述第一主要特征与第二主要特征,本实用新型又提出一种可同时具有部分空乏晶体管与完全空乏晶体管的芯片,主要包括:
一半导体基底;一平面晶体管,设置于上述半导体基底上;以及一多重栅极晶体管,设置于上述半导体基底上。上述多重栅极晶体管包括:
一鳍形半导体层,位于上述半导体基底上,其中上述鳍形半导体层具有一源极、一汲极以及位于上述源极和上述汲极之间的一通道区,且上述鳍形半导体层中具有一应变;
一栅极介电层,位于上述鳍形半导体层的上述通道区表面;以及
一栅极电极,位于上述栅极介电层上,并包覆对应于上述通道区的上述鳍形半导体层的两侧壁和一顶面。
附图说明
图1是显示本实用新型的可同时具有部分空乏晶体管与完全空乏晶体管的芯片的立体图;
图2A与图2B是显示不同主动区宽度的晶体管的电性分析结果;
图3A与图3B是显示不同主动区宽度与不同通道长度之下,部分空乏晶体管与完全空乏晶体管之间的关系示意图。
符号说明:
108~半导体基底
120~部分空乏平面晶体管
130~完全空乏平面晶体管
140~多重栅极晶体管
122a、122b、122c~栅极层
124a、124b、124c~栅极介电层
126a、126b、126c~间隔物
S/D~汲极/源极
102~第一硅层
104~绝缘层
106~第二硅层
106a~鳍形半导体层
150~应力膜层
STI~隔离区
106b、106c~图案化第二硅层
具体实施方式
为使本实用新型的上述目的、特征和优点能更明显易懂,下文特举较佳实施例,并配合附图,作详细说明如下:
本实用新型将一部分空乏绝缘层上覆硅与一完全空乏绝缘层上覆硅晶体管同时整合于一芯片上,并且增大应变效应,以改善超大(ultra-scaled)集成电路的载子迁移率(carrier mobility)与组件功能。
本实用新型提供两种不同结构的完全空乏晶体管,利用两种手段1.调整信道的长度并且配合调整通道掺杂的浓度,2.调整主动区的宽度,来达成备制部分空乏(PD)晶体管与完全空乏(FD)晶体管于单一芯片上,如此一来,就可以在一厚度薄的硅层上,制备出部分空乏晶体管与完全空乏晶体管。
以下将配合图1的立体图,详细说明本实用新型的可同时具有部分空乏晶体管与完全空乏晶体管的芯片的结构。
根据本实用新型的芯片主要包括:一半导体基底102、设置于半导体基底102上的至少一平面晶体管120、130、设置于半导体基底102上的一多重栅极晶体管140。其中,平面晶体管120、130可以为部分空乏晶体管120,也可以为完全空乏晶体管130。多重栅极晶体管140是为完全空乏晶体管。
部分空乏平面晶体管120如同一般习知平面晶体管,包括:设置于半导体基底102上的一栅极层122b、设置于栅极层122b与半导体基底102之间的一栅极介电层124b、设置于栅极层122b侧壁的一间隔物(spacer)126b以及形成于栅极层122b外侧的半导体基底102表面的汲极与源极S/D。栅极层122b的长度小于宽度。栅极层122b的长度大体为40~60nm。
根据本实用新型的第一主要技术特征,即延长栅极层122b的长度,可使平面晶体管由部分空乏转变成完全空乏。便获得完全空乏平面晶体管130,包括:设置于半导体基底102上的一栅极层122c、设置于栅极层122c与半导体基底102之间的一栅极介电层124c、设置于栅极层122c侧壁的一间隔物126b以及形成于栅极层122c外侧的半导体基底102表面的汲极与源极S/D。完全空乏平面晶体管130的栅极层120c长度较部分空乏平面晶体管120的栅极层122b长度为长。栅极层120c的长度大于宽度。栅极层120c的长度大体为120~1000nm。值得注意的是,这里所指的栅极层长度,是指与沿着汲极经由信道(channel)至源极的方向相互平行的方向的尺寸,即为图1中的LL’方向的尺寸,也就是熟知此技艺人士所指的通道长度。
另外,半导体基底102是由一依序堆栈的一第一硅层102、一绝缘层104与一第二硅层106所构成。绝缘层104例如为埋入式氧化硅层,第二硅层106的厚度大体为10~2000。完全空乏平面晶体管130下方的第二硅层106具有浓度大体为1016~1018cm-3的掺杂物,而部分空乏平面晶体管120下方的第二硅层106具有浓度大体为1018~2*1019cm-3的掺杂物。
根据本实用新型的第二主要特征,缩窄晶体管主动区的宽度,可使平面晶体管由部分空乏转变成完全空乏。便获得完全空乏平面晶体管140,包括:一鳍形半导体层106a、一栅极介电层124a、一栅极电极122a、一汲极与源极S/D以及一间隔物126a。其中,鳍形半导体层106a,位于半导体基底102上,其中鳍形半导体层106a具有一源极/汲极S/D以及位于源极/汲极S/D之间的一通道区。另外,栅极介电层124a,位于鳍形半导体层122a的通道区表面。并且,栅极电极122a,位于栅极介电层124a上,并包覆对应于通道区的鳍形半导体层122a的两侧壁和一顶面。完全空乏多重栅极晶体管140的宽度(也就是其主动区宽度)较部分空乏平面晶体管120的宽度为窄。值得注意的是,这里所指的晶体管宽度,是指与前述栅极层长度同一平面且垂直于栅极层长度方向的空间尺寸,即为图1中的WW’方向的尺寸。当多重栅极晶体管140的主动区宽度减少至小于其空乏区最大宽度的两倍时,则多重栅极晶体管140便是完全空乏。
根据本实用新型的完全空乏多重栅极晶体管140,鳍形半导体层106a的宽度小于70nm。并且,多重栅极晶体管140更包括:一应力膜层150,位于源极和汲极S/D上,使源极和汲极S/D具有一应变,其中应力膜层150的材质包括氮化硅,此应变可为沿上述源极至上述汲极方向的拉伸应变,拉伸应变量约为0.1%至2%。鳍形半导体层106a具有圆滑化的上部边角(rounded corner),其厚度大体为20~1000,圆滑化的上部边角的半径大约为200。再者,栅极介电层124a的材质例如为氧化硅、氮氧化硅、或相对电容率(relative permittivity)大于5的介电材质,其中相对电容率大于5的介电材质包括氧化铝(Al2O3)、氧化铪(HfO2)、氮氧化硅铪(HfSiNxOy)、硅化铪(HfSi4)、氧化锆(ZrO2)、硅化锆(ZrSi4)或氧化镧(La2O3)。栅极介电层124a的等效氧化层厚度可为3~100。并且,鳍形半导体层106a的侧壁的栅极介电层124a的厚度可以不同于顶部的厚度,鳍形半导体层106a的侧壁的栅极介电层124a的厚度最好小于顶部的厚度,顶部的栅极介电层124a的等效氧化层厚度例如小于20。再者,栅极电极122a可为一金属、一金属硅化物或一金属氮化物,其材质包括一多晶硅或一多晶锗,其长度约小于65nm。另外,多重栅极晶体管140更包括:一间隔物126a,设置于栅极电极140沿汲极与源极S/D方向的两侧壁上,其宽度大约为500。
根据本实用新型的芯片上更包括:材质例如为绝缘物的一隔离区(STI),包围各晶体管120、130、140周围,以提供电性隔离,而隔离区(STI)可以由一绝缘物所构成,本实用新型的多重栅极晶体管140周围的隔离区(STI)绝缘层厚度可以较其它区域隔离区绝缘物为薄,使得鳍形半导体层106a表面与隔离区(STI)表面的高度差大约为200~400,甚至多重栅极晶体管140隔离区的绝缘物可以完全去除,再此定义为一平台式隔离(mesa isolation),而在后段制程制作内联机线时,会填入内层介电层,以达成电性隔离,如此鳍形半导体层106a表面与平台式隔离表面的高度差大体为200~400。
如此一来,在单一芯片上就可同时制备完全空乏晶体管130、140与部分空乏晶体管120,而完全空乏晶体管可以由具有长栅极层的平面晶体管130所构成,也可以由具有窄主动区宽度的多重栅极晶体管140所构成。为了清楚起见,本实施例的芯片共包括了3种型态晶体管,并非一芯片必须同时皆包括此3种型态晶体管,熟知此技艺人士可视实际需求调整芯片上前述晶体管的种类数及其组合,例如:单一芯片包括一部分空乏平面晶体管与一完全空乏平面晶体管、单一芯片包括一部分空乏平面晶体管与一完全空乏多重栅极晶体管或单一芯片包括一部分空乏平面晶体管、完全空乏平面晶体管与一完全空乏多重栅极晶体管等,在此并不加以设限。
以下请参照图1,说明本实用新型的可同时具有部分空乏晶体管与完全空乏晶体管的芯片的一较佳实施例。
首先提供一半导体基底102,可以为一半导体层/绝缘层迭置型基底,例如为一硅层/氧化硅层迭置型基底(silicon on insulator substrate;SOI substrate)108,其包括一第一硅层102、一绝缘层104和一第二硅层106,其中绝缘层104例如为埋入式氧化硅层。在此实施例中是以该种型式的基底为例,当然半导体层的材质和绝缘层的材质并不限定于此,例如硅锗亦可做为半导体层。
接着,于第二硅层106中预计形成平面晶体管120、130的区域定义出主动区硅层106b、106c,且在预计形成多重栅极晶体管140的区域定义出鳍形硅层(silicon fins)106a,以做为通道层之用。其中鳍形硅层106a的宽度小于70nm,高度约为20~1000。完全空乏平面晶体管130的栅极层长度约为120~1000nm。并且第二硅层106被施以掺杂物。预计形成完全空乏平面晶体管130的第二硅层106c具有浓度大体为1016~1018cm-3的掺杂物,而预计形成部分空乏平面晶体管120的第二硅层106b具有浓度大体为1018~2*1019cm-3的掺杂物。部分空乏平面晶体管120的栅极层122b的长度大约为9~100nm。完全空乏平面晶体管130的栅极层120c的长度大体为120~1000nm,定义主动区时需做应对调整。
定义第二硅层106的方法例如是于第二硅层106上形成一罩幕层,并以该罩幕层为蚀刻罩幕,以将该罩幕层的图案转移至其下方的第二硅层106中。此罩幕层可为光阻层(photoresist layer)、能量敏感层(energysensitive layer)、氧化硅层、氮化硅层、或其它材质的罩幕层。
接着,可对鳍形硅层106a进行侧表面平滑化处理,以降低鳍形硅层106a侧表面的粗糙度。侧表面平滑化处理的方法为牺牲性氧化处理和侧壁处理,其中侧壁处理的方法例如是在1000℃含氢(H2)的环境下进行高温回火。当鳍形硅层106a的侧表面经牺牲性氧化处理时,会于表面氧化生成一层氧化硅,借此修复表面于蚀刻过程中所受到的伤害,并将上部边角圆滑化,再将氧化硅移除。表面平滑化的目的在于使组件具有好的载子迁移率,以及利于后续形成可靠度佳的栅极介电层。将鳍形半导体层106a上部边角圆滑化I,可以避免因为应力集中于角落所导致缺陷传播和延伸的问题,可以使栅极电流稳定。缺陷可能是由于制程不良率或组件退化所产生的。
接着,将具有干净且平整表面的图案化第二硅层106a、106b、106c上方的罩幕层移除。移除的方法可为电浆蚀刻或湿蚀刻,湿蚀刻所使用的蚀刻剂可为稀释的氢氟酸(DHF)。在此蚀刻过程中,图案化第二硅层106a、106b、106c底部可能发生底切(undercut)或凹槽(notch)。
接着,形成一浅沟槽隔离物(shallow trench isolation;STI)于图案化硅层106a、106b、106c周围的半导体基底102表面。例如先全面性以适当沉积法,例如化学气相沉积(chemical vapor deposition;CVD)形成一材质例如为氧化物的隔离物于半导体基底102表面,然后经过化学机械研磨与选择性蚀刻,将部分隔离物去除,仅留下平面晶体管120、130、140的图案化硅层106a、106b、106c周围隔离物,以做为晶体管之间的浅沟槽隔离物(STI),其中多重栅极晶体管140周围的隔离物STI厚度较其它区域隔离区绝缘物为薄,使得鳍形半导体层106a表面与隔离区(STI)表面的高度差大约为200~400,甚至多重栅极晶体管140隔离区的绝缘物可以完全去除,以平台式隔离(mesa isolation)做电性隔离。
接着,分别于图案化第二硅层106a、106b、106c表面形成一层栅极介电层124a、124b、124c,平面晶体管120、130的栅极介电层124b、124c是形成于图案化第二硅层106b、106c顶部,而多重栅极介电层140的栅极介电层124a形成于鳍形硅层106a的顶部与侧壁,其形成方法例如是热氧化法、化学气相沉积法、溅镀等,其材质可为氧化硅、或氮氧化硅。通常,鳍形硅层106a的侧壁和顶部的栅极介电层124a具有不同的厚度,通常是顶部的栅极介电层124a的厚度较侧壁为厚,其厚度约为3埃至100埃,较佳的是10埃以下,顶部部分的厚度较佳的是20埃以下;或者为高介电常数的材质,例如氧化铝(Al2O5)、氧化铪(HfO2)、氧化锆(ZrO2)、或其它类似此性质者,其等效氧化层厚度(equivalent oxidethickness)约为3至100埃。
接着,形成一层导电层于栅极介电层124a、124b、124c上,其材质可为多晶硅、多晶硅锗、耐火金属(refractory metal)、类金属化合物、或其它导电材质,其中耐火金属可为钼(Mo)、钨(W)等,类金属化合物可为氮化钛。
接着,于导电层上覆盖一图案化罩幕层,并借由蚀刻,将图案化罩幕层的图案转移至导电层中,以形成栅极电极122a、122b、122c,平面晶体管120、130的栅极层122b、122c形成于栅极介电层124b、124c上方,而多重栅极晶体管140的栅极层122a则形成于栅极介电层124a上,并包覆对应于通道区的鳍形半导体层106a的两侧壁和一顶面。以材质为多晶硅的导电层以及材质为氮氧化硅的栅极介电层124a、124b、124c为例,其蚀刻条件例如是含氯和溴的蚀刻气体进行电浆蚀刻,其多晶硅对氮氧化硅的蚀刻选择比超过2000。
在完成栅极电极122a、122b、122c的定义后,则移除其上方的图案化罩幕层。
接着,进行源极/汲极的淡掺杂制程,其形成方法例是以离子植入、电浆侵入式离子植入(plasma immersion ion implantation,PIII)、或是其它的技术来进行。
接着,借由沉积以及选择性非等向性地蚀刻介电材质,以于栅极电极122a、122b、122c的侧壁形成间隙壁126a、126b、126c,间隙壁126的材质可为氮化硅或氧化硅。之后进行源极/汲极的浓掺杂制程,其形成方法例是以离子植入、电浆侵入式离子植入、固体源扩散(solid sourcediffusion)、或是其它的技术。在此步骤中,亦可以根据需要,同时将离子掺杂入栅极电极122a、122b、122c,借此提高其导电性。任何植入的伤害或非晶化可借由后续高温回火制程而获得改善。经过上述的源极/汲极的淡掺杂制程和浓掺杂制程后,于栅极电极122a、122b、122c两侧的图案化第二硅层106a、106b、106c中形成具有浅掺杂汲极结构(lightlydoped drain)LDD的源极/汲极S/D。并且,平面晶体管120、130的图案化硅层106b、106c的通道区可以施以一super halo布植,由于部分空乏晶体管120的信道长度短,所以信道两侧的super halo布植区域会在信道中间区域重达。
接着,为了降低源极/汲极S/D的片电阻,可以在源极/汲极S/D表面形成一层导电层,意即,此导电层形成于鳍形硅层106a的顶部和侧壁以及图案化硅层106b、106c的汲极/源极S/D表面。导电层的材质例如是以自动对准金属硅化物制程(self-aligned silicide process,salicideprocess)形成的金属硅化物,例如硅化钴。该材质亦可为金属、多晶硅、或是磊晶硅。
之后,沉积一层高应力膜层150覆盖于多重栅极晶体管140的栅极电极122a上,其厚度约为50~1000埃。由于鳍形硅层106a和高应力膜层150两者之间的热膨胀系数(thermal expansion coefficient)及杨氏系数(Young’s modulus)有很大的差异,使得在经过半导体制程中所需的高温沉积或热回火制程后,高应力膜层150自高温降温时的收缩速度和鳍形硅层106a的收缩速度会有很大的差异,因此会将应力导入鳍形硅层106a的通道区中,产生的应力可能是数百MPa甚至超过1GPa。
如果高应力膜层150的热膨胀系数小于鳍形硅层106a,则鳍形硅层106a会感受到压缩应变(compressive strain)。若高应力膜层150施与通道区的应变为压缩应变,则电洞载子的迁移率可获得提升。因此,覆盖于高应力膜层150下方的栅极电极122a和源极/汲极S/D构成的晶体管为PMOS晶体管。上述的应变是指沿源极至汲极方向的压缩应变,鳍形硅层106a中的压缩应变强度为0.1%至2%,较佳的是1%至2%,应力约为-500~1500MPa,,其中负值代表是一压缩应力,则正值代表是一拉伸应力。
如果高应力膜层150的热膨胀系数大于鳍形硅层26a,则鳍形硅层106a会感受到拉伸应变(tensile strain)。若高应力膜层150施与通道区的应变为拉伸应变,则电子和电洞载子两者的迁移率均可获得提升。因此,覆盖于高应力膜层150下方的栅极电极122a和源极/汲极S/D构成的晶体管可为PMOS晶体管和NMOS晶体管。上述的应变是指沿源极至汲极方向的拉伸应变,鳍形硅层106a中的拉伸应变强度为0.1%至2%,较佳的是1%至2%。
就高应力膜层150而言,借由控制形成的条件,可以调整所形成的膜层的应力大小,根据研究,可控制应力的因素有温度、压力或制程气体的流速比。举例而言,利用电浆增强型化学气相沉积的氮化硅(plasma-enhanced chemical vapor deposited silicon nitride)可以导入至通道区中的应力可为拉伸应力或压缩应力,端视沉积的条件而定。此外,若选择氧化硅制备高应力膜层150,还可以借由改变掺杂的物质及掺杂的浓度来改变其热膨胀系数及杨氏系数,可以掺杂的物质例如是锗(Ga)、氮(N)或耐火的金属(refractory metal)。
发明功效:
当主动区的宽度W越小,则应力膜层与鳍状半导体基底接触的面积则越大,因此,应力效应会随着主动区宽度W的减少而增强。如图2A与图2B所示,当主动区宽度W由1200nm(图2A)减少至110nm(图2B),在晶体管关闭状态(off-state)下,漏电流(leakage)约为300nA/mm,应变感应驱动电流由10%增加到17%。
关于通道长度、主动区宽度与完全空乏晶体管、部分空乏晶体管之间的关系,经由实验,得到以下结果。图3A与图3B是显示部分空乏晶体管与完全空乏晶体管的主动区宽度W与通道长度Lg的关系示意图。图3A是一N型晶体管的实验结果,平面部分空乏晶体管与平面完全空乏晶体管的主动区大于50nm,而非平面式多重栅极完全空乏晶体管的主动区宽度小于50nm。图3B是一P型晶体管的实验结果。在主动区宽度固定的情况下,欲将部分空乏晶体管转变成完全空乏晶体管的方法为增加栅极长度。另外,当主动区宽度小于50nm以下,便会形成多重栅极晶体管。第3B图中P型晶体管可形成部分空乏的范围较第3A图中N型晶体管可形成部分空乏的范围为小。这是因为P形晶体管中的冲击离子化引发寄生双极化反应(impact ionization induced parasitic bipolar action)较弱。
发明优点:
1.根据本实用新型的具有长通道的完全空乏平面晶体管或多重栅极完全空乏晶体管皆可有效克服浮体效应(floating body effect)的问题。
2.根据本实用新型的多重栅极晶体管,可视为三个并联的晶体管,分别位于鳍形硅层两侧及顶面。该结构可有效提高组件的电流量,并且无须缩短通道长度,可以有效控制短通道效应(short-channel effect)。
3.根据本实用新型的应力膜层,可使应力导入通道区中,以提高载子的迁移率,进而提升组件的操作效能。
4.本实用新型的具有多重栅极及应变的通道层的晶体管,借由其垂直型的结构,使晶体管的积集度可以有效地提升。

Claims (15)

1.一种可同时具有部分空乏晶体管与完全空乏晶体管的芯片,其特征在于所述芯片包括:
一半导体基底;
一完全空乏平面晶体管,具有一长栅极层,且设置于上述半导体基底上;以及
一部分空乏平面晶体管,具有一短栅极层,且设置于上述半导体基底上;
其中上述长栅极层的长度大于上述短栅极层。
2.根据权利要求1所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片,其特征在于:上述完全空乏平面晶体管的上述长栅极层的长度大于宽度。
3.根据权利要求1所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片,其特征在于:上述部分空乏平面晶体管的上述短栅极层的宽度大于长度。
4.根据权利要求1所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片,其特征在于:上述完全空乏平面晶体管的上述长栅极层的长度为120~1000nm。
5.根据权利要求1所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片,其特征在于:上述部分空乏平面晶体管的上述短栅极层的长度为9~100nm。
6.根据权利要求1所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片,其特征在于所述芯片更包括:一多重栅极晶体管,设置于上述半导体基底上方。
7.根据权利要求6所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片,其特征在于上述多重栅极晶体管包括:
一鳍形半导体层,位于上述半导体基底上,其中上述鳍形半导体层具有一源极、一汲极以及位于上述源极和上述汲极之间的一通道区,且上述鳍形半导体层中具有一应变;
一栅极介电层,位于上述鳍形半导体层的上述通道区表面;以及
一栅极电极,位于上述栅极介电层上,并包覆对应于上述通道区的上述鳍形半导体层的两侧壁和一顶面。
8.根据权利要求7所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片,其特征在于所述芯片更包括:一应力膜层,位于上述源极和上述汲极上。
9.根据权利要求7所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片,其特征在于:上述鳍形半导体层具有圆滑化的上部边角。
10.根据权利要求7所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片,其特征在于:上述鳍形半导体层中的上述应变为沿上述源极至上述汲极方向的拉伸应变。
11.根据权利要求7所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片,其特征在于:上述鳍形半导体层的侧壁的上述栅极介电层的厚度不同于顶部的厚度。
12.根据权利要求7所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片,其特征在于:上述鳍形半导体层的侧壁的上述栅极介电层的厚度小于顶部的厚度。
13.根据权利要求7所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片,其特征在于所述芯片更包括:一间隔物,设置于上述栅极电极沿上述汲极与上述源极方向的两侧壁上。
14.根据权利要求7所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片,其特征在于所述芯片更包括:一隔离区,包围于上述多重栅极晶体管周围,以提供电性隔离。
15.根据权利要求14所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片,其特征在于:上述隔离区是借由一平台式隔离达成电性隔离。
CNU2004200483757U 2003-04-30 2004-04-23 可同时具有部分空乏晶体管与完全空乏晶体管的芯片 Expired - Lifetime CN2704927Y (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/426,566 2003-04-30
US10/426,566 US6867433B2 (en) 2003-04-30 2003-04-30 Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

Publications (1)

Publication Number Publication Date
CN2704927Y true CN2704927Y (zh) 2005-06-15

Family

ID=33309898

Family Applications (2)

Application Number Title Priority Date Filing Date
CNB031565328A Expired - Lifetime CN1293635C (zh) 2003-04-30 2003-09-03 可同时具有部分耗尽晶体管与完全耗尽晶体管的芯片及其制作方法
CNU2004200483757U Expired - Lifetime CN2704927Y (zh) 2003-04-30 2004-04-23 可同时具有部分空乏晶体管与完全空乏晶体管的芯片

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CNB031565328A Expired - Lifetime CN1293635C (zh) 2003-04-30 2003-09-03 可同时具有部分耗尽晶体管与完全耗尽晶体管的芯片及其制作方法

Country Status (4)

Country Link
US (2) US6867433B2 (zh)
CN (2) CN1293635C (zh)
SG (1) SG143035A1 (zh)
TW (1) TWI255043B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1293635C (zh) * 2003-04-30 2007-01-03 台湾积体电路制造股份有限公司 可同时具有部分耗尽晶体管与完全耗尽晶体管的芯片及其制作方法
CN108028276A (zh) * 2015-09-25 2018-05-11 英特尔公司 晶体管沟道区域界面的钝化

Families Citing this family (231)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6503783B1 (en) * 2000-08-31 2003-01-07 Micron Technology, Inc. SOI CMOS device with reduced DIBL
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
KR100483425B1 (ko) * 2003-03-17 2005-04-14 삼성전자주식회사 반도체소자 및 그 제조 방법
US7812340B2 (en) * 2003-06-13 2010-10-12 International Business Machines Corporation Strained-silicon-on-insulator single-and double-gate MOSFET and method for forming the same
US6992354B2 (en) * 2003-06-25 2006-01-31 International Business Machines Corporation FinFET having suppressed parasitic device characteristics
US6909151B2 (en) * 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7078742B2 (en) * 2003-07-25 2006-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel semiconductor structure and method of fabricating the same
US7301206B2 (en) * 2003-08-01 2007-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
US8008136B2 (en) * 2003-09-03 2011-08-30 Advanced Micro Devices, Inc. Fully silicided gate structure for FinFET devices
JP2005086024A (ja) * 2003-09-09 2005-03-31 Toshiba Corp 半導体装置及びその製造方法
KR100555518B1 (ko) * 2003-09-16 2006-03-03 삼성전자주식회사 이중 게이트 전계 효과 트랜지스터 및 그 제조방법
US7612416B2 (en) * 2003-10-09 2009-11-03 Nec Corporation Semiconductor device having a conductive portion below an interlayer insulating film and method for producing the same
WO2005038931A1 (ja) * 2003-10-20 2005-04-28 Nec Corporation 半導体装置及び半導体装置の製造方法
US6946377B2 (en) * 2003-10-29 2005-09-20 Texas Instruments Incorporated Multiple-gate MOSFET device with lithography independent silicon body thickness and methods for fabricating the same
US7888201B2 (en) * 2003-11-04 2011-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
US6962843B2 (en) * 2003-11-05 2005-11-08 International Business Machines Corporation Method of fabricating a finfet
US7247534B2 (en) * 2003-11-19 2007-07-24 International Business Machines Corporation Silicon device on Si:C-OI and SGOI and method of manufacture
US7105390B2 (en) * 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US7268058B2 (en) * 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
KR100585131B1 (ko) * 2004-02-20 2006-06-01 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR100532353B1 (ko) * 2004-03-11 2005-11-30 삼성전자주식회사 핀 전계 효과 트랜지스터 및 그 제조방법
US6872640B1 (en) * 2004-03-16 2005-03-29 Micron Technology, Inc. SOI CMOS device with reduced DIBL
KR100540478B1 (ko) * 2004-03-22 2006-01-11 주식회사 하이닉스반도체 전하 트랩을 갖는 게이트유전체를 포함한 휘발성 메모리셀 트랜지스터 및 그 제조 방법
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7321155B2 (en) * 2004-05-06 2008-01-22 Taiwan Semiconductor Manufacturing Co., Ltd. Offset spacer formation for strained channel CMOS transistor
US7361973B2 (en) * 2004-05-21 2008-04-22 International Business Machines Corporation Embedded stressed nitride liners for CMOS performance improvement
US7579280B2 (en) * 2004-06-01 2009-08-25 Intel Corporation Method of patterning a film
JP2006012898A (ja) * 2004-06-22 2006-01-12 Toshiba Corp 半導体装置及びその製造方法
US6984564B1 (en) * 2004-06-24 2006-01-10 International Business Machines Corporation Structure and method to improve SRAM stability without increasing cell area or off current
TWI463526B (zh) * 2004-06-24 2014-12-01 Ibm 改良具應力矽之cmos元件的方法及以該方法製備而成的元件
JP2006013303A (ja) * 2004-06-29 2006-01-12 Toshiba Corp 半導体装置及びその製造方法
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
JP2006019578A (ja) * 2004-07-02 2006-01-19 Toshiba Corp 半導体装置及びその製造方法
KR100618852B1 (ko) * 2004-07-27 2006-09-01 삼성전자주식회사 높은 동작 전류를 갖는 반도체 소자
KR100555569B1 (ko) 2004-08-06 2006-03-03 삼성전자주식회사 절연막에 의해 제한된 채널영역을 갖는 반도체 소자 및 그제조방법
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7009250B1 (en) * 2004-08-20 2006-03-07 Micron Technology, Inc. FinFET device with reduced DIBL
US7271453B2 (en) * 2004-09-20 2007-09-18 International Business Machines Corporation Buried biasing wells in FETS
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7332439B2 (en) * 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7361958B2 (en) 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US20060086977A1 (en) * 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7193254B2 (en) * 2004-11-30 2007-03-20 International Business Machines Corporation Structure and method of applying stresses to PFET and NFET transistor channels for improved performance
DE102004057762B4 (de) * 2004-11-30 2010-11-11 Advanced Micro Devices Inc., Sunnyvale Verfahren zur Herstellung einer Halbleiterstruktur mit Ausbilden eines Feldeffekttransistors mit einem verspannten Kanalgebiet
US7393733B2 (en) * 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
US7198993B2 (en) 2004-12-13 2007-04-03 Texas Instruments Incorporated Method of fabricating a combined fully-depleted silicon-on-insulator (FD-SOI) and partially-depleted silicon-on-insulator (PD-SOI) devices
US7297577B2 (en) * 2004-12-30 2007-11-20 Sony Corporation SOI SRAM device structure with increased W and full depletion
US7193279B2 (en) * 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
US7256081B2 (en) * 2005-02-01 2007-08-14 International Business Machines Corporation Structure and method to induce strain in a semiconductor device channel with stressed film under the gate
US7224033B2 (en) * 2005-02-15 2007-05-29 International Business Machines Corporation Structure and method for manufacturing strained FINFET
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
KR100578818B1 (ko) 2005-02-24 2006-05-11 삼성전자주식회사 핀 전계 효과 트랜지스터 및 이의 형성 방법
US20060202266A1 (en) * 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
US7410840B2 (en) * 2005-03-28 2008-08-12 Texas Instruments Incorporated Building fully-depleted and bulk transistors on same chip
US7410841B2 (en) * 2005-03-28 2008-08-12 Texas Instruments Incorporated Building fully-depleted and partially-depleted transistors on same chip
US20060228872A1 (en) * 2005-03-30 2006-10-12 Bich-Yen Nguyen Method of making a semiconductor device having an arched structure strained semiconductor layer
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
CN101300663B (zh) * 2005-05-17 2010-12-01 台湾积体电路制造股份有限公司 具有降低了的位错缺陷密度的晶格失配的半导体结构和相关的器件制造方法
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US20070267722A1 (en) * 2006-05-17 2007-11-22 Amberwave Systems Corporation Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US7858481B2 (en) * 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US8105908B2 (en) * 2005-06-23 2012-01-31 Applied Materials, Inc. Methods for forming a transistor and modulating channel stress
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
CN101268547B (zh) * 2005-07-26 2014-07-09 琥珀波系统公司 包含交替有源区材料的结构及其形成方法
US7402875B2 (en) 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US7326617B2 (en) * 2005-08-23 2008-02-05 United Microelectronics Corp. Method of fabricating a three-dimensional multi-gate device
US7606066B2 (en) 2005-09-07 2009-10-20 Innovative Silicon Isi Sa Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same
US7638842B2 (en) * 2005-09-07 2009-12-29 Amberwave Systems Corporation Lattice-mismatched semiconductor structures on insulators
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US20070090408A1 (en) * 2005-09-29 2007-04-26 Amlan Majumdar Narrow-body multiple-gate FET with dominant body transistor for high performance
US8513066B2 (en) * 2005-10-25 2013-08-20 Freescale Semiconductor, Inc. Method of making an inverted-T channel transistor
US7452768B2 (en) * 2005-10-25 2008-11-18 Freescale Semiconductor, Inc. Multiple device types including an inverted-T channel transistor and method therefor
US7575975B2 (en) * 2005-10-31 2009-08-18 Freescale Semiconductor, Inc. Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer
US7655511B2 (en) 2005-11-03 2010-02-02 International Business Machines Corporation Gate electrode stress control for finFET performance enhancement
KR100653712B1 (ko) * 2005-11-14 2006-12-05 삼성전자주식회사 핀펫에서 활성영역과 실질적으로 동일한 상면을 갖는소자분리막이 배치된 반도체 장치들 및 그 형성방법들
KR100720510B1 (ko) * 2005-11-18 2007-05-22 동부일렉트로닉스 주식회사 반도체 소자의 트랜지스터 및 그 형성방법
KR100660327B1 (ko) * 2005-11-18 2006-12-22 동부일렉트로닉스 주식회사 반도체 소자의 트랜지스터 및 그 형성방법
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US7396711B2 (en) * 2005-12-27 2008-07-08 Intel Corporation Method of fabricating a multi-cornered film
US7473593B2 (en) * 2006-01-11 2009-01-06 International Business Machines Corporation Semiconductor transistors with expanded top portions of gates
JP4490927B2 (ja) * 2006-01-24 2010-06-30 株式会社東芝 半導体装置
US7456055B2 (en) 2006-03-15 2008-11-25 Freescale Semiconductor, Inc. Process for forming an electronic device including semiconductor fins
US7419866B2 (en) * 2006-03-15 2008-09-02 Freescale Semiconductor, Inc. Process of forming an electronic device including a semiconductor island over an insulating layer
WO2007112066A2 (en) * 2006-03-24 2007-10-04 Amberwave Systems Corporation Lattice-mismatched semiconductor structures and related methods for device fabrication
US7365401B2 (en) * 2006-03-28 2008-04-29 International Business Machines Corporation Dual-plane complementary metal oxide semiconductor
US7449373B2 (en) * 2006-03-31 2008-11-11 Intel Corporation Method of ion implanting for tri-gate devices
US7492632B2 (en) 2006-04-07 2009-02-17 Innovative Silicon Isi Sa Memory array having a programmable word length, and method of operating same
US20070249127A1 (en) * 2006-04-24 2007-10-25 Freescale Semiconductor, Inc. Electronic device including a semiconductor layer and a sidewall spacer and a process of forming the same
US7670895B2 (en) * 2006-04-24 2010-03-02 Freescale Semiconductor, Inc Process of forming an electronic device including a semiconductor layer and another layer adjacent to an opening within the semiconductor layer
US7491622B2 (en) * 2006-04-24 2009-02-17 Freescale Semiconductor, Inc. Process of forming an electronic device including a layer formed using an inductively coupled plasma
WO2007128738A1 (en) 2006-05-02 2007-11-15 Innovative Silicon Sa Semiconductor memory cell and array using punch-through to program and read same
US7573108B2 (en) * 2006-05-12 2009-08-11 Micron Technology, Inc Non-planar transistor and techniques for fabricating the same
US7528078B2 (en) * 2006-05-12 2009-05-05 Freescale Semiconductor, Inc. Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer
US8069377B2 (en) 2006-06-26 2011-11-29 Micron Technology, Inc. Integrated circuit having memory array including ECC and column redundancy and method of operating the same
US7542340B2 (en) 2006-07-11 2009-06-02 Innovative Silicon Isi Sa Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same
US7462916B2 (en) * 2006-07-19 2008-12-09 International Business Machines Corporation Semiconductor devices having torsional stresses
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
KR100751803B1 (ko) * 2006-08-22 2007-08-23 삼성전자주식회사 반도체 소자의 제조 방법
US7790540B2 (en) 2006-08-25 2010-09-07 International Business Machines Corporation Structure and method to use low k stress liner to reduce parasitic capacitance
WO2008030574A1 (en) 2006-09-07 2008-03-13 Amberwave Systems Corporation Defect reduction using aspect ratio trapping
WO2008036256A1 (en) * 2006-09-18 2008-03-27 Amberwave Systems Corporation Aspect ratio trapping for mixed signal applications
WO2008039495A1 (en) * 2006-09-27 2008-04-03 Amberwave Systems Corporation Tri-gate field-effect transistors formed by aspect ratio trapping
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
WO2008051503A2 (en) 2006-10-19 2008-05-02 Amberwave Systems Corporation Light-emitter-based devices with lattice-mismatched semiconductor structures
US20080128797A1 (en) * 2006-11-30 2008-06-05 International Business Machines Corporation Structure and method for multiple height finfet devices
US20080157225A1 (en) * 2006-12-29 2008-07-03 Suman Datta SRAM and logic transistors with variable height multi-gate transistor architecture
US8558278B2 (en) * 2007-01-16 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Strained transistor with optimized drive current and method of forming
US20080173942A1 (en) * 2007-01-22 2008-07-24 International Business Machines Corporation STRUCTURE AND METHOD OF MANUFACTURING A STRAINED FinFET WITH STRESSED SILICIDE
KR101277402B1 (ko) * 2007-01-26 2013-06-20 마이크론 테크놀로지, 인코포레이티드 게이트형 바디 영역으로부터 격리되는 소스/드레인 영역을 포함하는 플로팅-바디 dram 트랜지스터
US7399664B1 (en) * 2007-02-28 2008-07-15 International Business Machines Corporation Formation of spacers for FinFETs (Field Effect Transistors)
US7452758B2 (en) * 2007-03-14 2008-11-18 International Business Machines Corporation Process for making FinFET device with body contact and buried oxide junction isolation
US7960234B2 (en) * 2007-03-22 2011-06-14 Texas Instruments Incorporated Multiple-gate MOSFET device and associated manufacturing methods
WO2009031052A2 (en) 2007-03-29 2009-03-12 Innovative Silicon S.A. Zero-capacitor (floating body) random access memory circuits with polycide word lines and manufacturing methods therefor
DE102007015504B4 (de) * 2007-03-30 2014-10-23 Advanced Micro Devices, Inc. SOI-Transistor mit Drain- und Sourcegebieten mit reduzierter Länge und einem dazu benachbarten verspannten dielektrischen Material und Verfahren zur Herstellung
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
WO2008124154A2 (en) 2007-04-09 2008-10-16 Amberwave Systems Corporation Photovoltaics on silicon
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US8064274B2 (en) 2007-05-30 2011-11-22 Micron Technology, Inc. Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
US8085594B2 (en) 2007-06-01 2011-12-27 Micron Technology, Inc. Reading technique for memory cell with electrically floating body transistor
US8736016B2 (en) * 2007-06-07 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Strained isolation regions
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
KR101093588B1 (ko) 2007-09-07 2011-12-15 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 멀티-정션 솔라 셀
WO2009039169A1 (en) * 2007-09-17 2009-03-26 Innovative Silicon S.A. Refreshing data of memory cells with electrically floating body transistors
US8115254B2 (en) 2007-09-25 2012-02-14 International Business Machines Corporation Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same
US7910994B2 (en) * 2007-10-15 2011-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for source/drain contact processing
JP5525127B2 (ja) * 2007-11-12 2014-06-18 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
US8492846B2 (en) 2007-11-15 2013-07-23 International Business Machines Corporation Stress-generating shallow trench isolation structure having dual composition
US8536628B2 (en) 2007-11-29 2013-09-17 Micron Technology, Inc. Integrated circuit having memory cell array including barriers, and method of manufacturing same
US8349662B2 (en) 2007-12-11 2013-01-08 Micron Technology, Inc. Integrated circuit having memory cell array, and method of manufacturing same
ES2489615T3 (es) * 2007-12-11 2014-09-02 Apoteknos Para La Piel, S.L. Uso de un compuesto derivado del acido p-hidroxifenil propionico para el tratamiento de la psoriasis
US8773933B2 (en) 2012-03-16 2014-07-08 Micron Technology, Inc. Techniques for accessing memory cells
US8014195B2 (en) 2008-02-06 2011-09-06 Micron Technology, Inc. Single transistor memory cell
US8189376B2 (en) 2008-02-08 2012-05-29 Micron Technology, Inc. Integrated circuit having memory cells including gate material having high work function, and method of manufacturing same
US7943961B2 (en) * 2008-03-13 2011-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Strain bars in stressed layers of MOS devices
US7957206B2 (en) 2008-04-04 2011-06-07 Micron Technology, Inc. Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same
JP5285947B2 (ja) * 2008-04-11 2013-09-11 株式会社東芝 半導体装置、およびその製造方法
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
US20100072515A1 (en) * 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
KR101216541B1 (ko) 2008-09-19 2012-12-31 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 에피텍셜층 과성장에 의한 장치의 형성
US8253211B2 (en) * 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
US7947543B2 (en) 2008-09-25 2011-05-24 Micron Technology, Inc. Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
US7808051B2 (en) * 2008-09-29 2010-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell without OD space effect in Y-direction
US7933140B2 (en) 2008-10-02 2011-04-26 Micron Technology, Inc. Techniques for reducing a voltage swing
US7924630B2 (en) 2008-10-15 2011-04-12 Micron Technology, Inc. Techniques for simultaneously driving a plurality of source lines
US8223574B2 (en) 2008-11-05 2012-07-17 Micron Technology, Inc. Techniques for block refreshing a semiconductor memory device
JP2010118621A (ja) * 2008-11-14 2010-05-27 Nec Electronics Corp 半導体装置及びその製造方法
US8213226B2 (en) 2008-12-05 2012-07-03 Micron Technology, Inc. Vertical transistor memory cell and array
US8227867B2 (en) 2008-12-23 2012-07-24 International Business Machines Corporation Body contacted hybrid surface semiconductor-on-insulator devices
US8319294B2 (en) 2009-02-18 2012-11-27 Micron Technology, Inc. Techniques for providing a source line plane
WO2010102106A2 (en) 2009-03-04 2010-09-10 Innovative Silicon Isi Sa Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
WO2010114890A1 (en) 2009-03-31 2010-10-07 Innovative Silicon Isi Sa Techniques for providing a semiconductor memory device
CN101853882B (zh) * 2009-04-01 2016-03-23 台湾积体电路制造股份有限公司 具有改进的开关电流比的高迁移率多面栅晶体管
JP5705207B2 (ja) * 2009-04-02 2015-04-22 台湾積體電路製造股▲ふん▼有限公司Taiwan Semiconductor Manufacturing Company,Ltd. 結晶物質の非極性面から形成される装置とその製作方法
US8110467B2 (en) * 2009-04-21 2012-02-07 International Business Machines Corporation Multiple Vt field-effect transistor devices
US8139418B2 (en) 2009-04-27 2012-03-20 Micron Technology, Inc. Techniques for controlling a direct injection semiconductor memory device
US8508994B2 (en) 2009-04-30 2013-08-13 Micron Technology, Inc. Semiconductor device with floating gate and electrically floating body
US8498157B2 (en) 2009-05-22 2013-07-30 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US9768305B2 (en) * 2009-05-29 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Gradient ternary or quaternary multiple-gate transistor
US8617976B2 (en) 2009-06-01 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain re-growth for manufacturing III-V based transistors
US8537610B2 (en) 2009-07-10 2013-09-17 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9076543B2 (en) 2009-07-27 2015-07-07 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8629478B2 (en) 2009-07-31 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure for high mobility multiple-gate transistor
US8199595B2 (en) 2009-09-04 2012-06-12 Micron Technology, Inc. Techniques for sensing a semiconductor memory device
US8218353B1 (en) 2009-09-16 2012-07-10 Altera Corporation Memory element circuitry with stressed transistors
CN102034863B (zh) * 2009-09-28 2012-10-31 中芯国际集成电路制造(上海)有限公司 半导体器件、含包围圆柱形沟道的栅的晶体管及制造方法
US9373694B2 (en) 2009-09-28 2016-06-21 Semiconductor Manufacturing International (Shanghai) Corporation System and method for integrated circuits with cylindrical gate structures
US8946028B2 (en) * 2009-10-06 2015-02-03 International Business Machines Corporation Merged FinFETs and method of manufacturing the same
US8138543B2 (en) 2009-11-18 2012-03-20 International Business Machines Corporation Hybrid FinFET/planar SOI FETs
US8174881B2 (en) 2009-11-24 2012-05-08 Micron Technology, Inc. Techniques for reducing disturbance in a semiconductor device
CN101726274B (zh) * 2009-12-01 2011-04-27 中国科学院上海微系统与信息技术研究所 利用mosfet输入输出特性确定mosfet bsim模型参数宽度偏移量的方法
US8455334B2 (en) * 2009-12-04 2013-06-04 International Business Machines Corporation Planar and nanowire field effect transistors
US8310893B2 (en) 2009-12-16 2012-11-13 Micron Technology, Inc. Techniques for reducing impact of array disturbs in a semiconductor memory device
US8765532B2 (en) * 2010-01-11 2014-07-01 International Business Machines Corporation Fabrication of field effect devices using spacers
US8138791B1 (en) 2010-01-27 2012-03-20 Altera Corporation Stressed transistors with reduced leakage
US8416636B2 (en) 2010-02-12 2013-04-09 Micron Technology, Inc. Techniques for controlling a semiconductor memory device
US8576631B2 (en) 2010-03-04 2013-11-05 Micron Technology, Inc. Techniques for sensing a semiconductor memory device
US8411513B2 (en) 2010-03-04 2013-04-02 Micron Technology, Inc. Techniques for providing a semiconductor memory device having hierarchical bit lines
US8369177B2 (en) 2010-03-05 2013-02-05 Micron Technology, Inc. Techniques for reading from and/or writing to a semiconductor memory device
US8278179B2 (en) * 2010-03-09 2012-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. LDD epitaxy for FinFETs
CN102812552B (zh) 2010-03-15 2015-11-25 美光科技公司 半导体存储器装置及用于对半导体存储器装置进行偏置的方法
US8598006B2 (en) * 2010-03-16 2013-12-03 International Business Machines Corporation Strain preserving ion implantation methods
US9312179B2 (en) * 2010-03-17 2016-04-12 Taiwan-Semiconductor Manufacturing Co., Ltd. Method of making a finFET, and finFET formed by the method
US8411524B2 (en) 2010-05-06 2013-04-02 Micron Technology, Inc. Techniques for refreshing a semiconductor memory device
US8378394B2 (en) 2010-09-07 2013-02-19 International Business Machines Corporation Method for forming and structure of a recessed source/drain strap for a MUGFET
US8753942B2 (en) 2010-12-01 2014-06-17 Intel Corporation Silicon and silicon germanium nanowire structures
TWI538215B (zh) * 2011-03-25 2016-06-11 半導體能源研究所股份有限公司 場效電晶體及包含該場效電晶體之記憶體與半導體電路
US8649209B1 (en) * 2011-03-25 2014-02-11 Altera Corporation Memory element circuitry with reduced oxide definition width
US8531878B2 (en) 2011-05-17 2013-09-10 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9559216B2 (en) 2011-06-06 2017-01-31 Micron Technology, Inc. Semiconductor memory device and method for biasing same
KR20150089092A (ko) 2011-09-30 2015-08-04 인텔 코포레이션 비평면 트랜지스터들 및 그 제조 방법들
US8659097B2 (en) 2012-01-16 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Control fin heights in FinFET structures
FR2986369B1 (fr) * 2012-01-30 2016-12-02 Commissariat Energie Atomique Procede pour contraindre un motif mince et procede de fabrication de transistor integrant ledit procede
FR2987959B1 (fr) * 2012-03-06 2014-03-14 Soitec Silicon On Insulator Multiplexeur, table de correspondance et fgpa
US20130237026A1 (en) 2012-03-09 2013-09-12 Taiwan Semiconductor Manufacturing Company, Ltd., ("Tsmc") Finfet device having a strained region
JP6013201B2 (ja) * 2012-03-22 2016-10-25 三菱マテリアル電子化成株式会社 多結晶シリコンインゴット及び多結晶シリコンインゴットの製造方法
CN103378152B (zh) * 2012-04-24 2016-02-17 中芯国际集成电路制造(上海)有限公司 鳍式场效应管及其形成方法
US20130320453A1 (en) * 2012-06-01 2013-12-05 Abhijit Jayant Pethe Area scaling on trigate transistors
US8772117B2 (en) * 2012-12-05 2014-07-08 Globalfoundries Inc. Combination FinFET and planar FET semiconductor device and methods of making such a device
US9142674B2 (en) * 2013-03-15 2015-09-22 GlobalFoundries, Inc. FINFET devices having a body contact and methods of forming the same
US20140264490A1 (en) 2013-03-18 2014-09-18 International Business Machines Corporation Replacement gate electrode with a self-aligned dielectric spacer
US8957478B2 (en) * 2013-06-24 2015-02-17 International Business Machines Corporation Semiconductor device including source/drain formed on bulk and gate channel formed on oxide layer
US9059041B2 (en) 2013-07-02 2015-06-16 International Business Machines Corporation Dual channel hybrid semiconductor-on-insulator semiconductor devices
US9553012B2 (en) * 2013-09-13 2017-01-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and the manufacturing method thereof
US9391202B2 (en) * 2013-09-24 2016-07-12 Samsung Electronics Co., Ltd. Semiconductor device
US9337195B2 (en) 2013-12-18 2016-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US9236397B2 (en) * 2014-02-04 2016-01-12 Globalfoundries Inc. FinFET device containing a composite spacer structure
US9443769B2 (en) 2014-04-21 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap-around contact
JP6537341B2 (ja) * 2014-05-07 2019-07-03 株式会社半導体エネルギー研究所 半導体装置
US9484270B2 (en) 2014-09-16 2016-11-01 International Business Machines Corporation Fully-depleted silicon-on-insulator transistors
US9472575B2 (en) * 2015-02-06 2016-10-18 International Business Machines Corporation Formation of strained fins in a finFET device
US9401334B1 (en) 2015-03-13 2016-07-26 International Business Machines Corporation Preventing unauthorized use of integrated circuits for radiation-hard applications
US9496363B1 (en) 2015-10-14 2016-11-15 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET isolation structure and method for fabricating the same
US20190363135A1 (en) * 2016-09-29 2019-11-28 Intel Corporation Resistive random access memory cell
WO2018063301A1 (en) * 2016-09-30 2018-04-05 Intel Corporation Transistors including source/drain employing double-charge dopants
CN107958873B (zh) * 2016-10-18 2020-11-27 中芯国际集成电路制造(上海)有限公司 鳍式场效应管及其形成方法
TWI736644B (zh) * 2017-06-29 2021-08-21 聯華電子股份有限公司 場效電晶體及元件
FR3070220A1 (fr) * 2017-08-16 2019-02-22 Stmicroelectronics (Crolles 2) Sas Cointegration de transistors sur substrat massif, et sur semiconducteur sur isolant
US20190088766A1 (en) 2017-09-21 2019-03-21 Globalfoundries Inc. Methods of forming epi semiconductor material in source/drain regions of a transistor device formed on an soi substrate
CN109671777B (zh) * 2017-10-13 2021-10-15 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10971402B2 (en) * 2019-06-17 2021-04-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including interface layer and method of fabricating thereof
US11393915B2 (en) 2020-12-09 2022-07-19 Globalfoundries U.S. Inc. Epi semiconductor structures with increased epi volume in source/drain regions of a transistor device formed on an SOI substrate
US11810951B2 (en) 2021-12-16 2023-11-07 Globalfoundries U.S. Inc. Semiconductor-on-insulator field effect transistor with performance-enhancing source/drain shapes and/or materials
CN114121613B (zh) * 2022-01-27 2022-04-22 广东省大湾区集成电路与系统应用研究院 一种改善fdsoi外延生长的薄膜工艺优化方法

Family Cites Families (102)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4069094A (en) 1976-12-30 1978-01-17 Rca Corporation Method of manufacturing apertured aluminum oxide substrates
JPS551103A (en) * 1978-06-06 1980-01-07 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor resistor
US4497683A (en) 1982-05-03 1985-02-05 At&T Bell Laboratories Process for producing dielectrically isolated silicon devices
US4631803A (en) * 1985-02-14 1986-12-30 Texas Instruments Incorporated Method of fabricating defect free trench isolation devices
US4892614A (en) 1986-07-07 1990-01-09 Texas Instruments Incorporated Integrated circuit isolation process
JPH0640583B2 (ja) 1987-07-16 1994-05-25 株式会社東芝 半導体装置の製造方法
US4946799A (en) * 1988-07-08 1990-08-07 Texas Instruments, Incorporated Process for making high performance silicon-on-insulator transistor with body node to source node connection
JPH0394479A (ja) 1989-06-30 1991-04-19 Hitachi Ltd 感光性を有する半導体装置
US5155571A (en) 1990-08-06 1992-10-13 The Regents Of The University Of California Complementary field effect transistors having strained superlattice structure
JP3019430B2 (ja) 1991-01-21 2000-03-13 ソニー株式会社 半導体集積回路装置
US5338960A (en) 1992-08-05 1994-08-16 Harris Corporation Formation of dual polarity source/drain extensions in lateral complementary channel MOS architectures
US5461250A (en) * 1992-08-10 1995-10-24 International Business Machines Corporation SiGe thin film or SOI MOSFET and method for making the same
US5273915A (en) 1992-10-05 1993-12-28 Motorola, Inc. Method for fabricating bipolar junction and MOS transistors on SOI
EP0655785B1 (en) 1993-11-30 2001-10-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and its manufacturing method
JPH0846139A (ja) 1994-05-06 1996-02-16 Texas Instr Inc <Ti> ポリシリコン抵抗器とその作成法
US5534713A (en) * 1994-05-20 1996-07-09 International Business Machines Corporation Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
US5479033A (en) 1994-05-27 1995-12-26 Sandia Corporation Complementary junction heterostructure field-effect transistor
US5447884A (en) * 1994-06-29 1995-09-05 International Business Machines Corporation Shallow trench isolation with thin nitride liner
US6433382B1 (en) 1995-04-06 2002-08-13 Motorola, Inc. Split-gate vertically oriented EEPROM device and process
US5629544A (en) * 1995-04-25 1997-05-13 International Business Machines Corporation Semiconductor diode with silicide films and trench isolation
US5955766A (en) 1995-06-12 1999-09-21 Kabushiki Kaisha Toshiba Diode with controlled breakdown
US5708288A (en) 1995-11-02 1998-01-13 Motorola, Inc. Thin film silicon on insulator semiconductor integrated circuit with electrostatic damage protection and method
US6399970B2 (en) 1996-09-17 2002-06-04 Matsushita Electric Industrial Co., Ltd. FET having a Si/SiGeC heterojunction channel
US5789807A (en) 1996-10-15 1998-08-04 International Business Machines Corporation On-chip power distribution for improved decoupling
US5811857A (en) * 1996-10-22 1998-09-22 International Business Machines Corporation Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications
US5763315A (en) * 1997-01-28 1998-06-09 International Business Machines Corporation Shallow trench isolation with oxide-nitride/oxynitride liner
US5714777A (en) * 1997-02-19 1998-02-03 International Business Machines Corporation Si/SiGe vertical junction field effect transistor
JP4053647B2 (ja) 1997-02-27 2008-02-27 株式会社東芝 半導体記憶装置及びその製造方法
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
DE19720008A1 (de) 1997-05-13 1998-11-19 Siemens Ag Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung
US5894152A (en) 1997-06-18 1999-04-13 International Business Machines Corporation SOI/bulk hybrid substrate and method of forming the same
KR100400808B1 (ko) * 1997-06-24 2003-10-08 매사츄세츠 인스티튜트 오브 테크놀러지 그레이드된 GeSi층 및 평탄화를 사용한 Si상의 Ge의 쓰레딩 전위 밀도 제어
US6221709B1 (en) 1997-06-30 2001-04-24 Stmicroelectronics, Inc. Method of fabricating a CMOS integrated circuit device with LDD N-channel transistor and non-LDD P-channel transistor
US6103599A (en) 1997-07-25 2000-08-15 Silicon Genesis Corporation Planarizing technique for multilayered substrates
EP0923116A1 (en) * 1997-12-12 1999-06-16 STMicroelectronics S.r.l. Process for manufacturing integrated multi-crystal silicon resistors in MOS technology and integrated MOS device comprising multi-crystal silicon resistors
US6100153A (en) 1998-01-20 2000-08-08 International Business Machines Corporation Reliable diffusion resistor and diffusion capacitor
US5972722A (en) 1998-04-14 1999-10-26 Texas Instruments Incorporated Adhesion promoting sacrificial etch stop layer in advanced capacitor structures
JP3265569B2 (ja) * 1998-04-15 2002-03-11 日本電気株式会社 半導体装置及びその製造方法
US6558998B2 (en) * 1998-06-15 2003-05-06 Marc Belleville SOI type integrated circuit with a decoupling capacity and process for embodiment of such a circuit
JP3403076B2 (ja) 1998-06-30 2003-05-06 株式会社東芝 半導体装置及びその製造方法
US6008095A (en) * 1998-08-07 1999-12-28 Advanced Micro Devices, Inc. Process for formation of isolation trenches with high-K gate dielectrics
US6387739B1 (en) * 1998-08-07 2002-05-14 International Business Machines Corporation Method and improved SOI body contact structure for transistors
US6015993A (en) * 1998-08-31 2000-01-18 International Business Machines Corporation Semiconductor diode with depleted polysilicon gate structure and method
JP2000132990A (ja) 1998-10-27 2000-05-12 Fujitsu Ltd 冗長判定回路、半導体記憶装置及び冗長判定方法
US5965917A (en) * 1999-01-04 1999-10-12 Advanced Micro Devices, Inc. Structure and method of formation of body contacts in SOI MOSFETS to elimate floating body effects
US6258664B1 (en) * 1999-02-16 2001-07-10 Micron Technology, Inc. Methods of forming silicon-comprising materials having roughened outer surfaces, and methods of forming capacitor constructions
US6358791B1 (en) * 1999-06-04 2002-03-19 International Business Machines Corporation Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby
US6362082B1 (en) 1999-06-28 2002-03-26 Intel Corporation Methodology for control of short channel effects in MOS transistors
US6339232B1 (en) 1999-09-20 2002-01-15 Kabushika Kaisha Toshiba Semiconductor device
US6303479B1 (en) * 1999-12-16 2001-10-16 Spinnaker Semiconductor, Inc. Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts
US7391087B2 (en) 1999-12-30 2008-06-24 Intel Corporation MOS transistor structure and method of fabrication
US6255175B1 (en) 2000-01-07 2001-07-03 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with minimized parasitic Miller capacitance
TW503439B (en) * 2000-01-21 2002-09-21 United Microelectronics Corp Combination structure of passive element and logic circuit on silicon on insulator wafer
US6475838B1 (en) * 2000-03-14 2002-11-05 International Business Machines Corporation Methods for forming decoupling capacitors
US6281059B1 (en) 2000-05-11 2001-08-28 Worldwide Semiconductor Manufacturing Corp. Method of doing ESD protective device ion implant without additional photo mask
DE10025264A1 (de) 2000-05-22 2001-11-29 Max Planck Gesellschaft Feldeffekt-Transistor auf der Basis von eingebetteten Clusterstrukturen und Verfahren zu seiner Herstellung
JP2001338988A (ja) 2000-05-25 2001-12-07 Hitachi Ltd 半導体装置及びその製造方法
US6969875B2 (en) * 2000-05-26 2005-11-29 Amberwave Systems Corporation Buried channel strained silicon FET using a supply layer created through ion implantation
JP3843708B2 (ja) * 2000-07-14 2006-11-08 日本電気株式会社 半導体装置およびその製造方法ならびに薄膜コンデンサ
US6429061B1 (en) * 2000-07-26 2002-08-06 International Business Machines Corporation Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation
FR2812764B1 (fr) * 2000-08-02 2003-01-24 St Microelectronics Sa Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu
JP2002076287A (ja) 2000-08-28 2002-03-15 Nec Kansai Ltd 半導体装置およびその製造方法
JP4044276B2 (ja) * 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US20020125471A1 (en) 2000-12-04 2002-09-12 Fitzgerald Eugene A. CMOS inverter circuits utilizing strained silicon surface channel MOSFETS
US6414355B1 (en) * 2001-01-26 2002-07-02 Advanced Micro Devices, Inc. Silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness
US6894324B2 (en) * 2001-02-15 2005-05-17 United Microelectronics Corp. Silicon-on-insulator diodes and ESD protection circuits
US6518610B2 (en) 2001-02-20 2003-02-11 Micron Technology, Inc. Rhodium-rich oxygen barriers
US6475869B1 (en) * 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6593181B2 (en) * 2001-04-20 2003-07-15 International Business Machines Corporation Tailored insulator properties for devices
US6586311B2 (en) 2001-04-25 2003-07-01 Advanced Micro Devices, Inc. Salicide block for silicon-on-insulator (SOI) applications
JP2002329861A (ja) 2001-05-01 2002-11-15 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6952040B2 (en) * 2001-06-29 2005-10-04 Intel Corporation Transistor structure and method of fabrication
US6576526B2 (en) 2001-07-09 2003-06-10 Chartered Semiconductor Manufacturing Ltd. Darc layer for MIM process integration
WO2003017336A2 (en) 2001-08-13 2003-02-27 Amberwave Systems Corporation Dram trench capacitor and method of making the same
JP2003124345A (ja) * 2001-10-11 2003-04-25 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
US6521952B1 (en) 2001-10-22 2003-02-18 United Microelectronics Corp. Method of forming a silicon controlled rectifier devices in SOI CMOS process for on-chip ESD protection
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
JP4173658B2 (ja) * 2001-11-26 2008-10-29 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US6657259B2 (en) * 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US6657276B1 (en) 2001-12-10 2003-12-02 Advanced Micro Devices, Inc. Shallow trench isolation (STI) region with high-K liner and method of formation
US6600170B1 (en) 2001-12-17 2003-07-29 Advanced Micro Devices, Inc. CMOS with strained silicon channel NMOS and silicon germanium channel PMOS
US6784101B1 (en) 2002-05-16 2004-08-31 Advanced Micro Devices Inc Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation
WO2003105204A2 (en) * 2002-06-07 2003-12-18 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
US6812103B2 (en) 2002-06-20 2004-11-02 Micron Technology, Inc. Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects
US6617643B1 (en) 2002-06-28 2003-09-09 Mcnc Low power tunneling metal-oxide-semiconductor (MOS) device
JP4376490B2 (ja) 2002-07-19 2009-12-02 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
US6686247B1 (en) 2002-08-22 2004-02-03 Intel Corporation Self-aligned contacts to gates
JP4030383B2 (ja) 2002-08-26 2008-01-09 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US6573172B1 (en) 2002-09-16 2003-06-03 Advanced Micro Devices, Inc. Methods for improving carrier mobility of PMOS and NMOS devices
US6730573B1 (en) 2002-11-01 2004-05-04 Chartered Semiconductor Manufacturing Ltd. MIM and metal resistor formation at CU beol using only one extra mask
US6720619B1 (en) * 2002-12-13 2004-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices
US6919233B2 (en) 2002-12-31 2005-07-19 Texas Instruments Incorporated MIM capacitors and methods for fabricating same
US6921913B2 (en) 2003-03-04 2005-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel transistor structure with lattice-mismatched zone
US6794764B1 (en) 2003-03-05 2004-09-21 Advanced Micro Devices, Inc. Charge-trapping memory arrays resistant to damage from contact hole information
US6762448B1 (en) * 2003-04-03 2004-07-13 Advanced Micro Devices, Inc. FinFET device with multiple fin structures
US6867433B2 (en) * 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US20040266116A1 (en) * 2003-06-26 2004-12-30 Rj Mears, Llc Methods of fabricating semiconductor structures having improved conductivity effective mass
US6891192B2 (en) 2003-08-04 2005-05-10 International Business Machines Corporation Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
US6872610B1 (en) 2003-11-18 2005-03-29 Texas Instruments Incorporated Method for preventing polysilicon mushrooming during selective epitaxial processing
US7224068B2 (en) * 2004-04-06 2007-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Stable metal structure with tungsten plug
US7115974B2 (en) * 2004-04-27 2006-10-03 Taiwan Semiconductor Manfacturing Company, Ltd. Silicon oxycarbide and silicon carbonitride based materials for MOS devices

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1293635C (zh) * 2003-04-30 2007-01-03 台湾积体电路制造股份有限公司 可同时具有部分耗尽晶体管与完全耗尽晶体管的芯片及其制作方法
CN108028276A (zh) * 2015-09-25 2018-05-11 英特尔公司 晶体管沟道区域界面的钝化
US10978568B2 (en) 2015-09-25 2021-04-13 Intel Corporation Passivation of transistor channel region interfaces
CN108028276B (zh) * 2015-09-25 2022-04-26 英特尔公司 晶体管沟道区域界面的钝化

Also Published As

Publication number Publication date
US20050093067A1 (en) 2005-05-05
CN1293635C (zh) 2007-01-03
TW200423403A (en) 2004-11-01
US20040217420A1 (en) 2004-11-04
SG143035A1 (en) 2008-06-27
US7268024B2 (en) 2007-09-11
US6867433B2 (en) 2005-03-15
TWI255043B (en) 2006-05-11
CN1542966A (zh) 2004-11-03

Similar Documents

Publication Publication Date Title
CN2704927Y (zh) 可同时具有部分空乏晶体管与完全空乏晶体管的芯片
CN100345301C (zh) 整合型晶体管及其制造方法
CN1284245C (zh) 使用多栅极晶体管的互补金属氧化物半导体晶体管反向器
CN2751447Y (zh) 多重栅极晶体管
CN1293637C (zh) 具有应变沟道的互补式金属氧化物半导体及其制作方法
US6448613B1 (en) Fabrication of a field effect transistor with minimized parasitic Miller capacitance
CN1503372A (zh) 具有多重闸极及应变的通道层的晶体管及其制造方法
CN107527945B (zh) 外延结构、半导体装置以及其制造方法
CN1674298A (zh) 场效应晶体管
CN1661785A (zh) 场效应晶体管及其制造方法
CN1681103A (zh) 形成有掩埋氧化物图形的半导体器件的方法及其相关器件
CN1147003C (zh) “绝缘体上的硅”半导体装置及其制造方法
JP2007027738A (ja) 半導体装置及びその製作方法
CN101079443A (zh) 半导体装置及其制作方法
CN101604705B (zh) 四周环绕栅极鳍栅晶体管及其制作方法
CN1695254A (zh) 半导体装置及其制造方法
CN1826696A (zh) 在半导体器件中改变载流子迁移率以达到整体设计目标
US11923455B2 (en) Semiconductor device and method of forming the same
JP2003174101A (ja) 半導体装置および半導体装置の製造方法
CN101030541A (zh) 半导体晶体管元件及其制作方法
CN111933529B (zh) 一种沟槽型mosfet的制造方法及其结构
CN1819271A (zh) 硅覆盖绝缘层装置、晶片及其形成方法
CN1812060A (zh) 半导体器件的制造方法
CN1855395A (zh) 用于制造能够改善击穿电压特性的半导体器件的方法
CN1490882A (zh) 半导体器件和半导体器件的制造方法

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
AV01 Patent right actively abandoned

Effective date of abandoning: 20040423

AV01 Patent right actively abandoned

Effective date of abandoning: 20040423

C25 Abandonment of patent right or utility model to avoid double patenting