CN1930671A - 三栅晶体管及其制造方法 - Google Patents

三栅晶体管及其制造方法 Download PDF

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CN1930671A
CN1930671A CNA2005800072795A CN200580007279A CN1930671A CN 1930671 A CN1930671 A CN 1930671A CN A2005800072795 A CNA2005800072795 A CN A2005800072795A CN 200580007279 A CN200580007279 A CN 200580007279A CN 1930671 A CN1930671 A CN 1930671A
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conducting material
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coating
oxide skin
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CN100550324C (zh
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罗伯特·赵
休曼·达塔
布赖恩·多伊尔
B·金
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Intel Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

本发明的实施方案提供用于为绝缘体上硅晶体管制造实现一致硅体高度的方法。对于一个实施方案来说,牺牲氧化物层被设置在半导体衬底上。蚀刻所述氧化物层以形成沟槽。然后用半导体材料填充沟槽。然后以氧化物层的剩余物为基准,平坦化半导体材料,并且然后氧化物层的剩余物被移除。这样被暴露的半导体鳍具有达到在指定容限内的一致高度。

Description

三栅晶体管及其制造方法
领域
本发明的实施方案一般涉及集成电路器件制造的领域并且更具体地涉及三栅晶体管制造。
背景
朝着增加集成电路器件(IC器件)的功能的数量的趋势一直在继续。随着晶体管的尺寸减小,当前晶体管制造工艺中的严重缺点变得明显。例如,典型的绝缘体上硅(SOI)晶体管是通过用绝缘体(例如,玻璃或硅氧化物)层覆盖衬底来制造的。然后,第二硅晶片被结合到绝缘体层并且被薄化到期望厚度(即,由晶体管尺寸确定)。这种薄化工艺非常难以以很大的精确度来控制。
图1A-1D图示根据现有技术用于生成三栅SOI晶体管的部分制造工艺。如图1A中所示,通常为硅衬底的载体晶片(carrier wafer)101具有设置在其上的通常为二氧化硅的绝缘体层102。例如,可以在硅衬底上生长二氧化硅层。
如图1B中所示,然后转移晶片(transfer wafer)103被结合到绝缘体层102,所述绝缘体层102可以帮助结合。可以通过热致氢结合工艺(heat-induced hydrogen bondingprocess)实现载体晶片到绝缘体层的结合。可以是例如硅的转移晶片约为600微米厚。
然后,转移晶片基于晶体管尺寸被薄化到期望厚度。这个厚度通常为约50-100nm。可以通过几种典型工艺中的一种来完成转移晶片的薄化。例如,可以使用湿法蚀刻和抛光工艺研磨转移晶片到期望厚度。用于薄化转移晶片的可替换的方法包括转移层(transferlayer)的氢注入以生成转移晶片的脆弱区域。然后,被结合的对(pair)被加热,以实现氢掺杂界面的高温劈开(cleave)。随后,转移晶片表面被抛光或者以其他方式被处理以平坦化表面或者进一步降低厚度。这些方法提供达到在约几百埃范围内的厚度控制。如图1C中所示,转移晶片103已被薄化到用于晶体管的硅体(silicon body)的期望尺寸,导致薄膜层104。薄膜层104的厚度由硅体的期望高度(Hsi)确定。然后,薄膜层104被选择性地蚀刻以生成用于晶体管的硅体。如图1D中所示,使用光刻技术选择性地蚀刻薄膜层104导致硅体105具有期望体宽度(Wsi)和体高度(Hsi)。
对于典型的晶体管设计结构来说,栅长度与Hsi成比例,其中Hsi等于栅长度的约三分之一。对于栅长度为约20-100nm的典型晶体管来说,期望Hsi大于约20nm。使用当前的制造方法,可能生成合适的薄膜层。但是,随着栅长度并且因此期望Hsi降低,当前的制造方法显示出严重的缺点。
Hsi值必须在整个晶片上一致以生产具有一致特性的晶体管。例如,与Hsi直接成比例的晶体管阈值电压不应该以大于约10%的幅度变化。因此,确定Hsi的薄膜层厚度不应该以大于10%的幅度变化。
薄化转移层以获得薄膜层的方法能够生产约20nm厚度的薄膜层,所述厚度不会以大于约10%的幅度变化。但是,这些方法不能为更薄的薄膜层产生所需要的一致性。因此,当前制造SOI晶体管的方法不能制作栅长度小于约50nm的晶体管。
此外,结合载体晶片与转移晶片的工艺,以及薄化转移晶片到期望厚度的工艺昂贵并且难以控制。
附图说明
通过查阅以下描述和被用来图示本发明的实施方案的附图,本发明可以被最佳地理解。在附图中:
图1A-1D图示根据现有技术用于生成三栅SOI晶体管的工艺;
图2图示根据本发明的一个实施方案,用于提供硅体高度Hsi中增强的一致性的工艺;以及
图3A-3G图示根据本发明的一个实施方案的三栅晶体管的制造。
具体实施方式
在以下描述中,阐述了许多具体的细节。但是,应该理解无需使用这些具体的细节可以实现本发明。此外,公知电路,结构和技术没有以详细方式示出,以免模糊对本文描述的理解。
在整个说明书中提及“一个实施方案”或“实施方案”意味着关于该实施方案描述的特定特征、结构或特性被包括在本发明的至少一个实施方案中。因此,“在一个实施方案中”或“在实施方案中”在整个说明书中不同地方的出现不一定全是指同一实施方案。并且,特定特征,结构或特性可以在一个或更多个实施方案中以任意适当的方式被结合。
此外,发明方面处于比以上所公开的单个实施方案的全部特征少的状态。因此,在具体实施方式之后的的权利要求书特此明确地被并入具体实施方式中,其中每项权利要求独自作为本发明单独的实施方案。
图2图示根据本发明的一个实施方案,用于提供硅体高度Hsi中增强的一致性的工艺。图2中所示的工艺200以操作205开始,在所述操作205中沟槽层被设置在衬底层上。对于一个实施方案来说,可以使用化学气相沉积(CVD)工艺将沟槽层设置在衬底层上。对于一个实施方案来说,衬底层为硅。对于可替换的实施方案来说,衬底层可以是诸如锗(Ge)或砷化镓(GaAs)的另一种半导体材料。对于一个实施方案来说,基于晶体管的栅长度的规格确定沟槽层厚度。即,选择沟槽层厚度等于期望的Hsi值。
在操作210,移除沟槽层被选择的部分,由此形成沟槽。对于一个实施方案来说,沟槽层为可以使用常规蚀刻工艺选择性地蚀刻的材料。对于各种可替换的实施方案来说,沟槽层可以是多个层,每层的材料都与其他层材料不同。在一个这种实施方案中,沟槽层的多个层对不同的蚀刻工艺敏感。
在操作215,用半导体材料(例如,硅)填充由操作210形成的沟槽。对于一个实施方案来说,使用选择性外延工艺用外延硅填充沟槽。在可替换的实施方案中,以一些其他方式填充沟槽。例如,可以使用均厚沉积(Blanket Disposition)工艺用多晶硅填充沟槽。
在操作220,多余的半导体材料被移除。即,延伸到沟槽层剩余物的表面之上的填充沟槽的半导体材料被移除。对于一个实施方案来说,采用化学机械抛光(CMP)来平坦化半导体材料的表面。
在操作225,沟槽层的剩余物被移除以暴露半导体鳍(即,填充沟槽的半导体材料)。对于一个实施方案来说,半导体鳍的高度达到在少于5%的范围内一致。
图3A-3G图示根据本发明的一个实施方案的三栅晶体管的制造。图3A示出硅衬底301。多层沟槽层被设置在硅衬底301上。沟槽层包括第一氧化物(例如,SiO2)层302、氮化物(例如,Si3N4)层303,和第二氧化物(例如,SiO2)层304。三栅体厚度Hsi最终将由非常可控制的第二氧化物层的厚度确定。
图3B图示用来限定晶体管体的光致抗蚀剂掩模层305的应用。光致抗蚀剂掩模层305的图形化确定硅体的宽度Wsi
图3C图示用来限定沟槽306a和306b的沟槽层蚀刻。对于一个实施方案来说,一系列三种不同的干法蚀刻工艺被采用。在这个实施方案中,使用选择性干法蚀刻工艺蚀刻第二氧化物层304,在所述蚀刻工艺中氮化物层303充当蚀刻终止层(etch stop)。然后,使用不同的选择性干法蚀刻工艺蚀刻氮化物层303,在所述蚀刻工艺中第一氧化物层302充当蚀刻终止层。最后,使用干法蚀刻工艺蚀刻第一氧化物层302,所述蚀刻工艺是充分选择性的,以在硅衬底301的表面上终止。
如所指示的,图3D图示光致抗蚀剂层305已被去掉后,用硅307填充沟槽306a和306b。如以上所说明的,可以通过包括多晶硅的外延生长或均厚沉积的各种可替换的方法来用硅填充沟槽。
图3E图示被平坦化到第二氧化物层304的平面(level)的硅307。对于一个实施方案来说,使用CMP工艺实现平坦化。对于一个实施方案来说,使用抛光工艺移除第二氧化物层304并且氮化物层303被用作抛光终止层。对于这个实施方案来说,抛光在氧化物与氮化物之间具有高选择性。对于可替换的实施方案来说,第二氧化物层304被选择性地蚀刻到氮化物层303。随后,使用湿法蚀刻工艺蚀刻氮化物层303,所述蚀刻工艺使用例如磷酸。第一氧化物层302为这种工艺充当蚀刻终止层。
图3F图示用于随着沟槽层(例如,第二氧化物层304和氮化物层303)的移除而暴露的三栅晶体管的硅体。如图3F中所示,沟槽层的部分(例如,第一氧化物层302)可以被保留以实现下面所解释的晶体管的有利性质。形成栅体的硅307具有达到在指定容限内的一致高度。对于一个实施方案来说,硅307的高度Hsi为约10nm并且在5%的误差范围内一致。
图3G图示通过形成围绕硅307的栅308而制造的三栅晶体管。栅308可以是,例如,金属或者本领域中已知的另一适当材料。
总则
本发明的实施方案包括各种操作。许多方法以它们最基本的形式被描述,但是操作可以被添加到任意一种方法或者从任意一种方法被删除而不会背离本发明的基本范围。例如,在图2的操作205中所描述的沟槽层可以被设置在为各种可替换物质的衬底上并且可以是如图3A所图示的包括多于一个层。并且,沟槽层的部分可以被保留以实现优点。如图3F和3G中所示,第一氧化物层的部分被保留以减少晶体管中的边缘电容(fringecapacitance)。
如以上所描述的,可以以包括例如多晶硅的均厚沉积的多个方式来用硅填充在沟槽层中形成的沟槽。对于其中使用多晶硅的均厚沉积的实施方案来说,在沉积后采用退火工艺以使硅退火为单晶。
虽然已经依据几个实施方案对本发明进行了描述,但是本领域中的那些技术人员将发现本发明不仅限于所描述的实施方案,而是可以由处于所附的权利要求书的精神和范围内的修改和替换来实施。因此,本文的描述应该被认为是例证性而不是限制性的。

Claims (23)

1.一种方法包括:
在半导体衬底上设置沟槽层;
选择性地移除所述沟槽层的部分以便所述沟槽层的剩余物形成一个或更多个沟槽,所述沟槽层的部分的移除暴露所述半导体衬底;
用半导体材料填充所述一个或更多个沟槽;
从所述一个或更多个沟槽移除任何多余的半导体材料;以及
移除所述沟槽层的额外部分以将所述半导体材料暴露为一个或更多个半导体鳍。
2.如权利要求1所述的方法,其中所述沟槽层包括多个层。
3.如权利要求2所述的方法,其中所述多个层包括设置在所述半导体衬底上的第一氧化物层、设置在所述第一氧化物层上的氮化物层,以及设置在所述氮化物层上的第二氧化物层。
4.如权利要求3所述的方法,其中移除所述沟槽层的额外部分的操作包括移除所述第二氧化物层的任何剩余部分、所述氮化物层的任何剩余部分,以及保留所述第一氧化物层的任何剩余部分的至少一些部分。
5.如权利要求1所述的方法,其中所述一个或更多个沟槽具有约10nm的深度。
6.如权利要求5所述的方法,其中所述一个或更多个半导体鳍具有约10nm的高度,所述高度达到在5%的范围内一致。
7.如权利要求1所述的方法,其中从所述一个或更多个沟槽移除任何多余半导体材料的操作包括将所述半导体材料平坦化到所述沟槽层的表面。
8.如权利要求7所述的方法,其中所述平坦化操作是通过化学机械抛光工艺实现的。
9.如权利要求1所述的方法,其中用半导体材料填充所述一个或更多个沟槽的操作包括在所述一个或更多个沟槽内部外延地生长所述半导体材料。
10.如权利要求1所述的方法,其中用半导体材料填充所述一个或更多个沟槽的操作包括半导体材料的均厚沉积。
11.一种集成电路器件包括:
衬底;以及
形成在所述衬底上的一个或更多个晶体管,每个晶体管具有半导体体,每个半导体体具有小于20nm的高度,每个半导体体的高度在指定高度的5%的容限内一致。
12.如权利要求11所述的集成电路器件,其中所述一个或更多个晶体管为三栅晶体管。
13.如权利要求12所述的集成电路器件,其中每个半导体体具有约10nm的高度。
14.一种方法包括:
在半导体衬底上设置第一氧化物层;
在所述第一氧化物层上设置氮化物层;
在所述氮化物层上设置第二氧化物层;
选择性地蚀刻所述第二氧化物层和所述氮化物层的部分以限定一个或更多个沟槽;
用半导体材料填充所述一个或更多个沟槽;
从所述一个或多个沟槽移除所述多余的半导体材料;以及
选择性地蚀刻所述第二氧化物层和所述氮化物层的剩余物以便形成一个或更多个半导体体。
15.如权利要求14所述的方法,其中所述一个或更多个沟槽具有约10nm的深度。
16.如权利要求14所述的方法,其中所述一个或更多个半导体体具有小于20nm的高度,所述高度达到在5%的范围内一致。
17.如权利要求16所述的方法,其中所述一个或更多个半导体体具有约10nm的高度。
18.如权利要求14所述的方法,其中从所述一个或更多个沟槽移除任何多余的半导体材料的操作包括将所述半导体材料平坦化到所述第二氧化物层的表面。
19.如权利要求18所述的方法,其中所述平坦化操作是通过化学机械抛光工艺实现的。
20.如权利要求14所述的方法,其中用半导体材料填充所述一个或更多个沟槽的操作包括在所述一个或更多个沟槽内部外延地生长所述半导体材料。
21.如权利要求14所述的方法,其中用半导体材料填充所述一个或更多个沟槽的操作包括半导体材料的均厚沉积。
22.如权利要求14所述的方法,其中所述半导体衬底包括从由硅、锗和砷化镓组成的组中选择的半导体材料。
23.如权利要求14所述的方法,其中所述半导体衬底包括硅,所述第一氧化物层包括SiO2,所述氮化物层包括Si3N4,以及所述第二氧化物层包括SiO2
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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103094121A (zh) * 2011-01-13 2013-05-08 英飞凌科技奥地利有限公司 一种用于制造半导体器件的方法
CN103137445A (zh) * 2011-12-05 2013-06-05 中芯国际集成电路制造(上海)有限公司 形成Finfet掺杂鳍状物的方法
CN103177948A (zh) * 2011-12-22 2013-06-26 中芯国际集成电路制造(上海)有限公司 鳍式场效应管的鳍部以及鳍式场效应管的形成方法
CN103208424A (zh) * 2012-01-16 2013-07-17 英飞凌科技奥地利有限公司 用于制造半导体元件的方法及场效应半导体元件
CN103515234A (zh) * 2012-06-25 2014-01-15 中芯国际集成电路制造(上海)有限公司 形成FinFET的方法
WO2014059686A1 (zh) * 2012-10-18 2014-04-24 中国科学院微电子研究所 FinFET鳍状结构的制造方法
CN103811324A (zh) * 2012-11-13 2014-05-21 中芯国际集成电路制造(上海)有限公司 鳍式场效应管的形成方法
CN104347409A (zh) * 2013-07-24 2015-02-11 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
CN105428413A (zh) * 2014-07-24 2016-03-23 中芯国际集成电路制造(上海)有限公司 鳍式场效应管及其形成方法
CN107039519A (zh) * 2016-02-03 2017-08-11 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法

Families Citing this family (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060202266A1 (en) 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7402875B2 (en) 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US20070054467A1 (en) * 2005-09-07 2007-03-08 Amberwave Systems Corporation Methods for integrating lattice-mismatched semiconductor structure on insulators
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US7525160B2 (en) * 2005-12-27 2009-04-28 Intel Corporation Multigate device with recessed strain regions
WO2007112066A2 (en) 2006-03-24 2007-10-04 Amberwave Systems Corporation Lattice-mismatched semiconductor structures and related methods for device fabrication
JP2007299991A (ja) * 2006-05-01 2007-11-15 Toshiba Corp 半導体装置及びその製造方法
US7354832B2 (en) * 2006-05-03 2008-04-08 Intel Corporation Tri-gate device with conformal PVD workfunction metal on its three-dimensional body and fabrication method thereof
US7517764B2 (en) * 2006-06-29 2009-04-14 International Business Machines Corporation Bulk FinFET device
KR100801078B1 (ko) * 2006-06-29 2008-02-11 삼성전자주식회사 수직 채널을 갖는 비휘발성 메모리 집적 회로 장치 및 그제조 방법
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
WO2008030574A1 (en) 2006-09-07 2008-03-13 Amberwave Systems Corporation Defect reduction using aspect ratio trapping
WO2008039495A1 (en) 2006-09-27 2008-04-03 Amberwave Systems Corporation Tri-gate field-effect transistors formed by aspect ratio trapping
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
WO2008051503A2 (en) 2006-10-19 2008-05-02 Amberwave Systems Corporation Light-emitter-based devices with lattice-mismatched semiconductor structures
US8247850B2 (en) * 2007-01-04 2012-08-21 Freescale Semiconductor, Inc. Dual interlayer dielectric stressor integration with a sacrificial underlayer film stack
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
WO2008124154A2 (en) 2007-04-09 2008-10-16 Amberwave Systems Corporation Photovoltaics on silicon
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
KR101093588B1 (ko) 2007-09-07 2011-12-15 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 멀티-정션 솔라 셀
US8030163B2 (en) * 2007-12-26 2011-10-04 Intel Corporation Reducing external resistance of a multi-gate device using spacer processing techniques
US7763943B2 (en) * 2007-12-26 2010-07-27 Intel Corporation Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin
US20090206404A1 (en) * 2008-02-15 2009-08-20 Ravi Pillarisetty Reducing external resistance of a multi-gate device by silicidation
US8129749B2 (en) * 2008-03-28 2012-03-06 Intel Corporation Double quantum well structures for transistors
US8278687B2 (en) * 2008-03-28 2012-10-02 Intel Corporation Semiconductor heterostructures to reduce short channel effects
US7800166B2 (en) * 2008-05-30 2010-09-21 Intel Corporation Recessed channel array transistor (RCAT) structures and method of formation
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
US7833891B2 (en) * 2008-07-23 2010-11-16 International Business Machines Corporation Semiconductor device manufacturing method using oxygen diffusion barrier layer between buried oxide layer and high K dielectric layer
US7884354B2 (en) * 2008-07-31 2011-02-08 Intel Corporation Germanium on insulator (GOI) semiconductor substrates
US7781283B2 (en) * 2008-08-15 2010-08-24 International Business Machines Corporation Split-gate DRAM with MuGFET, design structure, and method of manufacture
US7979836B2 (en) * 2008-08-15 2011-07-12 International Business Machines Corporation Split-gate DRAM with MuGFET, design structure, and method of manufacture
US20100072515A1 (en) 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
KR101216541B1 (ko) 2008-09-19 2012-12-31 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 에피텍셜층 과성장에 의한 장치의 형성
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
US8184472B2 (en) * 2009-03-13 2012-05-22 International Business Machines Corporation Split-gate DRAM with lateral control-gate MuGFET
JP5705207B2 (ja) 2009-04-02 2015-04-22 台湾積體電路製造股▲ふん▼有限公司Taiwan Semiconductor Manufacturing Company,Ltd. 結晶物質の非極性面から形成される装置とその製作方法
US8440998B2 (en) * 2009-12-21 2013-05-14 Intel Corporation Increasing carrier injection velocity for integrated circuit devices
US8633470B2 (en) * 2009-12-23 2014-01-21 Intel Corporation Techniques and configurations to impart strain to integrated circuit devices
US9105660B2 (en) 2011-08-17 2015-08-11 United Microelectronics Corp. Fin-FET and method of forming the same
CN102956466B (zh) * 2011-08-26 2016-11-16 联华电子股份有限公司 鳍状晶体管与其制作方法
US8923048B2 (en) 2012-04-13 2014-12-30 Sandisk Technologies Inc. 3D non-volatile storage with transistor decoding structure
US20130302954A1 (en) * 2012-05-10 2013-11-14 Globalfoundries Inc. Methods of forming fins for a finfet device without performing a cmp process
US9142400B1 (en) 2012-07-17 2015-09-22 Stc.Unm Method of making a heteroepitaxial layer on a seed area
CN103578995B (zh) * 2012-07-27 2015-12-02 中芯国际集成电路制造(上海)有限公司 形成FinFET的方法
US8765563B2 (en) 2012-09-28 2014-07-01 Intel Corporation Trench confined epitaxially grown device layer(s)
US8768271B1 (en) 2012-12-19 2014-07-01 Intel Corporation Group III-N transistors on nanoscale template structures
US9165933B2 (en) 2013-03-07 2015-10-20 Sandisk 3D Llc Vertical bit line TFT decoder for high voltage operation
CN104037085A (zh) * 2013-03-07 2014-09-10 中国科学院微电子研究所 半导体器件制造方法
US8987082B2 (en) 2013-05-31 2015-03-24 Stmicroelectronics, Inc. Method of making a semiconductor device using sacrificial fins
US20140353716A1 (en) 2013-05-31 2014-12-04 Stmicroelectronics, Inc Method of making a semiconductor device using a dummy gate
US9082788B2 (en) 2013-05-31 2015-07-14 Stmicroelectronics, Inc. Method of making a semiconductor device including an all around gate
US9105582B2 (en) 2013-08-15 2015-08-11 United Microelectronics Corporation Spatial semiconductor structure and method of fabricating the same
US9240420B2 (en) 2013-09-06 2016-01-19 Sandisk Technologies Inc. 3D non-volatile storage with wide band gap transistor decoder
US9018711B1 (en) * 2013-10-17 2015-04-28 Globalfoundries Inc. Selective growth of a work-function metal in a replacement metal gate of a semiconductor device
CN103887177A (zh) * 2014-03-27 2014-06-25 上海集成电路研发中心有限公司 鳍式有源区的制备方法
US20150380258A1 (en) * 2014-06-25 2015-12-31 Stmicroelectronics, Inc. Method for controlling height of a fin structure
US9312143B1 (en) 2014-11-24 2016-04-12 International Business Machines Corporation Formation of isolation surrounding well implantation
US9530701B2 (en) 2014-12-18 2016-12-27 International Business Machines Corporation Method of forming semiconductor fins on SOI substrate
US20170018427A1 (en) * 2015-07-15 2017-01-19 Applied Materials, Inc. Method of selective epitaxy
US9397005B1 (en) 2015-07-20 2016-07-19 International Business Machines Corporation Dual-material mandrel for epitaxial crystal growth on silicon
US10121675B2 (en) 2016-12-29 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor device and a method for fabricating the same

Family Cites Families (195)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4907048A (en) * 1987-11-23 1990-03-06 Xerox Corporation Double implanted LDD transistor self-aligned with gate
US4905063A (en) * 1988-06-21 1990-02-27 American Telephone And Telegraph Company, At&T Bell Laboratories Floating gate memories
JPH0214578A (ja) * 1988-07-01 1990-01-18 Fujitsu Ltd 半導体装置
US4994873A (en) * 1988-10-17 1991-02-19 Motorola, Inc. Local interconnect for stacked polysilicon device
US5346834A (en) 1988-11-21 1994-09-13 Hitachi, Ltd. Method for manufacturing a semiconductor device and a semiconductor memory device
US4906589A (en) 1989-02-06 1990-03-06 Industrial Technology Research Institute Inverse-T LDDFET with self-aligned silicide
KR930003790B1 (ko) 1990-07-02 1993-05-10 삼성전자 주식회사 반도체 장치의 캐패시터용 유전체
US5278102A (en) * 1990-08-18 1994-01-11 Fujitsu Limited SOI device and a fabrication process thereof
JP3202223B2 (ja) 1990-11-27 2001-08-27 日本電気株式会社 トランジスタの製造方法
US5521859A (en) * 1991-03-20 1996-05-28 Fujitsu Limited Semiconductor memory device having thin film transistor and method of producing the same
JP2851968B2 (ja) * 1991-04-26 1999-01-27 キヤノン株式会社 改良された絶縁ゲート型トランジスタを有する半導体装置及びその製造方法
JPH05152293A (ja) * 1991-04-30 1993-06-18 Sgs Thomson Microelectron Inc 段差付き壁相互接続体及びゲートの製造方法
US5292670A (en) 1991-06-10 1994-03-08 Texas Instruments Incorporated Sidewall doping technique for SOI transistors
US5179037A (en) * 1991-12-24 1993-01-12 Texas Instruments Incorporated Integration of lateral and vertical quantum well transistors in the same epitaxial stack
US5391506A (en) * 1992-01-31 1995-02-21 Kawasaki Steel Corporation Manufacturing method for semiconductor devices with source/drain formed in substrate projection.
US5405454A (en) * 1992-03-19 1995-04-11 Matsushita Electric Industrial Co., Ltd. Electrically insulated silicon structure and producing method therefor
JP2572003B2 (ja) 1992-03-30 1997-01-16 三星電子株式会社 三次元マルチチャンネル構造を有する薄膜トランジスタの製造方法
JPH0793441B2 (ja) 1992-04-24 1995-10-09 ヒュンダイ エレクトロニクス インダストリーズ カンパニー リミテッド 薄膜トランジスタ及びその製造方法
JPH06177089A (ja) 1992-12-04 1994-06-24 Fujitsu Ltd 半導体装置の製造方法
KR960002088B1 (ko) * 1993-02-17 1996-02-10 삼성전자주식회사 에스오아이(SOI : silicon on insulator) 구조의 반도체 장치 제조방법
JPH0750421A (ja) 1993-05-06 1995-02-21 Siemens Ag Mos形電界効果トランジスタ
US5739544A (en) * 1993-05-26 1998-04-14 Matsushita Electric Industrial Co., Ltd. Quantization functional device utilizing a resonance tunneling effect and method for producing the same
US6730549B1 (en) 1993-06-25 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
JP3460863B2 (ja) 1993-09-17 2003-10-27 三菱電機株式会社 半導体装置の製造方法
JP3317582B2 (ja) * 1994-06-01 2002-08-26 菱電セミコンダクタシステムエンジニアリング株式会社 微細パターンの形成方法
JPH08125152A (ja) 1994-10-28 1996-05-17 Canon Inc 半導体装置、それを用いた相関演算装置、ad変換器、da変換器、信号処理システム
US5728594A (en) * 1994-11-02 1998-03-17 Texas Instruments Incorporated Method of making a multiple transistor integrated circuit with thick copper interconnect
GB2295488B (en) 1994-11-24 1996-11-20 Toshiba Cambridge Res Center Semiconductor device
US5716879A (en) 1994-12-15 1998-02-10 Goldstar Electron Company, Ltd. Method of making a thin film transistor
JPH08204191A (ja) * 1995-01-20 1996-08-09 Sony Corp 電界効果トランジスタ及びその製造方法
KR0165398B1 (ko) * 1995-05-26 1998-12-15 윤종용 버티칼 트랜지스터의 제조방법
US5658806A (en) 1995-10-26 1997-08-19 National Science Council Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration
US5595919A (en) * 1996-02-20 1997-01-21 Chartered Semiconductor Manufacturing Pte Ltd. Method of making self-aligned halo process for reducing junction capacitance
JPH09293793A (ja) * 1996-04-26 1997-11-11 Mitsubishi Electric Corp 薄膜トランジスタを有する半導体装置およびその製造方法
US5851882A (en) * 1996-05-06 1998-12-22 Micron Technology, Inc. ZPROM manufacture and design and methods for forming thin structures using spacers as an etching mask
JP3710880B2 (ja) * 1996-06-28 2005-10-26 株式会社東芝 不揮発性半導体記憶装置
TW556263B (en) * 1996-07-11 2003-10-01 Semiconductor Energy Lab Semiconductor device and method of manufacturing the same
US5817560A (en) 1996-09-12 1998-10-06 Advanced Micro Devices, Inc. Ultra short trench transistors and process for making same
US6399970B2 (en) * 1996-09-17 2002-06-04 Matsushita Electric Industrial Co., Ltd. FET having a Si/SiGeC heterojunction channel
US6163053A (en) 1996-11-06 2000-12-19 Ricoh Company, Ltd. Semiconductor device having opposite-polarity region under channel
JPH10150185A (ja) * 1996-11-20 1998-06-02 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5827769A (en) 1996-11-20 1998-10-27 Intel Corporation Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode
JPH1140811A (ja) 1997-07-22 1999-02-12 Hitachi Ltd 半導体装置およびその製造方法
US6066869A (en) * 1997-10-06 2000-05-23 Micron Technology, Inc. Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
US5856225A (en) * 1997-11-24 1999-01-05 Chartered Semiconductor Manufacturing Ltd Creation of a self-aligned, ion implanted channel region, after source and drain formation
US5888309A (en) 1997-12-29 1999-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluorine containing plasma followed by an oxygen containing plasma
US6097065A (en) 1998-03-30 2000-08-01 Micron Technology, Inc. Circuits and methods for dual-gated transistors
US6232641B1 (en) * 1998-05-29 2001-05-15 Kabushiki Kaisha Toshiba Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor
US6114201A (en) * 1998-06-01 2000-09-05 Texas Instruments-Acer Incorporated Method of manufacturing a multiple fin-shaped capacitor for high density DRAMs
US6696366B1 (en) * 1998-08-17 2004-02-24 Lam Research Corporation Technique for etching a low capacitance dielectric layer
US6200865B1 (en) * 1998-12-04 2001-03-13 Advanced Micro Devices, Inc. Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate
US6362111B1 (en) * 1998-12-09 2002-03-26 Texas Instruments Incorporated Tunable gate linewidth reduction process
US6380558B1 (en) 1998-12-29 2002-04-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US6174820B1 (en) * 1999-02-16 2001-01-16 Sandia Corporation Use of silicon oxynitride as a sacrificial material for microelectromechanical devices
US7045468B2 (en) * 1999-04-09 2006-05-16 Intel Corporation Isolated junction structure and method of manufacture
DE60001601T2 (de) * 1999-06-18 2003-12-18 Lucent Technologies Inc Fertigungsverfahren zur Herstellung eines CMOS integrieten Schaltkreises mit vertikalen Transistoren
JP2001093972A (ja) * 1999-09-20 2001-04-06 Denso Corp 半導体装置の製造方法
US6259135B1 (en) * 1999-09-24 2001-07-10 International Business Machines Corporation MOS transistors structure for reducing the size of pitch limited circuits
US6252284B1 (en) 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
JP4923318B2 (ja) * 1999-12-17 2012-04-25 ソニー株式会社 不揮発性半導体記憶装置およびその動作方法
JP3846706B2 (ja) 2000-02-23 2006-11-15 信越半導体株式会社 ウエーハ外周面取部の研磨方法及び研磨装置
US6483156B1 (en) 2000-03-16 2002-11-19 International Business Machines Corporation Double planar gated SOI MOSFET structure
FR2810161B1 (fr) * 2000-06-09 2005-03-11 Commissariat Energie Atomique Memoire electronique a architecture damascene et procede de realisation d'une telle memoire
US6526996B1 (en) * 2000-06-12 2003-03-04 Promos Technologies, Inc. Dry clean method instead of traditional wet clean after metal etch
US6391782B1 (en) * 2000-06-20 2002-05-21 Advanced Micro Devices, Inc. Process for forming multiple active lines and gate-all-around MOSFET
US20020011612A1 (en) 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2002118255A (ja) * 2000-07-31 2002-04-19 Toshiba Corp 半導体装置およびその製造方法
JP2002047034A (ja) * 2000-07-31 2002-02-12 Shinetsu Quartz Prod Co Ltd プラズマを利用したプロセス装置用の石英ガラス治具
KR100338778B1 (ko) * 2000-08-21 2002-05-31 윤종용 선택적 실리사이드 공정을 이용한 모스 트랜지스터의제조방법
US6358800B1 (en) * 2000-09-18 2002-03-19 Vanguard International Semiconductor Corporation Method of forming a MOSFET with a recessed-gate having a channel length beyond photolithography limit
JP2002100762A (ja) * 2000-09-22 2002-04-05 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP4044276B2 (ja) 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6562665B1 (en) 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
US7163864B1 (en) 2000-10-18 2007-01-16 International Business Machines Corporation Method of fabricating semiconductor side wall fin
US6413802B1 (en) 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6396108B1 (en) 2000-11-13 2002-05-28 Advanced Micro Devices, Inc. Self-aligned double gate silicon-on-insulator (SOI) device
US6716684B1 (en) 2000-11-13 2004-04-06 Advanced Micro Devices, Inc. Method of making a self-aligned triple gate silicon-on-insulator device
CN101465295A (zh) 2000-11-22 2009-06-24 株式会社日立制作所 半导体器件及其制造方法
US6921947B2 (en) * 2000-12-15 2005-07-26 Renesas Technology Corp. Semiconductor device having recessed isolation insulation film
US6413877B1 (en) 2000-12-22 2002-07-02 Lam Research Corporation Method of preventing damage to organo-silicate-glass materials during resist stripping
JP2002198368A (ja) 2000-12-26 2002-07-12 Nec Corp 半導体装置の製造方法
US6537901B2 (en) * 2000-12-29 2003-03-25 Hynix Semiconductor Inc. Method of manufacturing a transistor in a semiconductor device
US6359311B1 (en) * 2001-01-17 2002-03-19 Taiwan Semiconductor Manufacturing Co., Ltd. Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same
US6475890B1 (en) 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
US6475869B1 (en) 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6630388B2 (en) 2001-03-13 2003-10-07 National Institute Of Advanced Industrial Science And Technology Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
US6902947B2 (en) * 2001-05-07 2005-06-07 Applied Materials, Inc. Integrated method for release and passivation of MEMS structures
SG112804A1 (en) 2001-05-10 2005-07-28 Inst Of Microelectronics Sloped trench etching process
KR100363332B1 (en) * 2001-05-23 2002-12-05 Samsung Electronics Co Ltd Method for forming semiconductor device having gate all-around type transistor
US6635923B2 (en) 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US6506692B2 (en) * 2001-05-30 2003-01-14 Intel Corporation Method of making a semiconductor device using a silicon carbide hard mask
JP2003017508A (ja) 2001-07-05 2003-01-17 Nec Corp 電界効果トランジスタ
US6534807B2 (en) * 2001-08-13 2003-03-18 International Business Machines Corporation Local interconnect junction on insulator (JOI) structure
US6764965B2 (en) * 2001-08-17 2004-07-20 United Microelectronics Corp. Method for improving the coating capability of low-k dielectric layer
US6689650B2 (en) 2001-09-27 2004-02-10 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US6492212B1 (en) * 2001-10-05 2002-12-10 International Business Machines Corporation Variable threshold voltage double gated transistors and method of fabrication
US20030085194A1 (en) 2001-11-07 2003-05-08 Hopkins Dean A. Method for fabricating close spaced mirror arrays
US7385262B2 (en) 2001-11-27 2008-06-10 The Board Of Trustees Of The Leland Stanford Junior University Band-structure modulation of nano-structures in an electric field
US6967351B2 (en) * 2001-12-04 2005-11-22 International Business Machines Corporation Finfet SRAM cell using low mobility plane for cell stability and method for forming
US6657259B2 (en) 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US6610576B2 (en) 2001-12-13 2003-08-26 International Business Machines Corporation Method for forming asymmetric dual gate transistor
US6722946B2 (en) * 2002-01-17 2004-04-20 Nutool, Inc. Advanced chemical mechanical polishing system with smart endpoint detection
US6583469B1 (en) * 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same
KR100442089B1 (ko) * 2002-01-29 2004-07-27 삼성전자주식회사 노치된 게이트 전극을 갖는 모스 트랜지스터의 제조방법
KR100458288B1 (ko) 2002-01-30 2004-11-26 한국과학기술원 이중-게이트 FinFET 소자 및 그 제조방법
US20030151077A1 (en) 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
JP3782021B2 (ja) 2002-02-22 2006-06-07 株式会社東芝 半導体装置、半導体装置の製造方法、半導体基板の製造方法
US6635909B2 (en) 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
FR2838238B1 (fr) * 2002-04-08 2005-04-15 St Microelectronics Sa Dispositif semiconducteur a grille enveloppante encapsule dans un milieu isolant
US6762469B2 (en) * 2002-04-19 2004-07-13 International Business Machines Corporation High performance CMOS device structure with mid-gap metal gate
US6713396B2 (en) 2002-04-29 2004-03-30 Hewlett-Packard Development Company, L.P. Method of fabricating high density sub-lithographic features on a substrate
US6537885B1 (en) * 2002-05-09 2003-03-25 Infineon Technologies Ag Transistor and method of manufacturing a transistor having a shallow junction formation using a two step EPI layer
US7074623B2 (en) 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US6680240B1 (en) 2002-06-25 2004-01-20 Advanced Micro Devices, Inc. Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
US6974729B2 (en) * 2002-07-16 2005-12-13 Interuniversitair Microelektronica Centrum (Imec) Integrated semiconductor fin device and a method for manufacturing such device
KR100477543B1 (ko) * 2002-07-26 2005-03-18 동부아남반도체 주식회사 단채널 트랜지스터 형성방법
EP1387395B1 (en) * 2002-07-31 2016-11-23 Micron Technology, Inc. Method for manufacturing semiconductor integrated circuit structures
JP2004071996A (ja) * 2002-08-09 2004-03-04 Hitachi Ltd 半導体集積回路装置の製造方法
US6984585B2 (en) * 2002-08-12 2006-01-10 Applied Materials Inc Method for removal of residue from a magneto-resistive random access memory (MRAM) film stack using a sacrificial mask layer
US7358121B2 (en) * 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US7163851B2 (en) 2002-08-26 2007-01-16 International Business Machines Corporation Concurrent Fin-FET and thick-body device fabrication
US6794313B1 (en) 2002-09-20 2004-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Oxidation process to improve polysilicon sidewall roughness
JP3556651B2 (ja) * 2002-09-27 2004-08-18 沖電気工業株式会社 半導体装置の製造方法
JP4294935B2 (ja) * 2002-10-17 2009-07-15 株式会社ルネサステクノロジ 半導体装置
US6706571B1 (en) 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US6611029B1 (en) 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6787439B2 (en) 2002-11-08 2004-09-07 Advanced Micro Devices, Inc. Method using planarizing gate material to improve gate critical dimension in semiconductor devices
JP2004175866A (ja) 2002-11-26 2004-06-24 Nippon Kayaku Co Ltd 光ディスク用接着剤組成物、硬化物および物品
US6709982B1 (en) 2002-11-26 2004-03-23 Advanced Micro Devices, Inc. Double spacer FinFET formation
US6855990B2 (en) * 2002-11-26 2005-02-15 Taiwan Semiconductor Manufacturing Co., Ltd Strained-channel multiple-gate transistor
US6825506B2 (en) * 2002-11-27 2004-11-30 Intel Corporation Field effect transistor and method of fabrication
US6645797B1 (en) 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
US7728360B2 (en) * 2002-12-06 2010-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-gate transistor structure
KR100487922B1 (ko) * 2002-12-06 2005-05-06 주식회사 하이닉스반도체 반도체소자의 트랜지스터 및 그 형성방법
US6686231B1 (en) * 2002-12-06 2004-02-03 Advanced Micro Devices, Inc. Damascene gate process with sacrificial oxide in semiconductor devices
US6869868B2 (en) * 2002-12-13 2005-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a MOSFET device with metal containing gate structures
US6794718B2 (en) 2002-12-19 2004-09-21 International Business Machines Corporation High mobility crystalline planes in double-gate CMOS technology
DE60236375D1 (de) 2002-12-20 2010-06-24 Ibm Integrierte anitfuse-struktur für finfet- und cmos-vorrichtungen
US6762483B1 (en) * 2003-01-23 2004-07-13 Advanced Micro Devices, Inc. Narrow fin FinFET
US6803631B2 (en) * 2003-01-23 2004-10-12 Advanced Micro Devices, Inc. Strained channel finfet
US6885055B2 (en) * 2003-02-04 2005-04-26 Lee Jong-Ho Double-gate FinFET device and fabricating method thereof
US7304336B2 (en) 2003-02-13 2007-12-04 Massachusetts Institute Of Technology FinFET structure and method to make the same
US6855606B2 (en) 2003-02-20 2005-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-rod devices
US6716690B1 (en) 2003-03-12 2004-04-06 Advanced Micro Devices, Inc. Uniformly doped source/drain junction in a double-gate MOSFET
KR100607647B1 (ko) 2003-03-14 2006-08-23 주식회사 하이닉스반도체 반도체소자의 제조 방법
US6844238B2 (en) 2003-03-26 2005-01-18 Taiwan Semiconductor Manufacturing Co., Ltd Multiple-gate transistors with improved gate control
US20040191980A1 (en) 2003-03-27 2004-09-30 Rafael Rios Multi-corner FET for better immunity from short channel effects
US6790733B1 (en) 2003-03-28 2004-09-14 International Business Machines Corporation Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer
US6764884B1 (en) 2003-04-03 2004-07-20 Advanced Micro Devices, Inc. Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
TWI231994B (en) 2003-04-04 2005-05-01 Univ Nat Taiwan Strained Si FinFET
JP3976703B2 (ja) 2003-04-30 2007-09-19 エルピーダメモリ株式会社 半導体装置の製造方法
US6867433B2 (en) * 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US6838322B2 (en) * 2003-05-01 2005-01-04 Freescale Semiconductor, Inc. Method for forming a double-gated semiconductor device
US7045401B2 (en) 2003-06-23 2006-05-16 Sharp Laboratories Of America, Inc. Strained silicon finFET device
US6909151B2 (en) * 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US20040262683A1 (en) 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US6960517B2 (en) 2003-06-30 2005-11-01 Intel Corporation N-gate transistor
US6716686B1 (en) * 2003-07-08 2004-04-06 Advanced Micro Devices, Inc. Method for forming channels in a finfet device
US6921982B2 (en) 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
US7013447B2 (en) * 2003-07-22 2006-03-14 Freescale Semiconductor, Inc. Method for converting a planar transistor design to a vertical double gate transistor design
KR100487567B1 (ko) * 2003-07-24 2005-05-03 삼성전자주식회사 핀 전계효과 트랜지스터 형성 방법
EP1519420A2 (en) * 2003-09-25 2005-03-30 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Multiple gate semiconductor device and method for forming same
US6835618B1 (en) 2003-08-05 2004-12-28 Advanced Micro Devices, Inc. Epitaxially grown fin for FinFET
US7172943B2 (en) 2003-08-13 2007-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate transistors formed on bulk substrates
US7355253B2 (en) * 2003-08-22 2008-04-08 International Business Machines Corporation Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates
US6998301B1 (en) * 2003-09-03 2006-02-14 Advanced Micro Devices, Inc. Method for forming a tri-gate MOSFET
US7170126B2 (en) * 2003-09-16 2007-01-30 International Business Machines Corporation Structure of vertical strained silicon devices
US6867460B1 (en) * 2003-11-05 2005-03-15 International Business Machines Corporation FinFET SRAM cell with chevron FinFET logic
US7183137B2 (en) 2003-12-01 2007-02-27 Taiwan Semiconductor Manufacturing Company Method for dicing semiconductor wafers
US7018551B2 (en) * 2003-12-09 2006-03-28 International Business Machines Corporation Pull-back method of forming fins in FinFets
US7388258B2 (en) 2003-12-10 2008-06-17 International Business Machines Corporation Sectional field effect devices
US7223679B2 (en) * 2003-12-24 2007-05-29 Intel Corporation Transistor gate electrode having conductor material layer
US7247578B2 (en) * 2003-12-30 2007-07-24 Intel Corporation Method of varying etch selectivities of a film
US7105390B2 (en) * 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US7705345B2 (en) 2004-01-07 2010-04-27 International Business Machines Corporation High performance strained silicon FinFETs device and method for forming same
US7385247B2 (en) * 2004-01-17 2008-06-10 Samsung Electronics Co., Ltd. At least penta-sided-channel type of FinFET transistor
US7224029B2 (en) * 2004-01-28 2007-05-29 International Business Machines Corporation Method and structure to create multiple device widths in FinFET technology in both bulk and SOI
US7060539B2 (en) * 2004-03-01 2006-06-13 International Business Machines Corporation Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US20050224797A1 (en) 2004-04-01 2005-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS fabricated on different crystallographic orientation substrates
US6864540B1 (en) * 2004-05-21 2005-03-08 International Business Machines Corp. High performance FET with elevated source/drain region
US8669145B2 (en) * 2004-06-30 2014-03-11 International Business Machines Corporation Method and structure for strained FinFET devices
US20060040054A1 (en) * 2004-08-18 2006-02-23 Pearlstein Ronald M Passivating ALD reactor chamber internal surfaces to prevent residue buildup
US20060043500A1 (en) * 2004-08-24 2006-03-02 Jian Chen Transistor structure with stress modification and capacitive reduction feature in a channel direction and method thereof
US7250367B2 (en) * 2004-09-01 2007-07-31 Micron Technology, Inc. Deposition methods using heteroleptic precursors
US7332439B2 (en) * 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7279375B2 (en) * 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US20070023795A1 (en) * 2005-07-15 2007-02-01 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US7348642B2 (en) * 2005-08-03 2008-03-25 International Business Machines Corporation Fin-type field effect transistor
US7352034B2 (en) * 2005-08-25 2008-04-01 International Business Machines Corporation Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
US7339241B2 (en) * 2005-08-31 2008-03-04 Freescale Semiconductor, Inc. FinFET structure with contacts
US7479421B2 (en) * 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
KR100718159B1 (ko) * 2006-05-18 2007-05-14 삼성전자주식회사 와이어-타입 반도체 소자 및 그 제조 방법
US20080017890A1 (en) * 2006-06-30 2008-01-24 Sandisk 3D Llc Highly dense monolithic three dimensional memory array and method for forming
US7655989B2 (en) * 2006-11-30 2010-02-02 International Business Machines Corporation Triple gate and double gate finFETs with different vertical dimension fins

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9806187B2 (en) 2011-01-13 2017-10-31 Infineon Technologies Austria Ag Method for manufacturing a semiconductor device
CN103094121A (zh) * 2011-01-13 2013-05-08 英飞凌科技奥地利有限公司 一种用于制造半导体器件的方法
CN103137445A (zh) * 2011-12-05 2013-06-05 中芯国际集成电路制造(上海)有限公司 形成Finfet掺杂鳍状物的方法
CN103137445B (zh) * 2011-12-05 2015-12-02 中芯国际集成电路制造(上海)有限公司 形成Finfet掺杂鳍状物的方法
CN103177948B (zh) * 2011-12-22 2015-11-25 中芯国际集成电路制造(上海)有限公司 鳍式场效应管的鳍部以及鳍式场效应管的形成方法
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CN103208424A (zh) * 2012-01-16 2013-07-17 英飞凌科技奥地利有限公司 用于制造半导体元件的方法及场效应半导体元件
CN103208424B (zh) * 2012-01-16 2016-08-31 英飞凌科技奥地利有限公司 用于制造半导体元件的方法及场效应半导体元件
CN103515234B (zh) * 2012-06-25 2016-12-21 中芯国际集成电路制造(上海)有限公司 形成FinFET的方法
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US9343530B2 (en) 2012-10-18 2016-05-17 Institute of Microelectronics, Chinese Academy of Sciences Method for manufacturing fin structure of finFET
CN103779210A (zh) * 2012-10-18 2014-05-07 中国科学院微电子研究所 FinFET鳍状结构的制造方法
WO2014059686A1 (zh) * 2012-10-18 2014-04-24 中国科学院微电子研究所 FinFET鳍状结构的制造方法
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