CN1902758A - 沟道区中具有硅和碳层的晶体管 - Google Patents

沟道区中具有硅和碳层的晶体管 Download PDF

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CN1902758A
CN1902758A CNA2004800395388A CN200480039538A CN1902758A CN 1902758 A CN1902758 A CN 1902758A CN A2004800395388 A CNA2004800395388 A CN A2004800395388A CN 200480039538 A CN200480039538 A CN 200480039538A CN 1902758 A CN1902758 A CN 1902758A
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H·-J·李
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    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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Abstract

一种晶体管及其制造方法,该晶体管具有形成于沟道内的应变材料层以增加晶体管速度并改善晶体管性能。在该沟道区内外延生长硅和碳层。可在该硅和碳层上形成薄半导体材料,并在形成该硅和碳层之前外延生长应变半导体层。

Description

沟道区中具有硅和碳层的晶体管
技术领域
本发明通常涉及半导体装置,更为具体地涉及晶体管的制造方法及其结构。
背景技术
半导体装置被用于各种电器,其示例为例如个人计算机、蜂窝电话、数码相机、及其它电子设备。晶体管是一种被广泛用于半导体装置的元件。例如在单个集成电路(IC)上可存在数百万个晶体管。半导体装置制造中使用的常见类型的晶体管为金属氧化物场效应晶体管(MOSFET)。
MOSFET器件的栅电介质过去通常包含二氧化硅。然而,随着器件尺寸的缩小,二氧化硅由于栅极漏电流而成为问题,该栅漏电流会使器件性能退化。因此在该行业中存在朝着使用高介电常数(k)材料作为MOSFET器件中使用的栅电介质的方向发展的趋势。
在2003版International Technology Roadmap for Semiconductor(ITRS)中已经将高k栅电介质发展确定为重大挑战之一,该ITRS指出了接下来15年中半导体行业面临的技术挑战和需要。对于低功率逻辑(例如用于便携式电器),主要问题在于低泄漏电流,为了延长电池寿命这是绝对必需的。由此根据小泄漏电流需要最大化器件性能。在低功率应用中,除了亚阈值泄漏、结泄漏、以及带间隧穿之外,还需要控制栅极泄漏电流。
为了完全实现晶体管尺寸缩小的益处,需要将栅极氧化物的厚度缩小到小于2nm。然而,在要求低待机功耗的许多装置应用中,所产生的栅极泄漏电流使采用这么薄的氧化物变得不切实际。为此,栅极氧化物电介质材料将最终被具有更高介电常数的备选介电材料所替代。然而,使用高k介电材料的器件性能遭受在介电层中存在被俘获电荷的问题,这会使迁移率恶化,使得驱动电流小于使用二氧化硅栅极氧化物的晶体管中的驱动电流,因此降低了使用高k栅介电材料的晶体管的速度和性能。
因此,本领域中需要的是使用高k栅介电材料并具有增加的速度和改善的性能的晶体管的设计和制造方法。
发明内容
通常通过本发明的优选实施例来解决或克服这些及其它问题,并通过本发明的优选实施例实现技术优势,本发明的优选实施例包含具有应变沟道的MOS器件,该应变沟道增大了MOS器件的速度并改善了器件性能。在MOS器件的沟道区中外延生长硅和碳层。该硅和碳层可置于可选的外延生长的应变半导体层上。可在该硅和碳层上沉积可选的薄半导体材料。该硅和碳层以及可选的应变半导体层在MOS器件的沟道内产生应变区域,这是有利的,因为改善了电子迁移率和空穴迁移率。应变半导体层降低了下方工件与该硅和碳层之间的晶格失配界面,这进一步改善了MOS器件的性能。
根据本发明的优选实施例,制造晶体管的方法包括:提供工件,在该工件上生长应变半导体层,在该应变半导体层上生长第一硅和碳层,并在该硅和碳层上沉积栅介电材料。在该栅介电材料上沉积栅材料,图形化该栅材料和栅介电材料从而形成置于该硅和碳层上的栅及栅电介质。在该硅和碳层以及应变半导体层内形成源区和漏区,其中该源区、漏区、栅和栅电介质构成晶体管。
根据本发明的另一个优选实施例,制造晶体管的方法包括:提供工件,在该工件上生长第一硅和碳层,并在该硅和碳层上沉积栅介电材料,该栅电介质材料包含高k材料。在该栅介电材料上沉积包含金属的栅材料,图形化该栅材料和栅介电材料从而形成置于该硅和碳层上的栅及栅电介质。至少在该硅和碳层内形成源区和漏区,其中该源区、漏区、栅和栅电介质构成晶体管。
根据本发明的又一个优选实施例,晶体管包括:工件、置于该工件上的应变半导体层、以及置于该应变半导体层上的第一硅和碳层。栅电介质置于该硅和碳层上,且栅置于该栅电介质上。源区和漏区形成在该硅和碳层以及应变半导体层内,其中该源区、漏区、栅和栅电介质构成晶体管。
根据本发明的另一个优选实施例,晶体管包括:工件、置于该工件上的第一硅和碳层、以及置于该硅和碳层上的栅电介质,该栅电介质包含高k材料。包含金属的栅置于该栅电介质上,并且源区和漏区至少形成在该硅和碳层内,其中该源区、漏区、栅和栅电介质构成晶体管。
本发明优选实施例的优点包括,提供了晶体管设计及其制造方法,其中该晶体管的电学性能以及电学参数得到改善。该晶体管具有增加的速度,并可制成更小的尺寸。将外延生长的材料层引入到沟道区,从而在晶体结构中引入应力,改善了电子和空穴迁移率。该晶体管的驱动电流也得到增大。
前文非常广泛地概述了本发明实施例的特征和技术优点,以便可以更好地理解下文中对本发明的详细描述。下面将详细描述本发明实施例的另外特征和优点,这些特征和优点形成了本发明权利要求的主题。本领域技术人员应理解,可容易地使用这里所公开的概念和具体实施例作为基础,调整或设计出用于实现本发明相同目的的其它结构或工艺。本领域技术人员还应意识到,这种等效构造并不偏离由所附权利要求定义的本发明的精神和范围。
附图说明
为了更彻底地理解本发明及其优点,现在参考附图进行下述描述。附图中:
图1和2示出了根据本发明优选实施例的晶体管在各个制造阶段的截面视图,其中在该晶体管的沟道区上形成硅和碳层;
图3示出了本发明一实施例,其中在该晶体管沟道区内的硅和碳层上形成薄半导体材料;
图4和5示出了本发明实施例的截面视图,其中分别在绝缘体上硅(SOI)衬底上形成图2和3的实施例;
图6和7分别示出了图2和3的实施例,其中在形成第一层硅和碳之前,在工件上形成应变半导体层;以及
图8示出了本发明的一个实施例,该实施例包含形成于硅和碳层下的应变半导体层以及形成于SOI衬底上的薄半导体层。
除非另外指出,不同附图中相应的数字和符号通常表示相应的部件。绘制这些附图的目的是清楚地阐述优选实施例的相关方面,不一定按比例绘制这些附图。
具体实施方式
下面详细描述当前优选实施例的制造和使用。然而应该理解,本发明提供了可在许多特定环境中实施的诸多可应用发明概念。所讨论的具体实施例纯粹是阐述了制造和使用本发明的具体方式,但并不限制本发明的范围。
将参考在特定环境中的优选实施例,即形成于半导体装置上的晶体管,对本发明进行描述。然而,本发明还可应用于MOSFET或其它晶体管器件,可包括例如PMOS、NMOS、或CMOS器件。在各个附图中只示出了一个晶体管,然而,可在所示的半导体装置上形成许多个晶体管。
图1和2示出了根据本发明优选实施例的晶体管在各种制造阶段的截面视图,其中在该晶体管的沟道区内沉积了硅和碳层。为了制造根据本发明实施例的晶体管100,提供了工件102。工件102可包含半导体衬底,该半导体衬底包含覆盖了例如绝缘层的硅或其它半导体材料。工件102也可包含形成于前段制程(front end of line,FEOL)内的其它有源元件或电路(未示出)。工件102可包含例如单晶硅上的氧化硅。工件102可包含其它导电层或其它半导体元件,例如晶体管、二极管等。可使用例如GaAs、InP、Si/Ge、或SiC的化合物半导体替代硅。
如图所示,可在工件102上的不同位置形成隔离区104。隔离区104例如可置于晶体管器件100的沟道区105的任意一侧。可通过在工件102上沉积光致抗蚀剂(未示出)而形成隔离区104。使用光刻技术图形化该光致抗蚀剂,该光致抗蚀剂可用作掩模,同时蚀刻工件102,从而在工件102的上表面内形成用于隔离区104的孔或图形。可在该工件102上沉积例如诸如氧化物的绝缘体以填充该图形,形成隔离区104。或者,例如可通过其它方法形成隔离区104。根据本发明的实施例,可在沟道区105内形成应变材料层106之前或之后形成隔离区104,这将在这里得到进一步描述。
根据本发明的优选实施例,如图所示,在沟道区105内的工件102上表面上形成硅和碳层106。优选地,通过外延生长包含约90至99.5%的硅和约0.5至10%的碳的材料层而形成该硅和碳层106。该硅和碳层优选包含约为几十至约5μm的厚度。或者,该硅和碳层106例如可包含其它百分比的硅和碳,并可包含其它厚度。该硅和碳层106优选包含相对少量的碳,以便层106保持导电。例如,碳可包含硅晶体材料中的间隙键(interstitial bond)。优选地,该硅和碳层106不形成于隔离区104上。因为使用外延生长方法形成该硅和碳层106,硅和碳层106优选不形成于例如隔离区104的绝缘体材料上。然而,如果在隔离区104上沉积或生长了任何材料,可使用抛光工艺或蚀刻工艺从隔离区104的上表面上除去任何硅和碳。
为了VT阈值电压,例如随后可注入工件102的一些区域(未示出)。可在工件102多个部分上执行抗击穿注入,这也未在图中示出。该工件102可随后经过栅前(pre-gate)清洗或包含例如HF化学腐蚀的处理,从而除去位于沟道区105内硅和碳层106上表面上的例如任何颗粒、污物、或自然氧化物颗粒。
接着,根据本发明实施例,如图1所示,在该硅和碳层106及隔离区104上沉积栅介电材料108。根据本发明一个优选实施例的栅介电材料108包含高k材料。栅介电材料108的高k材料可包含例如HfO2、HfSiOx、ZrO2、ZrSiOx、Ta2O5、或其它高k材料。然而,在另一个实施例中,栅介电材料108可包含非高k介电材料,例如SiO2、Si3N4、或其它介电材料。
随后在栅介电材料108上沉积栅材料110。栅材料110优选包含适合用作晶体管器件100的栅电极的材料。在本发明一个优选实施例中,栅材料110包含金属,例如TiN、HfN、TaN,完全硅化的栅材料(FUSI),或其它金属。备选地,在另一个实施例中,栅材料110可包含多晶硅或其它半导体材料。
图形化栅材料110和栅介电材料108以形成栅110和栅电介质108,如图2所示。可使用传统的光刻技术图形化栅材料110和栅介电材料108,例如通过沉积光致抗蚀剂、图形化该光致抗蚀剂、并使用该光致抗蚀剂作为掩模图形化该栅材料110和栅介电材料108(未示出)。备选地,例如可直接蚀刻或使用其它方法图形化该栅材料110和栅介电材料108。
随后靠近沟道区105形成源区S和漏区D。更为特别地,如图所示,优选至少在硅和碳层106内形成源区S和漏区D。注意,在本实施例中,源区S和漏区D的部分也形成在工件102的顶部内。可使用延伸注入(extension implant)形成源区S和漏区D,该注入可包含使用例如约200eV至1KeV的低能注入来注入掺杂剂。在整个工件102上沉积例如氮化硅或其它绝缘体的隔离材料,随后使用例如各向异性蚀刻的蚀刻过程蚀刻该隔离材料,形成如图所示的隔离物112。备选地,隔离物112的形状可更接近矩形,且例如可使用光致抗蚀剂作为掩模进行图形化(未示出)。为了完成该延伸注入,随后执行第二掺杂剂注入过程,优选使用高能注入工艺。例如,第二注入过程可以约为5KeV至20KeV。随后可执行高温退火从而将掺杂剂向内驱赶并激活掺杂剂。例如可在约800℃至约1015℃下执行该高温退火。
图2所示的晶体管100的优点为,沟道区105内的硅和碳层106在沟道区105内引入了应力,这增大了晶体管100工作时的驱动电流,还增大了晶体管器件100的空穴和电子迁移率。这样形成了性能得到改善且速度增大的晶体管100。
在图1和2所示的实施例中,可在外延生长硅和碳层106之前或之后形成隔离区104。如果在形成隔离区104之后生长硅和碳层106,则可使用氧化物或绝缘体回填该隔离区104,使得隔离区104上表面与硅和碳层106的上表面共面,并确保沟道区105不会升高到高于隔离区104的上表面。
图3示出了本发明的另一个实施例,其中在晶体管200的沟道区205内的硅和碳层206上放置了薄半导体材料214。使用与图1和2中相似的参考数字表示各个元件。为了避免重复,在此不详细描述图中所示每个参考数字。更确切地,与图1和2所述相同,所示材料层优选使用相似材料x02、x04、x05等,其中在图1和2中x=1,在图3中x=2。例如,图1和2的描述中所罗列的栅介电材料108的优选和备选材料也优选用于图3中的栅介电材料208。
在所示晶体管200中,在沉积栅介电材料208之前,在硅和碳层206上形成薄半导体材料214。该薄半导体材料214优选包含约100或更薄的半导体材料。例如,该薄半导体材料214优选地外延生长在硅和碳层206上。该薄半导体材料214在一个实施例中优选包含硅。备选地,该薄半导体材料214可包含Ge、SiGe、Si/SiGe双层或Ge/SiGe双层。
如果该薄半导体材料214包含Si/SiGe双层,该双层可包含第一层Si和置于该第一层Si上的第二层SiGe。备选地,该双层例如可包含第一层SiGe和置于该第一层SiGe上的第二层Si。类似地,如果该薄半导体材料214包含Ge/SiGe双层,则该双层可包含第一层Ge和置于该第一层Ge上的第二层SiGe,或者包含第一层SiGe以及置于该第一层SiGe上的第二层Ge。
图3所示晶体管200的优点为,薄半导体材料214置于栅电介质208与硅和碳层206之间。这将硅和碳层206与沟道区205中的下方工件202之间的界面向下移动到沟道区205内。这是有利的,因为该硅和碳层206与工件202的界面可包含失配晶格。例如,工件202内硅的晶体结构的晶格间距不同于硅和碳层206内包含间隙碳原子的硅的晶格间距。因此,这会在硅和碳层206与工件202的相交或界面处产生晶格失配与/或缺陷。因此,通过另外的薄半导体材料214层可进一步改善晶体管200的器件性能和速度。
在图3所示实施例中,可在外延生长硅和碳层206及薄半导体材料214层之前或之后形成隔离区204。如果在形成隔离区204之后生长硅和碳层206及薄半导体材料214层,可使用氧化物或其它绝缘体材料回填该隔离区204,使得隔离区204上表面与薄半导体材料214层上表面共面,并确保沟道区205不会升高到高于隔离区204的上表面。
图4和5示出了本发明实施例的截面视图,其中分别参考图1和2以及图3所述的实施例被示成形成于绝缘体上硅(SOI)衬底或晶片302上。同样,使用与图1至3中相似的参考数字表示各个元件,且为了避免重复,在此不再详细描述图中所示每个参考数字。更确切地,与图1至3所述相同,所示材料层优选使用相似材料x02、x04、x05等,其中在图1和2中x=1,在图3中x=2,在图4和5,x=3。
在图4和5所示实施例中,工件302优选包含SOI衬底302。SOI衬底302包含厚的硅或厚度例如约为500μm的其它半导体材料部分316。在该厚硅层区域316上形成掩埋SiO2层318。该SiO2层318可包含例如约1000的厚度。在掩埋SiO2层318上形成薄硅层320。薄硅层320可包含例如约500或更小的厚度。SOI衬底302的优点为,从源到衬底的泄漏电流得到阻止并降低了晶体管300的寄生电容,进一步增大了晶体管300的速度并减小功耗。
在图4中,晶体管300包含生长在沟道区305内的SOI衬底302的顶部薄硅层320上的硅和碳层306。在图5中,晶体管300进一步包含生长于沟道区305内的硅和碳层306上的薄半导体层314。同样地,在这些实施例中,可在外延生长硅和碳层306及薄半导体材料314层之前或之后形成隔离区304。如果在形成隔离区304之后生长硅和碳层306及薄半导体材料314层,则可使用氧化物或其它绝缘体材料回填该隔离区304,使得隔离区304上表面与薄半导体材料314层或硅和碳层306上表面共面,并确保沟道区305不会升高到高于隔离区304的上表面。
图6和7分别示出了图2和3的实施例,其中在形成硅和碳层406之前,在工件402上外延生长应变半导体层422。同样地,使用了和前述图示中相似的参考数字。在这些实施例中,在生长硅和碳层406之前,在工件402上外延生长应变半导体层422。随后在图6的硅和碳层406及应变半导体层422内,并且也在图7所示可选薄半导体材料414内,形成源区S和漏区D。在这些实施例中,应变半导体层422优选包含约100至5μm的厚度。在一个实施例中,应变半导体层422优选包含第二硅和碳层,该层包含与硅和碳层406相似的材料。在该实施例中,应变半导体层422优选包含大于硅和碳层406的厚度。优选地,应变半导体层422包含的碳的浓度低于硅和碳层406的碳浓度。例如,应变半导体层422优选包含约2-3%或更小的碳浓度。
在另一个实施例中,应变半导体层422优选包含硅和锗层或硅、碳、和锗层。在应变半导体层422中引入锗是有利的,因为硅和锗晶体结构(或硅、碳、和锗)的晶格间距不同于硅和碳层406的晶格间距,这进一步增大晶体管400的空穴迁移率。在本实施例中,例如,应变半导体层422的锗浓度优选约为25%,备选地可包含约15至45%,碳浓度优选为约2-3%。
图8示出了本发明的一实施例,该实施例包含形成于SOI衬底502上的置于硅和碳层506和可选的薄半导体层514之下的应变半导体层522。在本实施例中,在晶体管500的沟道区505内形成薄半导体材料514、硅和碳层506、以及应变半导体层522。工件502包含SOI衬底502,该SOI衬底502包含硅区域516、掩埋SiO2层518、和形成于掩埋SiO2层518上的薄硅层520。注意,在本实施例中,优选地至少在外延生长应变半导体层522之后形成隔离区504。尽管如图8所示,但薄半导体材料514是可选的,可以不置于硅和碳层506与栅电介质508之间(未示出)。
注意,在附图中所示各个实施例中,外延硅层可分别置于硅和碳层106、206、306、406、506与下方的层102、202、320、422、和522之间(未示出)。该外延硅层薄,并优选包含例如约50或更薄的材料。该外延薄硅层改善了例如随后形成的外延层106、206、306、406、506的生长。
本发明实施例的优点包括提供了具有增加的速度和改善的电学特性的晶体管100、200、300、400、500。晶体管100、200、300、400、500具有增大的驱动电流、降低的功耗、以及增加的空穴和电子迁移率。
尽管已经详细描述了本发明的实施例及其优点,应该理解,在不离开由所附权利要求定义的本发明精神和范围的情况下可进行各种改变、替换、和变更。例如,本领域技术人员将容易理解,在本发明的范围内可改变这里所描述的特征、功能、工艺、和材料中的很多。此外,本发明的范围不应受限于本说明书中所描述的工艺、机器、制造、物质成分、工具、方法和步骤的具体实施例。本领域普通技术人员将容易地从本发明的公开了解到,根据本发明可以使用能够执行和这里所述相应实施例基本上相同功能或获得与其基本上相同的结果的现有或随后发展的工艺、机器、制造、物质成分、工具、方法、或步骤。因此,所附权利要求旨在将这些工艺、机器、制造、物质成分、工具、方法、或步骤包含在其范围内。

Claims (32)

1.一种制造晶体管的方法,该方法包括:
提供工件;
在该工件上生长应变半导体层;
在该应变半导体层上生长第一硅和碳层;
在该硅和碳层上沉积栅介电材料;
在该栅介电材料上沉积栅材料;
图形化该栅材料和该栅介电材料从而形成置于该硅和碳层上的栅及栅电介质;以及
在该硅和碳层以及该应变半导体层内形成源区和漏区,其中该源区、漏区、栅和栅电介质构成晶体管。
2.根据权利要求1的方法,其中生长该硅和碳层包括外延生长由约90至99.5%的硅和约0.5至10%的碳形成的层,该层厚度为约几十至约5μm。
3.根据权利要求1的方法,其中生长该应变半导体层包括外延生长第二硅和碳层,硅和锗层,或硅、碳和锗层,且其中生长该应变半导体层包括生长厚度为约100至约5μm的材料。
4.根据权利要求1的方法,其中沉积该栅介电材料包括沉积高k介电材料或氧化物,且其中沉积该栅材料包括沉积半导体材料或金属。
5.根据权利要求1的方法,进一步包括,在沉积栅介电材料之前,在第一硅和碳层上沉积薄半导体材料。
6.根据权利要求5的方法,其中沉积该薄半导体材料包括沉积约100或更薄的Si、Ge、SiGe、Si/SiGe双层、或Ge/SiGe双层。
7.根据权利要求1的方法,进一步包括在该工件上生长该应变半导体层及在该工件上生长第一硅和碳层之前或之后,在该工件内形成隔离区,并进一步包括在该栅和栅电介质的侧壁上形成隔离物。
8.根据权利要求1的方法,其中提供工件包括提供绝缘体上硅(SOI)晶片。
9.一种制造晶体管的方法,该方法包括:
提供工件;
在该工件上生长第一硅和碳层;
在该硅和碳层上沉积栅介电材料,该栅电介质包含高介电常数(k)材料;
在该栅介电材料上沉积栅材料,该栅材料包含金属;
图形化该栅材料和栅介电材料以形成置于该硅和碳层上的栅及栅电介质;以及
至少在该硅和碳层内形成源区和漏区,其中该源区、漏区、栅和栅电介质构成晶体管。
10.根据权利要求9的方法,其中生长该硅和碳层包括外延生长由约90至99.5%的硅和约0.5至10%的碳形成的层,该层厚度为约几十至约5μm。
11.根据权利要求9的方法,进一步包括,在该工件上生长第一硅和碳层之前,在该工件上生长应变半导体层,其中形成源区和漏区包括在应变半导体层内形成源区和漏区。
12.根据权利要求11的方法,其中生长应变半导体层包括外延生长第二硅和碳层,硅和锗层,或硅、碳和锗层,且其中生长应变半导体层包括生长厚度为约100至5μm的材料。
13.根据权利要求9的方法,进一步包括,在沉积栅介电材料之前,在第一硅和碳层上沉积薄半导体材料。
14.根据权利要求13的方法,其中沉积该薄半导体材料包括沉积约100或更薄的Si、Ge、SiGe、Si/SiGe的双层、或Ge/SiGe的双层。
15.根据权利要求9的方法,进一步包括在该工件上生长应变半导体层及在该工件上生长第一硅和碳层之前或之后,在该工件内形成隔离区,并进一步包括在该栅和栅电介质的侧壁上形成隔离物。
16.根据权利要求9的方法,其中提供工件包括提供绝缘体上硅(SOI)晶片。
17.一种晶体管,包括:
工件;
置于该工件上的应变半导体层;
置于该应变半导体层上的第一硅和碳层;
置于该硅和碳层上的栅电介质;
置于该栅电介质上的栅;以及
形成于该硅和碳层以及应变半导体层内的源区和漏区,其中该源区、漏区、栅和栅电介质构成晶体管。
18.根据权利要求17的晶体管,其中该硅和碳层包含外延生长层,该外延生长层包含约90至99.5%的硅和约0.5至10%的碳,厚度为约几十至约5μm。
19.根据权利要求17的晶体管,其中该应变半导体层包含外延生长的第二硅和碳层,硅和锗层,或硅、碳和锗层,且其中该应变半导体层包含约100至5μm的厚度。
20.根据权利要求17的晶体管,其中该栅电介质包含高k介电材料或氧化物,且其中该栅包含半导体材料或金属。
21.根据权利要求17的晶体管,进一步包含置于第一硅和碳层上的薄半导体材料。
22.根据权利要求21的晶体管,其中该薄半导体材料包含约100或更薄的Si、Ge、SiGe、Si/SiGe双层、或Ge/SiGe双层。
23.根据权利要求21的晶体管,进一步包含置于该工件内的隔离区,并进一步包含形成于该栅和栅电介质的侧壁上的隔离物。
24.根据权利要求21的晶体管,其中该工件包括绝缘体上硅(SOI)晶片。
25.一种晶体管,包含:
工件;
置于该工件上的第一硅和碳层;
置于该硅和碳层上的栅电介质,该栅电介质包含高介电常数(k)材料;
置于该栅电介质上的栅,该栅包含金属;以及
形成于至少该硅和碳层内的源区和漏区,其中该源区、漏区、栅和栅电介质构成晶体管。
26.根据权利要求25的晶体管,其中该硅和碳层包含外延生长层,该外延生长层包含约90至99.5%的硅和约0.5至10%的碳,厚度为约几十至约5μm。
27.根据权利要求25的晶体管,进一步包含在第一硅和碳层下方形成于工件上的应变半导体层,其中源区和漏也形成于该应变半导体层内。
28.根据权利要求27的晶体管,其中该应变半导体层包含第二硅和碳层,硅和锗层,或硅、碳和锗层,且其中该应变半导体层包含厚度为约100至5μm的材料。
29.根据权利要求25的晶体管,进一步包含栅介电材料下方的置于第一硅和碳层之上的薄半导体材料。
30.根据权利要求29的晶体管,其中该薄半导体材料包含约100或更薄的Si、Ge、SiGe、Si/SiGe双层、或Ge/SiGe双层。
31.根据权利要求25的晶体管,进一步包含形成于该工件内的隔离区,并进一步包含形成于该栅和栅电介质的侧壁上的隔离物。
32.根据权利要求25的晶体管,其中该工件包括绝缘体上硅(SOI)晶片。
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