CN1902739A - 改变膜的刻蚀选择性的方法 - Google Patents

改变膜的刻蚀选择性的方法 Download PDF

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CN1902739A
CN1902739A CNA2004800395316A CN200480039531A CN1902739A CN 1902739 A CN1902739 A CN 1902739A CN A2004800395316 A CNA2004800395316 A CN A2004800395316A CN 200480039531 A CN200480039531 A CN 200480039531A CN 1902739 A CN1902739 A CN 1902739A
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district
lattice
gate electrode
etching
film
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J·K·布拉斯克
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Intel Corp
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Abstract

一种构图晶体膜的方法。提供具有退化晶格的晶体膜,所述退化晶格包括在第一区和第二区中的第一原子。掺杂剂代替了所述第一区中的所述第一原子,以在所述第一区中形成非退化晶体膜。第一区和第二区暴露于湿刻蚀剂,其中该湿刻蚀剂刻蚀所述第二区中的退化晶格,而不刻蚀第一区中的非退化晶格。

Description

改变膜的刻蚀选择性的方法
发明背景
1.发明领域
【0001】本发明涉及晶体膜的构图,更特别地涉及改变晶体膜的刻蚀选择性的方法。
2.相关技术讨论
【0002】半导体集成电路由多层构图薄膜制造。在现代集成电路的整个制造中采用构图单晶和多晶薄膜。例如,构图半导体晶体膜,如外延硅、砷化镓和InSb用于形成非平面或三栅器件中的半导体本体或翼片(fin)。另外,使用高介电常数金属氧化物晶体膜形成现代集成电路中的栅极介电层。目前,晶体膜是通过首先在晶体膜上形成具有所希望图形的掩模来构图的。然后使用湿刻蚀剂刻蚀掉晶体膜的暴露部分。不幸地是,湿刻蚀剂钻蚀掩模,导致掩模中的图形和晶体膜中得到的图形之间的不良保真度。晶体膜的构图和掩模之间缺乏保真度限制了进一步衡量晶体膜的构图尺寸的能力。为了增加特征密度以产生功能更强的集成电路如微处理器,进一步衡量晶体膜的尺寸的能力是必不可少的。
附图说明
【0003】图1A-1D表示根据本发明的刻蚀晶体膜的方法。
【0004】图1E表示如图1A-1D所示形成的选择性刻蚀膜上的非平面器件的形成。
【0005】图2A-2P表示根据本发明的制造CMOS集成电路的方法,所述CMOS集成电路包括利用了替代栅极技术的n型晶体管和p型晶体管,所述替代栅极技术采用晶体膜的选择性刻蚀。
具体实施方式
【0006】描述了一种改变晶体膜的刻蚀选择性的方法。在下面的说明中,为了全面理解本发明而列举了多个具体细节。在其它例子中,为了不使本发明不清楚,没有特别详细地描述公知的半导体处理技术和特征。
【0007】本发明是一种通过修改膜的晶格能量来改变晶体膜的刻蚀选择性的方法。根据本发明,提供要刻蚀的晶体膜。该晶体膜具有对称的晶格或“退化的”晶格。然后将掺杂剂原子放入晶体膜的一部分中并将该膜加热到足够的能量,使掺杂剂与晶体膜中的原子进行取代。利用具有远远不同于晶体膜的原子的尺寸的掺杂剂原子使晶格变形,并使晶格变成非对称或“非退化”。使一部分晶格变成非退化导致晶格中的热力学稳定或晶格“能量倾卸(energy dump)”并使非退化部分变得更强和更难以刻蚀。更稳定的非退化晶格部分具有比未改变的膜的退化部分更高的刻蚀剂的激活势垒。通过利用具有足够高的激活能量以刻蚀掉晶体膜的退化晶格部分但不会高到足以刻蚀掉晶体膜的非退化晶格部分的刻蚀剂,可以利用晶体膜的退化晶格部分和非退化晶格部分之间的激活能量势垒的差。通过这种方式,可以在不刻蚀膜的非退化部分的情况下刻蚀掉膜的退化晶格部分,结果形成非常高的选择性刻蚀工艺。本发明可以用于提供高于100∶1的选择性。也就是说,本发明能用特殊刻蚀剂比膜的非退化部分快100倍以上的速度刻蚀掉膜的退化部分。可以利用这种刻蚀选择性来实现膜的无掩模刻蚀并利用湿刻蚀剂实现膜的各向异性刻蚀。这种工艺在构图晶体膜时可以是很有价值的,如用于形成翼片FET的翼片或本体或非平面器件的半导体膜,和/或可以在替代栅极工艺(在平面和非平面器件中)期间用于除去晶体牺牲栅电极。晶体膜的选择性刻蚀的其它用途,如用作栅极介电层的高介电常数电介质膜的选择性刻蚀,将从本发明的说明中变得明显。
【0008】图1A-1D中示出了根据本发明的实施例的构图膜的方法的例子。根据本发明,提供要刻蚀的膜102。膜102是具有对称或退化晶格的晶体膜。该晶体膜可以是单个晶体膜,如外延膜或单晶膜。晶体膜102还可以是多晶膜,其包括单个晶体材料的多个晶粒。晶体膜应该是非镶嵌膜,由此个别的单位单元或晶粒足够大,使得掺杂剂原子可以放入并代替晶格的原子,从而使晶格变形,由此使晶格变成非退化以提供足够不同的晶格能量,并由此具有与退化晶格部分足够不同的刻蚀剂的激活势垒。在本发明的实施例中,晶体膜102具有非镶嵌退化晶格。在本发明的实施例中,晶体膜102是单晶体半导体膜,例如但不限于硅、砷化镓和InSb。在本发明的实施例中,晶体膜102是高介电常数金属氧化物膜,例如但不限于氧化铪、氧化锆、氧化钛和氧化钽。
【0009】晶体膜102形成在衬底104上。在本发明的实施例中,衬底104是为了形成绝缘体上半导体(SOI)衬底的绝缘衬底104。在本发明的实施例中,绝缘衬底包括绝缘膜106,如形成在硅单晶衬底108上的氧化硅或氮化硅。
【0010】接着,如图1B所示,将掺杂剂原子放入晶体膜102中,从而在晶体膜102中形成掺杂区110。掺杂区110可以通过在晶体膜102上形成掩模112来形成。掩模112具有限定将要向晶体膜102中放入掺杂剂的位置或区域110的开口114。掩模112可以是光致抗蚀剂掩模,其是通过以下步骤形成的:在晶体膜102上覆盖淀积光致抗蚀剂膜,并使用公知光刻工艺,如掩模、曝光、和显影,在光致抗蚀剂膜中形成开口114。尽管理想地使用光致抗蚀剂掩模112,但是可使用其它类型掩模,如但不限于由氧化硅、氮化硅或氮氧化硅膜或其组合形成的硬掩模。然后例如利用离子注入通过开口114将掺杂剂放入区域110中。掩模112防止掺杂剂放入到被掩模112覆盖的部位处的晶体膜102中。在本发明的实施例中,掺杂剂是利用零度注入角(即垂直于衬底104的平面的注入角)放入的。通过这种方式,将掺杂剂放入晶体膜102中的与开口114对准的区域110中。尽管在本发明的实施例中希望使用零度或基本上零度离子注入角,但是如果希望具有角度轮廓的掺杂区,则可以使用较大角度离子注入。尽管本发明的实施例采用掩模112和离子注入来形成掺杂区110,但是可以采用其他公知技术来形成掺杂区114,例如但不限于固体源扩散。
【0011】放入到晶体膜102中的掺杂剂原子具有远不同于形成晶体膜102的晶格的原子的尺寸。掺杂剂具有远不同于晶体膜的原子的物理尺寸(即更大或更小),使得当它们取代晶体膜102的晶格中的原子时,它们使晶格的对称性变形并使晶格变成非对称或非退化。在本发明的实施例中,掺杂剂原子小于晶格中的原子。在本发明的替换实施例中,这些原子在物理上大于晶格中的原子。在本发明的实施例中,掺杂剂相对于晶体膜是电中性的,因此当它们被激活时,它们并不改变晶体膜的导电性。在本发明的实施例中,掺杂剂相对于晶体膜不是电中性的,并使晶体膜变成导电类型(即n型或p型)的晶体膜。掺杂剂原子是足够的尺寸,使得当它们代替晶格中的原子时,它们足够量地改变了晶格能量,以使得一个相对于另一个的选择性刻蚀能够进行。
【0012】在本发明的实施例中,当晶体膜是硅时,掺杂剂原子可以是硼或碳。在本发明的实施例中,当晶体膜是砷化镓时,掺杂剂原子可以是硼或碳。在本发明的实施例中,当晶体膜是InSb时,掺杂剂可以是硼或碳或磷。足够数量的掺杂剂放入晶体膜102的区域110中,以便产生足以使退化晶体膜102一定程度地变为非退化晶体膜的浓度,从而实现在不刻蚀非退化膜的情况下选择性地刻蚀退化膜。已经发现在1×1015到1×1022原子/cm3之间的掺杂剂浓度范围用以提供合理的刻蚀差异。
【0013】应当认识到,如图1B所示,此时,掺杂剂已经放入晶体膜102的区域110中,但是位于晶格内的空隙部位上。也就是说,此时,掺杂剂还没有被“激活”,因此掺杂剂原子代替了晶格内的原子。
【0014】接着,如图1C所示,区域110中的掺杂剂被激活,从而掺杂剂从晶格内的空隙部位移动并代替晶格内的原子。由于掺杂剂原子的物理尺寸与构成晶格的原子的物理尺寸不同,因此掺杂剂原子取代晶格内原子导致区域110中的晶体膜变形并变为非对称的,由此形成“非退化”晶格区116。由于掺杂剂代替了晶格原子,因此它们使区域116中的晶格变成非对称的,并相对于退化晶格102产生“能量倾卸”。“能量倾卸”产生非退化晶格区116,其具有比晶体膜102的退化晶格部分118更低的晶格能量和更稳定的结构。掺杂剂的激活基本上产生具有非退化区116和退化区118的晶体膜102,如图1C所示。由于非退化晶格区116具有比晶体膜102的退化晶格区118更低的(热力学更稳定的)晶格能量并且比它更稳定,因此与退化晶格区118相比,必须克服更高的激活势垒来刻蚀非退化晶格区116。可以利用用于刻蚀的激活势垒的差异来选择性地刻蚀退化部分118,而不刻蚀非退化部分116。
【0015】接着,如图1D所示,在不刻蚀非退化晶格部分116的情况下,刻蚀掉晶体膜102的退化部分118。由于退化晶格部分118没有非退化晶格部分116稳定,因此对于利用联合反应的刻蚀剂来说,它具有比非退化部分116的激活能量势垒更低的要克服的激活能量势垒。通过利用采用联合反应进行刻蚀的刻蚀剂,所述刻蚀剂能克服退化晶格部分118而不是非退化晶格部分116的激活能量势垒,可以在不刻蚀非退化部分的情况下刻蚀掉退化部分。利用联合反应进行刻蚀的刻蚀剂是如下刻蚀剂:它利用亲核的(或在一些情况下,是亲电子的)附着性,由此在从晶格除去该原子之前,构成晶格的原子(例如硅)直接附着于刻蚀剂上。在本发明的实施例中,用利用联合反应的刻蚀剂刻蚀晶体膜,所述刻蚀剂具有足够的激活能量或化学能量以克服晶体膜102的退化部分118而不是非退化部分116的反应阈值势垒。通过这种方式,在不刻蚀非退化部分116的情况下可以刻蚀掉晶体膜102的退化晶格部分118。通过在晶体膜中形成退化晶格部分118和非退化晶格部分116并利用合适的刻蚀剂,可以获得大于100∶1的刻蚀选择性。
【0016】当晶体膜102是硅时,在不刻蚀掉非退化晶格部分116的情况下,可以通过利用包括非氧化碱性溶液的湿刻蚀剂刻蚀掉晶体膜102的退化晶格部分。在本发明的实施例中,利用氢氧化物刻蚀剂,如但不限于氢氧化钾(KOH)和氢氧化铵来刻蚀硅晶体膜118。在本发明的实施例中,硅刻蚀剂具有在9和11之间的pH值。在本发明的实施例中,用包括氢氧化铵和水的湿刻蚀剂除去退化硅晶体膜118,所述湿刻蚀剂包括1-30%体积的氢氧化铵。在本发明的实施例中,在15-45℃之间的温度下采用氢氧化铵和水刻蚀剂,并在刻蚀工艺期间将兆声波或超声波能量施加于该溶液。在本发明的实施例中,在除去退化晶格部分118的同时,旋转衬底。
【0017】当晶体膜102是砷化镓或InSb时,通过利用湿刻蚀剂可以在不刻蚀非退化晶格部分116的情况下刻蚀掉退化部分118,所述湿刻蚀剂包括氧化剂,如硝酸或在存在酸的情况下的过氧化氢。在本发明的实施例中,利用具有小于4、理想地在2和4之间的pH值的刻蚀剂刻蚀InSb或GaAs的退化部分118。
【0018】除去退化晶格部分118之后,只留下非退化部分116。应当认识到,已经刻蚀了晶体膜102,从而产生与掩模104中的开口114直接对准的构图晶体膜116。另外,利用湿刻蚀剂各向异性地刻蚀了晶体膜102(只在一个方向上刻蚀,垂直方向)。晶体膜102被刻蚀,从而形成具有垂直侧壁的图形晶体膜116,而不需要等离子体刻蚀剂或将衬底暴露于有害等离子体的其它干刻蚀技术。此外,晶体膜102被刻蚀,从而形成图形晶体膜116,而在刻蚀期间不存在掩模。这样,在无掩膜工艺中刻蚀膜102。另外,本发明已经产生了特征结构116,其具有开口114之间的高保真度,并没有经受掩模的横向钻蚀,其通常是与使用掩模和湿刻蚀剂进行膜构图相关的。
【0019】在本发明的实施例中,构图晶体膜116是半导体膜,例如但不限于硅、砷化镓、InSb,并用于形成非平面或三栅晶体管的本体或翼片,如图1E所示。为了形成非平面晶体管,在构图晶体半导体膜116的顶部和侧壁上形成栅极介电层118,如二氧化硅或氮化硅。在构图半导体本体116的顶表面和侧壁上的栅极介电层118上形成栅电极120。在栅电极120的相反侧上、在半导体本体116中形成源/漏区122,如图1E所示。通过在图1D所示的衬底上覆盖淀积栅极介电层118,然后在栅极电介质膜上覆盖淀积栅电极材料,可以形成栅极介电层118和栅电极120。然后用公知光刻和刻蚀技术对栅极电介质膜和栅电极膜进行构图,以形成栅电极120和栅极介电层118。接着,可以利用公知离子注入技术向半导体本体116中注入n型或p型导电性离子,以形成源区和漏区122。
【0020】尽管相对于图1A-1D描述并示出的本发明的实施例开始于具有退化晶格的晶体膜,然后将一部分膜变成非退化晶格,其后在不刻蚀掉非退化晶格部分的情况下刻蚀掉退化晶格部分,但是在其它实施例中,相同的概念可用于选择性地和无掩模地构图晶体膜。例如,在本发明的实施例中,可以首先提供具有非退化晶格的晶体膜。具有非退化晶格的晶体膜可以如上所述那样地形成,即,通过将更大或更小尺寸的掺杂剂代入具有对称结构的晶格中以使晶格变形并给它提供更低、热力学更稳定的晶格能量。例如,开始的晶体膜可以是具有用晶格中的硅原子取代的硼原子的硅晶体膜,以提供具有非退化晶格的晶体膜。然后可以用非退化晶格中的掺杂剂原子取代与晶格原子的尺寸相似的原子或掺杂剂,以使晶体膜的一部分退化或不太非退化。例如,硅原子可以注入到掺杂硼的硅晶体膜中并取代硼原子,以使硅膜退化或不太非退化。然后用适当的刻蚀剂除去退化晶格或不太非退化晶格部分。通过这种方式,未变的非退化晶格部分将保留,改变的退化或不太退化晶格部分被除去。
【0021】在本发明的另一实施例中,其利用改变晶格结构或能量来改变刻蚀选择性,可以提供具有退化晶格结构的晶体膜。然后用取代了退化晶体膜原子的掺杂剂原子掺杂晶体膜的第一区,以提供具有第一非退化度或第一晶格能量的晶格结构的第一区,之后用不同的掺杂剂或更多或更少的相同掺杂剂掺杂退化晶格的第二部分,以提供具有晶格结构的第二区,所述晶格结构具有第二非退化晶格度或第二晶格能量。尽管已经将这两部分形成为“非退化”晶格,但是可利用晶格能量的差异或者“非退化”度来实现刻蚀一个而不刻蚀另一个的选择性刻蚀。这样,本发明的实施例相对于第二部分改变了晶体膜的第一部分的晶格结构或晶格能量,改变的程度使得可以刻蚀一个而不刻蚀另一个。
【0022】图2A-2P表示利用替代栅极技术形成具有金属栅电极的p型器件和具有金属栅电极的n型非平面器件的方法,所述替代栅极技术利用了本发明的选择性刻蚀工艺。替代栅极技术能使栅电极用于由不同材料形成的p型器件和n型器件。通过这种方式,用于p型器件的栅电极可以具有适合于p型器件的功函数(work function),用于n型器件的栅电极可以具有适合于n型器件的功函数。通过使栅电极的功函数适合用于特定器件类型,可以显著改善CMOS集成电路的性能。尽管图2A-2P表示了用于形成具有常规平面器件的CMOS集成电路的替代栅极法,但是相同的技术可以用于形成如图1E所示的具有非平面或三栅器件的CMOS集成电路。
【0023】为了形成根据本发明的实施例的CMOS集成电路,首先提供半导体衬底,如硅单晶衬底202。衬底202包括用于n型器件的掺杂成p型导电性的区域204以及用于p型器件的掺杂成n型导电性的区域206。在衬底202中形成隔离区208,如沟槽隔离区(STI),以电隔离区域204和206。接着,在衬底202上形成牺牲栅极介电层212,如图2A所示。牺牲栅极电介质602理想地由在除去或刻蚀牺牲栅电极材料期间没有充分刻蚀的材料形成,从而在后来除去牺牲栅电极时,它可以保护下面的半导体本体。在牺牲栅电极材料和半导体衬底202由相同材料如硅形成时,这尤其重要。在本发明的实施例中,牺牲栅极电介质是氧化物,如形成为厚度在10-30埃之间的二氧化硅。如果牺牲栅极电介质是生长的电介质,则它将只形成在半导体衬底202的暴露表面上,而不形成在隔离区208上。如果牺牲栅极电介质是淀积膜,则它将覆盖淀积到隔离区208上以及半导体衬底202上,如图2A所示。
【0024】接着,在牺牲栅极电介质上覆盖淀积牺牲栅电极材料212,淀积的牺牲栅电极材料213的厚度对于后来形成的非平面器件的栅电极的高度是所希望的。然后通过公知技术如光刻和刻蚀对牺牲栅电极材料和牺牲栅极电介质进行构图,以形成用于n型器件的牺牲栅电极214和用于p型器件的牺牲栅电极216,如图2B所示。牺牲栅电极214和216被构图成相同的形状,并位于需要后来形成的p型器件的栅电极和n型器件的栅电极的相同位置上。
【0025】牺牲栅电极材料是可以改变为改变的牺牲材料的材料,使得牺牲材料或改变的牺牲材料可以被选择性地刻蚀或除去,而不会刻蚀或除去另一个。也就是说,牺牲栅电极材料由能这样改变的材料形成:1)可以在不刻蚀未改变的牺牲材料的情况下刻蚀或除去改变的牺牲材料,或2)可以在不刻蚀或除去改变的牺牲材料的情况下刻蚀除去未改变的牺牲材料。如下所述,p型牺牲栅电极和n型牺牲栅电极的这种不同将可以实现在分开的时间除去不同的牺牲栅电极,以实现后来用不同材料填充的开口。
【0026】在本发明的实施例中,牺牲材料是具有晶体结构的材料,如多晶膜或单个晶体膜,其可以通过增加刻蚀该膜所需的激活能量而被改变。在本发明的实施例中,晶体膜具有对称或退化晶格,这种晶格可以通过在其中放入掺杂剂以产生非对称晶格或“非退化”晶格来改变。在本发明的实施例中,牺牲膜是一种晶体膜,其可以通过改变晶格以使改变的晶格具有足够的高于未改变的晶格的用于刻蚀的激活能量势垒来改变。在本发明的实施例中,牺牲材料是一种晶体膜,其可以通过用掺杂剂原子代替该膜中的晶格中的原子由此形成改变的晶格来改变,所述改变的晶格具有比未改变的晶格更高的激活能量。换言之,将掺杂剂放在晶格中,以改变牺牲膜并赋予它比未改变的牺牲膜更高的激活势垒。通过这种方式,具有足够高以刻蚀掉未改变的膜但不高到足以刻蚀改变的膜的激活能量的刻蚀剂将只刻蚀未改变的膜,并且将不刻蚀改变的膜。这样,本发明的实施例利用了牺牲材料,这种牺牲材料可以被改变以产生足够不同的晶格能量,使得这种差别可以用于选择性地除去一个而不除去另一个。在本发明的实施例中,n型区上的牺牲栅电极和p型区上的改变的牺牲栅电极的激活能量之间的差足以能够实现刻蚀一个而不刻蚀另一个。此外,在本发明的实施例中,用于p型器件的牺牲栅电极材料和用于n型器件的牺牲栅电极材料都被改变了,但是都是用如下方式改变的:改变的膜之间的差别足以可以相对于另一个对一个进行选择性刻蚀。在本发明的实施例中,牺牲膜是多晶硅膜。在本发明的其它实施例中,牺牲膜是单晶硅膜或外延硅膜。在本发明的实施例中,通过用硼原子取代晶格中的硅原子来改变多晶硅牺牲栅电极材料。
【0027】接着,如果需要的话,可以通过用形成源区和漏区所使用的相同导电类型的杂质在牺牲栅电极214和216的相反侧上掺杂半导体衬底102来形成端部或源/漏延伸。在本发明的实施例中,端部区是利用公知离子注入技术形成的。首先,如图2C所示,在用于n型器件的区域上形成光致抗蚀剂掩模218,并且用于p型器件的区域未被掩蔽。然后将p型杂质离子注入到半导体衬底202中并与用于p型器件的牺牲栅电极216的外边缘对准。牺牲栅电极216防止在端部形成步骤期间半导体衬底202的沟道区209被p型掺杂剂掺杂。此时,牺牲栅电极掺杂了这种p型掺杂剂。注入工艺将p型掺杂剂如硼放入牺牲栅电极216中。然而,由于此时利用高温工艺没有激活掺杂剂,因此这些掺杂剂原子位于晶格的空隙部位,并且没有被晶格中的原子取代。在本发明的实施例中,当半导体衬底202和牺牲栅电极216是硅时,利用硼离子以本领域中公知的剂量和能量掺杂它们,以随后形成具有在1×1019到1×1021原子/cm3之间的硼浓度的端部区211。光致抗蚀剂掩模218防止n型器件区被p型导电性离子掺杂。
【0028】接着,如图2D所示,除去光致抗蚀剂掩模218,在p型器件上形成光致抗蚀剂掩模220,并且使n型器件未被掩蔽。接着,将n型杂质离子在牺牲栅电极的相反侧上注入到半导体衬底202中,以形成端部区213。牺牲栅电极214防止在端部形成步骤期间掺杂半导体衬底202的沟道区215。此时还可以用n型掺杂剂掺杂牺牲栅电极214。由于该掺杂剂没有被高温工艺激活,因此掺杂剂留在牺牲栅电极214和半导体衬底202的晶格中的空隙部位处,并且没有代替晶格中的原子。在本发明的实施例中,当半导体衬底202和牺牲栅电极214是硅时,可以以本领域公知的剂量和能量注入砷或磷原子,以产生具有在1×1019到1×1021原子/cm3之间的n型浓度的端部区。然后除去光致抗蚀剂掩模220。
【0029】接着,如果需要的话,可以沿着牺牲栅电极214和216的相反侧壁形成电介质侧壁隔离物216,如图2E所示。该侧壁隔离物可以利用任何公知技术来形成,如通过在包括牺牲栅电极214和216的顶表面和侧壁的衬底上以及衬底202的暴露表面上覆盖淀积保形侧壁隔离电介质。淀积的电介质隔离材料的厚度大致等于隔离物222所需的宽度。在本发明的实施例中,淀积的电介质隔离材料的厚度在20-350埃之间。隔离材料可以是电介质,如氮化硅、氧化硅、氮氧化硅或其组合。在本发明的实施例中,隔离材料是通过热壁低压化学汽相淀积(LPCVD)工艺形成的氮化硅。然后各向异性地回刻蚀电介质隔离材料,以从牺牲栅电极214和216的水平表面(例如顶表面)以及半导体衬底202和绝缘衬底202的顶表面除去电介质隔离材料,同时留下牺牲栅电极214和216的垂直表面(例如侧壁)上的隔离材料,以形成如图2E所示的侧壁隔离物212。
【0030】此时,如果需要的话,可以将附加的硅形成在衬底202上,以形成升高的源区/漏区。附加硅,如外延硅,可以利用公知的选择性淀积工艺形成在半导体衬底202的暴露表面上。选择性硅淀积工艺将向含硅区域如衬底202上淀积硅,如外延硅,并且不向不含硅区域如侧壁隔离物212上淀积硅。
【0031】接着,可以在牺牲栅电极214和216的相反侧上在半导体衬底202中形成重源/漏接触区。在本发明的实施例中,重源/漏区可以利用离子注入来形成。在这种工艺中,可以在n型晶体管区上形成光致抗蚀剂掩模224,并且使p型晶体管区未被掩蔽。然后将P型掺杂剂离子注入到半导体衬底202中并与形成在其上的外边缘侧壁隔离物222对准,以形成源/漏接触区225。另外,离子注入工艺将p型掺杂剂注入到牺牲栅电极216中。当半导体衬底202是硅以及牺牲栅电极216是多晶硅时,可以以本领域公知的剂量和能量注入硼离子,以随后在多晶硅牺牲栅电极216和硅衬底202中形成在1×1019到1×1021原子/cm3之间的硼浓度。由于此时没有通过高温工艺来激活掺杂剂,因此这些掺杂剂位于晶格中的空隙部位处,并且没有取代晶格中的原子。牺牲栅电极216掩蔽了p型器件的沟道区229使其在重源/漏接触注入期间不被p型杂质掺杂。此外,侧壁隔离物222防止下面的在半导体衬底202中预先形成的端部区211被重源/漏注入掺杂。
【0032】接着,除去光致抗蚀剂掩模224。然后在p型晶体管区上形成光致抗蚀剂掩模226,并且使n型晶体管区未被掩蔽,如图2G所示。接下来,将n型导电性离子在牺牲栅电极214上的侧壁隔离物的相反侧上离子注入到半导体衬底202中,以便形成重掺杂的源和漏接触区。牺牲栅电极214掩蔽了n型器件的沟道区215使其在重源/漏形成步骤期间不被掺杂。另外,侧壁隔离物222防止下面的在半导体衬底202中预先形成的端部区213被重源/漏注入掺杂。重源/漏注入还用n型杂质掺杂牺牲栅电极214。由于没有利用高温工艺激活掺杂剂,因此这些掺杂剂位于牺牲栅电极214和半导体衬底202的晶格中的空隙部位处,并且没有代替晶格中的原子。在本发明的实施例中,当半导体衬底202和牺牲栅电极是硅时,可以以本领域公知的剂量和能量注入磷原子,以随后形成在1×1019到1×1021原子/cm3之间的磷浓度。
【0033】接着,如图2H所示,对衬底进行退火,以激活位于半导体衬底202中的掺杂剂。此外,激活退火还激活了放入牺牲栅电极214和216中的掺杂剂。即,现在将衬底退火到一定温度和一定时间,足以使半导体衬底202中的n型掺杂剂和p型掺杂剂从空隙部位移动,并代替晶格中的原子,以形成n型源和漏区以及p型源和漏区。在本发明的实施例中,退火使得形成具有在1×1019原子/cm3到1×1021原子/cm3范围内的浓度的端部区和重源/漏接触区。该退火还使得放入到牺牲栅电极214中的n型掺杂剂从空隙部位移动,并代替牺牲栅电极214的晶格中的原子。此外,该退火还使得p型掺杂剂从牺牲栅电极216中的空隙部位移动,并代替牺牲栅电极216的晶格中的原子。
【0034】在本发明的实施例中,当牺牲栅电极是多晶硅时,硼原子代替牺牲栅电极216的晶格中的硅原子,磷原子代替牺牲栅电极214的晶格中的硅原子。由于硼原子小于硅原子,因此硼原子与晶格中的硅原子形成的键比硅原子形成的键更近和更紧。结果是硅晶格整个不再是对称的,导致晶格的“能量倾卸”。当多晶硅牺牲栅电极216中的硅晶格变得不太对称或变形时,可以将该晶格称为“非退化”。与未掺杂多晶硅膜或具有对称晶格或“退化”晶格的多晶硅膜相比,使牺牲栅电极216中的晶格变成“非退化”以及得到的能量倾卸使掺杂硼的多晶硅牺牲硅膜变得更稳定并需要更高的激活能量来刻蚀。这样,如图2H所示,牺牲多晶硅栅电极216中的硼掺杂剂的热激活将牺牲栅电极216转换成具有不同于未改变的牺牲栅电极的刻蚀特性的改变的牺牲栅电极228。应该注意,多晶牺牲栅电极214中的磷原子的激活还使得硅晶格变形或变成“非退化”,但是其程度比牺牲多晶硅栅电极216中的硼原子轻得多(这是因为磷原子具有接近于硅原子尺寸的物理尺寸)。由于磷掺杂剂只使多晶硅牺牲栅电极214的硅晶格稍微变形(即只稍微地使晶格变成“非退化”),因此牺牲栅电极214可以被认为是未改变的。注入和激活的结果是形成改变的牺牲栅电极228和未改变的牺牲栅电极214,它们具有不同的晶格能量和能量势垒,其可用于实现未改变的牺牲栅电极的选择性刻蚀而不刻蚀改变的牺牲栅电极。
【0035】接着,如图2J所示,在衬底上覆盖淀积介电层230。介电层形成的厚度足以完全覆盖包括牺牲栅电极214和改变的牺牲栅电极228的衬底。介电层230由可以相对于改变的和未改变的牺牲栅电极228和214进行选择性刻蚀的材料形成。也就是说,电介质材料由一种材料形成,由此可以除去牺牲栅电极214和改变的牺牲栅电极228,而没有明显地刻蚀掉介电层230。覆盖淀积介电层230之后,如通过化学机械平面化对介电层进行平面化,直到电介质膜的顶表面与牺牲栅电极214和改变的牺牲栅电极228成平面,并暴露牺牲栅电极214和改变的牺牲栅电极228的顶表面为止,如图2H所示。
【0036】接着,如图2J所示,现在除去牺牲栅电极214不除去牺牲栅电极228。除去牺牲栅电极214之后,还除去牺牲栅极介电层210。除去牺牲栅电极214形成了将要形成n型器件的栅电极的开口232。除去牺牲栅电极214和牺牲介电层210暴露了n型器件的半导体衬底214的沟道区215,如图2J所示。
【0037】牺牲栅电极214是用刻蚀剂除去的,所述刻蚀剂可以刻蚀掉牺牲栅电极材料214而没有明显地刻蚀掉改变的牺牲栅电极材料228。在本发明的实施例中,用湿刻蚀剂除去牺牲栅电极214。在本发明的实施例中,湿刻蚀剂具有大于100∶1的牺牲栅电极材料对于改变的牺牲栅电极材料的选择性(即湿刻蚀剂以比改变的牺牲栅电极材料快至少100倍的速度刻蚀牺牲栅电极材料)。在本发明的实施例中,n型多晶硅牺牲栅电极材料214是用湿刻蚀剂除去的。在本发明的实施例中,施加兆声波能量,同时用湿刻蚀剂除去牺牲栅电极214。在本发明的实施例中,用包括金属氢氧化物如但不限于氢氧化钾(KOH)或氢氧化铵(NH4OH)的湿刻蚀剂除去n型多晶硅牺牲栅电极材料214。在本发明的实施例中,用包括氢氧化铵和水的湿刻蚀剂除去牺牲多晶牺牲硅栅电极214,所述湿刻蚀剂包括1-30%体积的氢氧化铵。在本发明的实施例中,在刻蚀工艺期间,将氢氧化铵和水刻蚀剂加热到15-45℃的温度,并向溶液施加兆声波或超声波能量。在本发明的实施例中,旋转衬底,同时除去牺牲栅电极214。在本发明的实施例中,用刻蚀剂除去牺牲栅电极214,所述刻蚀剂不具有足够的能量来克服改变的牺牲栅电极228的晶格的激活能量势垒。通过这种方式,在刻蚀牺牲栅电极214期间,改变的牺牲栅电极228保持不被刻蚀。本发明实现了在不除去p型器件的牺牲栅电极的情况下来除去n型器件的牺牲栅电极214,而且这样做并不需要掩摸或其它光刻处理步骤。这样,利用无掩模方法除去了牺牲栅电极214,由此节省了昂贵的光刻工艺步骤并使本发明成为可制造的。一旦已经除去了牺牲栅电极材料214,刻蚀剂就停止在牺牲介电层210上。在本发明的实施例中,牺牲介电层210是氧化物,并具有相对于牺牲栅电极的至少10∶1的选择性。接着,用刻蚀剂除去牺牲栅极介电层210,如但不限于含水的氢氟酸。
【0038】接着,在开口232中形成用于n型器件的栅极介电层和栅电极材料,如图2K所示。首先,在衬底上覆盖淀积栅极电介质膜234。栅极电介质材料覆盖了半导体衬底202的沟道区215。栅极电介质材料可以用任何公知工艺来形成。在本发明的实施例中,使用热氧化工艺,如干/湿氧化来生长栅极介电层234,如二氧化硅或氮氧化硅介电层。在本发明的另一实施例中,利用保形淀积工艺如CVD或ALD来淀积高K栅极介电层。接着,在栅极电介电234上覆盖淀积用于n型器件的栅电极材料236。栅电极材料236可以是任何公知栅电极材料。在本发明的实施例中,栅电极材料具有适合于n型器件的功函数。在本发明的实施例中,栅电极具有在3.9eV-4.2eV之间的功函数。在本发明的实施例中,当半导体衬底202是p型硅时,栅电极材料选自具有在大约3.9eV和大约4.2eV之间的功函数的铪、锆、钛、钽、和铝。接着,对栅电极材料236进行平面化,直到暴露介电层230的顶表面为止,如图2L所示。一旦对栅电极材料和栅极电介质材料进行回抛光或从顶部电介质膜230除去它,则形成用于n型器件的栅电极238。
【0039】接着,如图2M所示,现在除去改变的牺牲栅电极228而不除去用于n型器件的栅电极238。除去改变的牺牲栅电极228之后,除去牺牲栅电极氧化物602。改变的牺牲栅电极228和牺牲栅极介电层210的除去暴露了非平面p型器件的半导体衬底202的沟道区209,如图2M所示。此外,除去改变的牺牲栅电极228在介电层220中形成开口240,后来在该开口中将要形成用于p型器件的栅电极。在本发明的实施例中,利用包括氢氧化四甲铵和水的湿刻蚀剂除去了掺杂硼的多晶硅牺牲栅电极228。在本发明的实施例中,氢氧化四甲铵包括10-35%体积的溶液。在本发明的实施例中,在刻蚀期间将氢氧化四甲铵溶液加热到60-95℃之间的温度。在本发明的实施例中,在刻蚀工艺期间施加声波能量,如超声波或兆声波能量。声波能量提供对刻蚀剂的激励,其能够从开口240除去来自改变的牺牲栅电极228的刻蚀残余物,并允许新的刻蚀剂进入沟槽240中,以刻蚀改变的牺牲栅极228。
【0040】在本发明的实施例中,牺牲栅电极刻蚀剂对于牺牲栅极介电层具有选择性(即不刻蚀或只稍微刻蚀牺牲栅极电介质),使得牺牲栅极电介质210用作改变的牺牲栅电极刻蚀的腐蚀停(etch stop)。通过这种方式,保护下面的半导体衬底202不被刻蚀剂刻蚀。希望牺牲栅电极228相对于牺牲栅极电介质的刻蚀选择性为至少10∶1。
【0041】接着,除去牺牲栅极电介质210。在本发明的实施例中,牺牲栅极电介质210是氧化物,并可以用包括含水的氢氟酸的刻蚀剂除去。
【0042】接着,如图2N所示,在衬底上覆盖淀积用于p型器件的栅极电介质膜242。栅极电介质膜242覆盖半导体衬底202的沟道区209的顶表面和侧壁。栅极介电层642可以用任何公知的工艺来形成。在本发明的实施例中,栅极电介质是热生长的氧化物,如氧化硅或氮氧化硅。在本发明的实施例中,栅极电介质是通过保形工艺如CVD或ALD淀积的淀积氧化物。栅极介电层可包括高K绝缘膜,其选自氧化钽、氧化钛、氧化铪、氧化锆、PZT、BST、氧化铝和其硅酸盐。栅极介电层242的覆盖淀积在衬底202上以及栅电极238的暴露部分的顶部上形成栅极介电层。接着,在栅极介电层238上覆盖淀积用于p型器件的栅极介质材料244。栅电极材料244可以是任何公知的栅电极材料。在本发明的实施例中,栅电极材料是具有适合于p型器件的功函数的金属膜。在本发明的实施例中,当半导体衬底202是n型硅时,栅电极材料包括钌、钯、铂、钴、镍、和具有在大约4.9eV和5.2eV之间的功函数的导电金属氧化物。在本发明的实施例中,栅电极244具有在4.9-5.2eV之间的功函数。
【0043】接着,如图20所示,从顶表面电介质膜230除去形成在电介质膜230的顶表面上的栅电极材料244和栅极介电层242,以形成用于p型器件的栅极246,并暴露用于n型器件的栅电极238。例如,可以利用化学机械抛光或其它合适方法除去形成在介电层230顶部上的栅极介电层和栅电极材料244。此时,已经形成了利用替换栅极工艺制造具有金属栅电极的n型器件和具有金属栅电极的p型器件。如果需要的话,现在可以除去介电层230,以暴露p型器件和n型器件,如图2P所示。现在利用处理来形成例如源区和漏区上的硅化物,并将n型晶体管和p型晶体管互连在一起成为功能集成电路,以形成互补金属氧化物半导体(CMOS)集成电路。

Claims (31)

1、一种构图晶体膜的方法,包括:
形成具有退化晶格的晶体膜,所述退化晶格包括在第一区和第二区中的第一原子;
将掺杂剂放入到所述第一区中的所述晶体膜中的空隙部位中;
激活所述掺杂剂,使得所述掺杂剂代替所述晶格中的所述第一原子,以在所述第一区中形成非退化晶格,所述第二区保持退化晶格;以及
将所述第一区和所述第二区暴露于湿刻蚀剂,其中所述湿刻蚀剂刻蚀所述第二区中的所述退化晶格,而不刻蚀所述第一区中的所述非退化晶格。
2、根据权利要求1的方法,其中所述晶体膜是半导体膜。
3、根据权利要求2的方法,其中所述半导体膜是硅膜。
4、根据权利要求3的方法,其中所述硅膜是多晶膜。
5、根据权利要求1的方法,其中所述晶体膜选自砷化镓和InSb。
6、根据权利要求1的方法,其中所述刻蚀剂利用联合反应来刻蚀所述退化晶格。
7、根据权利要求3的方法,其中所述刻蚀剂是非氧化碱性溶液。
8、根据权利要求7的方法,其中所述刻蚀剂包括具有在9和11之间的pH值的氢氧化物。
9、根据权利要求5的方法,其中所述刻蚀剂包括存在酸的氧化剂。
10、根据权利要求9的方法,其中所述刻蚀剂包括选自硝酸和过氧化氢的氧化剂,并且其中所述刻蚀剂具有在2和4之间的pH值。
11、根据权利要求1的方法,其中所述第一区中的所述非退化晶格具有第一晶格能量,所述第二区中的所述退化晶格具有第二晶格能量,其中所述第二晶格能量比所述第一晶格能量在热力学上更高(相对不太稳定)。
12、根据权利要求1的方法,其中所述非退化晶格具有对所述刻蚀剂的第一激活能量势垒,所述退化晶格具有对所述刻蚀剂的第二激活能量势垒,其中所述第二激活能量势垒低于所述第一激活势垒。
13、根据权利要求12的方法,其中所述刻蚀剂具有大于所述第二激活能量势垒和小于所述第一激活能量势垒的化学能量。
14、一种构图晶体膜的方法,包括:
在晶体膜上形成具有开口的掩模,所述晶体膜具有包括第一原子的晶格,所述开口形成在第一区上,所述掩膜覆盖第二区;
经过所述开口将掺杂剂注入到所述开口下面的所述晶体膜的所述第一区中;
除去所述掩模;
加热所述晶体膜,使得所述掺杂剂代替所述第一区中的所述晶体膜中的所述晶格的所述第一原子;以及
将所述第一区和所述第二区暴露于刻蚀剂,其中所述刻蚀剂刻蚀所述第二区而不刻蚀所述第一区。
15、根据权利要求14的方法,其中在所述第一区中包括掺杂剂的晶格是非退化晶格。
16、根据权利要求15的方法,其中所述第二区中的所述晶格是退化晶格。
17、根据权利要求14的方法,其中所述掺杂剂小于所述第一原子。
18、根据权利要求14的方法,其中所述掺杂剂大于所述第一原子。
19、根据权利要求14的方法,其中所述第一原子是硅,并且其中所述掺杂剂原子是硼。
20、一种构图晶体模的方法,包括:
提供具有退化晶格的晶体膜,所述退化晶格包括在第一区和第二区中的第一原子;
用掺杂剂原子代替所述第一区中的所述退化晶格中的所述第一原子,以在所述第一区中形成非退化晶格;以及
将具有所述非退化晶格的所述第一区和具有所述退化晶格的所述第二区暴露于刻蚀剂,其中所述刻蚀剂刻蚀所述第二区而不刻蚀所述第一区。
21、根据权利要求20的方法,其中所述晶体膜是硅。
22、根据权利要求21的方法,其中所述掺杂剂原子是硼。
23、一种构图晶体膜的方法,包括:
提供在第一区和第二区中具有非退化晶格的晶体膜;
用原子代替所述第一区中的所述非退化晶格,以使所述第一区中的所述晶格变为具有退化晶格或与所述第二区中的所述晶格相比非退化程度更低的晶格的晶格;以及
将所述第一区和所述第二区暴露于刻蚀剂,其中所述刻蚀剂刻蚀所述第一区中的所述退化晶格或所述非退化程度较低的晶格,而不刻蚀所述第二区中的所述非退化晶格。
24、根据权利要求23的方法,其中具有所述非退化晶格的所述晶体膜是硼掺杂的硅膜。
25、根据权利要求24的方法,其中所述原子是硅原子。
26、一种形成集成电路的方法,包括:
在半导体衬底的第一沟道区上形成牺牲栅电极,并在所述半导体衬底的第二沟道区上形成第二牺牲栅电极;
改变所述第一牺牲栅电极和/或所述第二牺牲栅电极,使得可以用刻蚀剂刻蚀所述第一牺牲栅电极,而不刻蚀所述第二牺牲栅电极;
在所述第一牺牲栅电极上和所述第二牺牲栅电极上形成介电层;
对所述介电层进行平面化,以便暴露所述第一牺牲栅电极和所述第二牺牲栅电极的顶表面;
在改变所述第一牺牲栅电极和/或所述第二牺牲栅电极之后,用所述刻蚀剂刻蚀所述第一牺牲栅电极,而不刻蚀所述第二牺牲栅电极,以形成第一开口并暴露所述半导体衬底的所述第一沟道区;
在所述半导体衬底的所述第一沟道区上以及在所述电介质膜的顶表面上淀积第一金属膜;
从所述电介质的顶部除去所述第一金属膜,以形成第一金属栅电极;
除去所述第二牺牲栅电极材料,以形成第二开口;
在所述介电层上并在所述第二开口中形成不同于所述第一金属膜的第二金属膜;以及
从所述介电层的顶表面除去所述第二金属膜,以形成第二金属栅电极。
27、根据权利要求26的半导体器件,其中所述第一金属膜具有在3.9eV和4.2eV之间的功函数。
28、根据权利要求26的方法,其中所述第二金属膜具有在4.9eV到5.2eV之间的功函数。
29、一种选择性地构图晶体膜的方法,包括:
提供具有晶格的晶体膜,所述晶格在第一区和第二区中具有第一晶格能量;以及
改变所述第一区和/或所述第二区中的所述晶格,以在所述第一区和所述第二区之间产生晶格能量差;
将所述第一区和所述第二区暴露于刻蚀剂,所述刻蚀剂刻蚀所述第一区或所述第二区,而不刻蚀另一区域。
30、根据权利要求29的方法,其中晶体膜是硅膜。
31、根据权利要求30的方法,其中通过用硼原子掺杂来改变所述第一区。
CNA2004800395316A 2003-12-30 2004-12-23 改变膜的刻蚀选择性的方法 Pending CN1902739A (zh)

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KR20060105871A (ko) 2006-10-11
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