CN1742375A - 应变沟道鳍片场效应晶体管 - Google Patents

应变沟道鳍片场效应晶体管 Download PDF

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CN1742375A
CN1742375A CNA200480002593XA CN200480002593A CN1742375A CN 1742375 A CN1742375 A CN 1742375A CN A200480002593X A CNA200480002593X A CN A200480002593XA CN 200480002593 A CN200480002593 A CN 200480002593A CN 1742375 A CN1742375 A CN 1742375A
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crystalline material
fin
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CN100521230C (zh
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S·达克什纳摩西
J·X·安
Z·克瑞沃卡皮奇
汪海宏
俞斌
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Innovation Core Making Co ltd
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
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    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT

Abstract

一种半导体结构，包括鳍片(205)和形成于该鳍片上的层(305)。该鳍片(205)包括具有矩形横剖面和许多表面的第一结晶材料。该层(305)形成于该等表面上并包括第二结晶材料。该第一结晶材料较的该第二结晶材料具有不同的晶格常数，以令该层(305)内产生张力应变。

Description

应变沟道鳍片场效应晶体管
技术领域
本发明大体上关于晶体管，而且尤其关于鳍片场效晶体管(fin fieldeffect transistor，FinFET)。
背景技术
缩小装置尺寸已经是驱使改进集成电路性能和减少集成电路成本的主要因素。由于相关于现有的栅极氧化物厚度和源极/漏极(S/D)接面深度的限制，要缩小现有的块状(bulk)金属氧化物半导体场效晶体管(MOSFET)装置尺寸低于0.1微米(μm)的制造过程代即使不是不可能，那也是很困难的。因此，需要有新的装置结构和新的材料以改进FET的性能。
双栅极MOSFET表现为可选择用来成功地替代现用平面MOSFET的新装置。于双栅极MOSFET中，使用双栅极以控制沟道系有效地抑制了短沟道效应。FinFET为最新的双栅极结构并且包括形成于垂直鳍片中的沟道。FinFET于布线和制造上相似于现用的平面MOSFET。FinFET相较于其它的双栅极结构，也提供了沟道长度的范围、CMOS兼容性和大封装密度。
发明内容
根据本发明，提供一种使用垂直形成的自行对准于鳍片沟道的应变沟道层(strained channel layer)的FinFET晶体管。应变沟道层可包括结晶体材料，该结晶体材料为晶格常数不匹配FinFET的鳍片的结晶体材料者。晶格常数不匹配(1attice constant mismatch)使得应变沟道层内产生张力应变(tensile strain)，该张力应变增加载流子(carrier)的迁移率。增加载流子迁移率会转而增加FinFET晶体管的驱动电流，因此而改进了FinFET的性能。
于下列的说明中将部分地提出本发明的额外的优点和其它的特征，而提出说明的部分，对于熟悉此项技术的一般技术人员而言于检视下列的说明后，对本发明将变得很清楚，或者他们可从实作本发明中而习得本发明。如详细指出于所附权利要求书中，可实现和获得本发明的优点和特征。
依照本发明，藉由包含有鳍片的半导体结构，可部分地达成上述和其它的优点。该鳍片包括第一结晶体材料和多个表面。该结构进一步包括形成于该多个表面的至少一部分的层，该层包括第二结晶体材料。该第一结晶体材料较的该第二结晶体材料具有不同的晶格常数而引起该层内的张力应变。
依照本发明的另一态样，提供一种晶体管。该晶体管包括鳍片，该鳍片尚包括第一结晶体材料以及第一和第二端部。该第一结晶体材料具有第一晶格常数。该晶体管尚包括形成邻近于该鳍片的第一和第二端部的源极和漏极区域。该晶体管也包括形成于该鳍片的至少一部分的第二结晶体材料的第一层。该第二结晶体材料具有第二晶格常数，其中该第一晶格常数要大于该第二晶格常数。该晶体管额外地包括形成于该第一层的至少一部分的电介质层，和形成于该电介质层的至少一部分的栅极电极。
依照本发明的又一态样，提供一种形成半导体装置的方法。该方法包括形成鳍片，该鳍片包括第一结晶体材料和多个表面。该方法进一步包括于该多个表面的至少一部分上形成第一层。该第一层包括第二结晶体材料，其中该第一结晶体材料的晶格常数与第二结晶体材料不匹配，以于该第一层内产生张力应变。
由下列的详细说明，本发明的其它的优点和特征，对于熟悉此项技术的一般技术人员而言，将变得很容易了解。所示和说明的实施例，提供考量用来施行本发明的最佳模式的说明。本发明于各种不同的态样可作修饰，而全然不会偏离本发明的范围。因此，各附图将作为说明的性质，而不是要用来限制本发明。
附图说明
可参考下列所附附图，其中于各图中具有相同组件符号指示的各组件系表示相同的组件。
图1显示根据本发明可用来形成FinFET的鳍片的基板的范例层；
图2A显示根据本发明的范例鳍片；
图2B显示根据本发明的图2A的范例鳍片的横剖面图；
图2C和图2D显示根据本发明的形成邻接于第2A和图2B的鳍片的范例源极和漏极区域；
图3A显示根据本发明的形成于鳍片上的应变层的横剖面图；
图3B显示根据本发明的形成于鳍片和源极和漏极区域上的图3A的应变层的上视图；
图4A显示根据本发明的形成于鳍片上的栅极电介质和栅极电极的横剖面图；
图4B显示根据本发明的形成于鳍片上的图4A的栅极电介质和栅极电极的上视图；
图5显示根据本发明另一实施例的于第2A和图2B的鳍片下方的应变绝缘体的示意图；以及
图6显示根据本发明另一实施例的镶嵌源极/漏极再生长。
具体实施方式
本发明的下列详细说明将参照所附各附图。于不同附图中相同的组件符号可视为相同或相似的组件。而且，下列的详细说明并不限制本发明。反之，本发明的范围系由所附权利要求书所界定。
根据本发明，提供了一种增加沟道迁移率的FinFET。根据本发明，垂直形成的应变沟道层系自行对准于FinFET的鳍片沟道。应变沟道层可包括与FinFET的鳍片的结晶体材料晶格不匹配的结晶体材料，而使得张力应变于应变沟道层内产生。
所引起的张力应变增加应变沟道层的载流子迁移率，因此，增加FinFET的驱动电流。
图1显示依照本发明的实施范例所形成的基板100的横剖面图。根据本发明，基板100可以是绝缘层上覆硅(silicon on insulator，SOI)结构，该结构例如包括形成于埋藏氧化物层110上的鳍片沟道层105。埋藏氧化物层110可形成于硅层上(图中未显示)。鳍片沟道层105的厚度例如可以是从大约500埃()至大约2000埃的厚度，且埋藏氧化物层110的厚度例如可以是从大约1000埃至大约3000埃的厚度。
鳍片沟道层105可包括具有晶格常数大于选用于应变沟道层的结晶体材料的晶格常数的结晶体材料(相关于下列第3A和图3B的说明)。举例而言，若选择硅用于应变沟道层，则鳍片沟道层105可包括具有晶格常数大于硅的晶格常数的结晶体材料。例如，鳍片沟道层105可包括SixGe(1-x)，而x约等于0.7。可适当地选择使用其它的x值。熟悉此项技术者将了解到，可以使用除了SixGe(1-x)以外的其它的结晶体材料，而使得材料的晶格常数要大于选择用于应变沟道层的结晶体材料的晶格常数。于一些实施例中，基板100可藉由晶圆结合磊晶SixGe(1-x)至氧化物/硅基板晶圆而形成。然而，熟悉此项技术者将了解到，可以使用其它现用的技术来形成基板100。
如第2A和图2B中所示，于形成基板100之后，可由鳍片沟道层105形成垂直鳍片205。例如，可形成鳍片205具有10纳米(nm)至15纳米范围的宽度(w)。可使用任何现用的技术，包括但不限于现用的光学微影术和蚀刻制造过程，而由鳍片沟道层105形成鳍片205。
接着形成鳍片205后，可形成源极210和漏极215邻接于个别的鳍片205的端部，如图2C和图2D中所示。例如，可藉由沉积结晶体材料层于鳍片205上而形成源极210和漏极215区域。例如，可使用现用的光学微影术和蚀刻制造过程，而由结晶体材料层形成源极210和漏极215区域。然而，熟悉此项技术者将了解到，可使用任何现用的其它技术来形成源极210和漏极215区域。源极210和漏极215区域可包括譬如像是SixGe(1-x)，x约等于0.7的结晶体材料。
于形成源极210和漏极215区域后，可在鳍片205、源极210和漏极215上形成应变层305，如第3A和图3B中所示。可使用任何适当的现用制造过程而于鳍片205、源极210和漏极215上形成应变层305。于一些实施范例中，例如，可使用选择的磊晶沉积制造过程而于鳍片205、源极210和漏极215上形成应变层305。应变层305可包括结晶体材料，该结晶体材料的晶格常数要小于用于鳍片205的结晶体材料的晶格常数。以晶格不匹配于鳍片205和应变层305之间，则会在应变层305上产生张力应变。例如，应变层305可形成具有厚度t大约为鳍片205的宽度w的1/2至1/3。例如，应变层305的厚度t可以是5纳米(nm)。应变层305可包括硅，但是不限于硅。熟悉此项技术者将了解到，可替代使用其它的具有晶格常数小于用于形成鳍片205的结晶体材料者的结晶体材料。
于形成应变层305后，可于鳍片205上未由源极210和漏极215所覆盖的部分形成栅极电介质405和栅极电极410，如第4A和图4B中所示。栅极电介质405可包括薄层的电介质材料，譬如SiO、SiO2、SiN、SiON、HFO2、ZrO2、Al2O3、HFSiO(x)、ZnS、MgF2、或其它的电介质材料。栅极电极410可形成于栅极电介质405上，并包括例如多晶硅层。可使用任何现用的制造过程，譬如例如现用的沉积和图案化制造过程，而将栅极电介质405和栅极电极410形成于鳍片205上。形成栅极电介质405和栅极电极410于鳍片205上，因而产生FET侧壁垂直沟道，该沟道包括于鳍片205的二个垂直表面的薄应变层305。应变层305透过由应变层305与鳍片205间的晶格不匹配所引起的于应变层305中的张力应变，而提供改良的载流子迁移率。此载流子迁移率的增强能增加使用第4A和图4B中所示半导体结构所建立的FinFET晶体管的驱动电流。
范例的应变绝缘体
图5显示范例的应变绝缘体505，根据本发明，应变绝缘体505可形成于FinFET的鳍片下，譬如第2A和图2B中所示的鳍片205的下方。鳍片205可形成于应变绝缘体505的绝缘材料上，而使得鳍片205和应变绝缘体505的结晶体材料为晶格不匹配。鳍片205和应变绝缘体505间的晶格不匹配产生鳍片205中的张力应变，该鳍片205因而改良FinFET的载流子迁移率。熟悉此项技术者将了解到，可以使用任何适当的具有晶格常数不匹配鳍片205的结晶体材料的绝缘材料作为应变绝缘体505。
范例的源极/漏极再生长制造过程
图6显示根据本发明另一实施例的范例的镶嵌源极/漏极再生长。在基板上形成作用区600与鳍片605之后，可沉积四乙基正硅酸盐(TEOS)于鳍片605和作用区600上，然后予以研磨。然后可使用屏蔽(屏蔽1)610以打开栅极区域615。可削薄鳍片605，并且可藉由沉积和研磨多晶硅于栅极区域615而形成栅极620。可使用第二屏蔽(屏蔽2)625以打开源极和漏极区域630。可蚀刻于经打开的源极和漏极区域630内的作用区600的氮化物层，以曝露源极和漏极区域630。由该曝露的区域，可选择地再生长硅以产生源极635和漏极640。
于前述的说明中，为了提供对本发明的完全了解，而提出了许多特定的详细说明，譬如特定的材料、结构、化学物、制造过程、等等。然而，可不须凭借此处所特别提出的详细说明而施行本发明。于其它的例子中，为了不致模糊了本发明的目标，已知的制造过程结构未予详细说明。在施行本发明中，可使用现有的光学微影术和蚀刻技术，而因此于此处不再详细提出此等技术的细部说明。
于此说明书中仅显示和说明了本发明的较佳实施例和其各种变化的少数例子。应了解到本发明能够使用于各种其它的组合和环境中，并在此处所表现的发明概念范围内能够作修改。

Claims (10)

1.一种半导体装置，包括：
鳍片(205)，包括第一结晶体材料和多个表面；以及
第一层(305)，形成于该多个表面的至少一部分上，该第一层(305)包括第二结晶体材料，其中该第一结晶体材料较的该第二结晶体材料具有不同的晶格常数，以于该第一层内产生张力应变。
2.根据权利要求1所述的半导体装置，其中该鳍片(205)具有矩形的横剖面，且其中该第一结晶体材料包括晶格常数大于该第二结晶体材料的晶格常数的结晶体材料。
3.根据权利要求1所述的半导体装置，其中该第二结晶体材料包含硅，且其中该第一结晶体材料包括具有晶格常数大于硅的结晶体材料。
4.根据权利要求3所述的半导体装置，其中该第一结晶体材料包括SixGe(1-x)，而其中x约等于0.7。
5.根据权利要求1所述的半导体装置，还包括：
第二层(405)，形成于该第一层(305)的至少一部分上，该第二层(405)包括电介质；以及
栅极电极(410)，形成于该第二层(405)的至少一部分上，该栅极电极(410)包括多晶硅。
6.一种晶体管，包括：
鳍片(205)，包括具有第一晶格常数的第一结晶体材料，该鳍片(205)还包括第一和第二端部，其中该第一结晶体材料包括SixGe(1-x)，而其中x约等于0.7；
源极(210)和漏极(215)区域，形成邻近于该鳍片(205)的该第一和第二端部；
形成于该鳍片(205)的至少一部分的第二结晶体材料的第一层(305)，该第二结晶体材料具有第二晶格常数，其中该第一晶格常数系大于该第二晶格常数，且其中该二结晶体材料包括硅；
形成于该第一层(305)的至少一部分上的电介质层(405)；以及
形成于该电介质层(405)的至少一部分上的栅极电极(410)，其中该栅极电极(410)包括第三结晶体材料且其中该第三结晶体材料包括多晶硅，
其中该第一晶格常数要大于该第二晶格常数，以于该第一层内产生张力应变，且其中该张力应变增加于该第一层中的载流子迁移率。
7.一种形成半导体装置的方法，包括：
形成鳍片(205)，该鳍片(205)包括第一结晶体材料和多个表面；以及
于该多个表面的至少一部分上形成第一层(305)，该第一层(305)包括第二结晶体材料，其中该第一结晶体材料为晶格常数不匹配于该第二结晶体材料者，以于该第一层内产生张力应变。
8.根据权利要求7所述的方法，还包括：
选择该第一结晶体材料而使得该第一结晶体材料具有晶格常数大于该第二结晶体材料的晶格常数。
9.根据权利要求7所述的方法，还包括：
选择硅作为该第二结晶体材料用于形成该第一层(305)；以及
选择该第一结晶体材料而使得该第一结晶体材料具有大于硅的晶格常数。
10.根据权利要求7所述的方法，还包括：
选择SixGe(1-x)作为该第一结晶体材料用来形成该鳍片(205)；
选择x约等于0.7；
于该第一层(305)上形成第二层(405)，该第二层(405)包括电介质；以及
于该第二层(405)上形成栅极电极(410)，该栅极电极(410)包括多晶硅。
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