CN1726595A - 致密双平面器件 - Google Patents

致密双平面器件 Download PDF

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CN1726595A
CN1726595A CNA2003801062984A CN200380106298A CN1726595A CN 1726595 A CN1726595 A CN 1726595A CN A2003801062984 A CNA2003801062984 A CN A2003801062984A CN 200380106298 A CN200380106298 A CN 200380106298A CN 1726595 A CN1726595 A CN 1726595A
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CN100505303C (zh
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E·J·诺瓦克
B·雷尼
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Microsoft Technology Licensing LLC
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Abstract

一种MOS器件，具有形成在衬底(10)上的第一和第二独立半导体管体(40N、40P)。第一独立半导体管体(40N或40P)具有相对于第二独立半导体管体(40P或40N)的第一部分呈非直角、非平行取向的第一部分。所述第一和第二独立半导体管体(40N、40P)的这些部分具有各自的第一和第二结晶取向。第一栅电极(60)以非直角的角度经过所述第一独立半导体管体(40N或40P)的所述第一部分的至少一部分，第二栅电极(60)同样经过第二独立半导体管体(40P或40N)的第一部分。

Description

致密双平面器件
相关申请的交叉引用
参考共同待审并受让于本发明的受让人的于2001年12月4日提交的题目为“Multiple-Plane FinFET CMOS”的美国专利申请10/011,846和于2002年4月12日提交的题目为“Fin Memory Cell and Method ofFabrication”的10/063,330。
技术领域
本发明通常涉及CMOS技术和超大规模集成电路，更具体地说，涉及能够在双栅极CMOS技术中使用高迁移率结晶平面的方法和结构。
背景技术
互补金属氧化物半导体(CMOS)已经成为超大规模集成电路(VLSI)的选择技术，其中可以制造差不多好几千万个(或更多)晶体管以形成单个集成电路。
为了提供更大数量的具有更高速度的晶体管，现有技术中已经提议出的一种选择是利用独立硅轨(silicon rail)作为晶体管的管体(body)。这些管体或所谓的“鳍片(fin)”垂直于晶片表面所限定的平面。参见例如Muller等人的美国专利6,252,284。
由这种鳍片构造的双栅极晶体管可以提供较低的漏电流并能够按比例缩小到更小的栅极长度。参见2001 IEEE International Solid State CircuitsConference，Page 7.4中的Tang等人的“FinFET-Aquasi-PlanrDouble-Gate MOSFET”。
还知道，在如硅的半导体晶体中，空穴和电子的迁移率是其中形成晶体管沟道的结晶平面的函数。例如在硅中，电子在{100}等效平面中具有它们最大的迁移率，而空穴在{110}等效平面中具有它们最大的迁移率，如在1994 IEEE Trans.on Electron Device，V.41，No.12，Dec.1994，pp.2357-2368中的Takagi等人的“On the Universality of Inversion Layer Mobility in SiMOSFETs：Part I-Effects of Substrate Impurity Concentration”中所讨论的那样。其它类型的半导体衬底(例如砷化镓)一般在不同的平面中具有不同的电子/空穴迁移率。
实际上，已经证明很难在不同的平面上形成NFET和PFET而不降低器件密度和/或增加工艺复杂性。
例如，在美国专利4,933,298中，SOI衬底上的硅岛选择地被掩蔽并被再结晶以形成不同结晶取向的岛，这增加了工艺成本。在美国专利5,317,175中，牺牲密度来将n和p型器件相互垂直地分别设置在衬底的分离区中。在美国专利5,698,893以及日本公开专利申请JP126454A和JP3285351A中，在衬底的水平和垂直表面上形成各自的器件；沟槽形成增加了工艺复杂性和成本。
因此，本发明显著的优点是以添加最小的工艺复杂性和密度损失的方式，提供具有p型和n型晶体管的独立半导体管体，所述晶体管在不同的沟道平面中具有沟道。
发明内容
在第一个方案中，本发明包括一个MOS器件，该MOS器件包括：在衬底上形成的第一与第二独立半导体管体，所述第一独立半导体管体具有相对于所述第二独立半导体管体的第一部分呈非直角、非平行取向设置的第一部分，所述第一和第二独立半导体管体的所述部分具有各自的第一和第二结晶取向；第一栅电极，以相对于所述第一独立半导体管体的所述第一部分呈非直角的角度经过所述第一独立半导体管体的所述第一部分的至少一部分；第二栅电极，以相对于所述第二独立半导体管体的所述第一部分呈非直角的角度经过所述第二独立半导体管体的所述第一部分的至少一部分；以及受控电极，至少设置在分别通过所述第一栅电极和所述第二栅电极暴露的所述第一和第二独立半导体管体的各部分中。
在第二个方案中，本发明包括一个CMOS器件，该CMOS器件包括：第一独立半导体管体，具有设置在第一结晶平面上的n型沟道区，以及以相对于所述沟道区呈非直角角度经过所述沟道区的第一栅电极，所述第一结晶平面的电子迁移率大于所述第一独立半导体管体的第二结晶平面的电子迁移率；以及第二独立半导体管体，具有设置在第二结晶平面上的p型沟道区，以及以相对于所述沟道区呈非直角角度经过所述沟道区的第二栅电极，所述第二结晶平面的空穴迁移率大于所述第一独立半导体管体的所述第一结晶平面的空穴迁移率。
在第三个方案中，本发明包括一种形成MOS器件的方法，该方法包括：形成第一独立半导体管体，其具有设置在第一结晶平面上的n型沟道区，以相对于所述沟道区呈非直角角度经过所述沟道区的第一栅电极，以及源极和漏极区，所述第一结晶平面的电子迁移率大于所述第一独立半导体管体的第二结晶平面的电子迁移率；以及形成第二独立硅管体，其具有设置在第二结晶平面上的p型沟道区，以相对于所述沟道区呈非直角角度经过所述沟道区的第二栅电极，以及源极和漏极区，所述第二结晶平面的空穴迁移率大于所述第一独立半导体管体的所述第一结晶平面的空穴迁移率。
在第四方案中，本发明包括一种提供包括第一和第二FinFET的致密集成电路的方法，该第一和第二FinFET具有设置在第一和第二结晶平面上的沟道区，该方法包括：在给定轴上取向半导体晶片；形成相对于所述给定轴呈第一方位角的第一掩模形状组；形成相对于所述给定轴呈第二方位角的第二掩模形状组；通过蚀刻由所述第一和第二掩模形状组暴露的所述晶片的部分，在所述半导体晶片中形成FinFET管体；以及在所述FinFET管体上以有利于光刻控制的取向形成栅电极。
附图说明
通过参考下述附图，结合附随的说明，将更好地理解本发明，并且对于本领域的技术人员其许多目的和优点将变得显而易见，其中：
图1是SOI晶片在根据本发明第一实施例的工艺某一点的截面图；
图2是SOI晶片在根据本发明第一实施例的工艺中间步骤的顶视图；
图3A和3B分别是SOI晶片在根据本发明第一实施例的图2之后的工艺中间步骤的顶视图和截面图；
图4A和4B分别是SOI晶片在根据本发明第一实施例的图3A和3B之后的工艺中间步骤的顶视图和截面图；
图5是根据本发明第一实施例的具有集成电路的SOI晶片的顶视图；
图6是根据本发明第一实施例的倒相电路的布局；
图7示出了根据本发明第二实施例的物理布局和结构；以及
图8是本发明的独立FET器件的顶视图，示出了其电子沟道长度的控制。
具体实施方式
一般而言，本发明是用于提供具有第一取向的p型沟道和第二取向的n型沟道的晶体管的致密封装的方法和结构，所有其它设计特征彼此正交(即垂直)。{100}面的硅晶片以相对于垂直参考轴呈22.5度的{100}平面取向，该垂直参考轴沿着晶片上表面的平面放置，这产生了具有与垂直参考轴的相反方向呈22.5度的取向的{110}平面。独立硅管体根据其是否用于构建n型或p型FET沿着这些各自的平面形成。沿着与晶片的垂直参考轴正交(即相对于其呈90度取向)的方向构图栅电极层，栅极长度由覆盖独立硅管体的栅电极的宽度来限定。
本发明可以制造在体硅晶片或绝缘体上硅(SOI)晶片上。通常，虽然相对于体硅晶片，优选SOI，由于其如下所述制造独立硅管体的容易性，但是也可以使用体硅晶片。此外，虽然相对于硅管体来讨论本发明，但是能够使用其它半导体管体(诸如常规的单晶锗、硅和锗的化合物(例如诸如SiGe和SiGeC的应变硅材料)、诸如GaAs和InAs的III-V族材料、或II-VI族材料)。
在本发明中，形成独立硅轨，以提供用于双栅极FET(即，具有多维而不仅仅是如常规FET中的上下控制沟道区的栅电极的FET)的硅管体。实际上，可以使用形成具有或不具有双栅极构造的这种独立硅管体的任何工艺。即，虽然本发明的优选实施例使用FinFET，由于它们构建的相对容易性以及它们最终的双栅极构造，但是可以使用其它用于在独立半导体管体上形成FET(或其它有源或无源集成电路部件)的方法、结构和构造。
在下面的描述中，将涉及用于本发明器件的各种结构的具体厚度、尺寸以及其它参数，它们基于当前的半导体制造技术以及未来所预见的。应该理解，随着将来工艺集成的进步，能够利用不同/更先进的参数形成所述结构。不应该认为本发明的范围受限于下述参数。
根据本发明的优选实施例，通过下述工艺来形成FinFET硅管体。首先，提供具有给定结晶取向的SOI衬底10。SOI晶片在掩埋氧化层的顶部上具有近似10-120nm厚度的硅层。该硅层由4-50nm厚的(利用常规技术在硅层上热生长的)氧化硅层12和在该氧化硅层12上的6-75nm厚的未掺杂多晶硅层(或适合于下述工艺的其它材料)覆盖。然后，在多晶硅上形成光掩模，并利用常规技术蚀刻该多晶硅层，在氧化硅层12上停止。然后如图1所示，利用常规工艺在蚀刻的多晶硅(心轴)20N和20P的侧面上形成氮化硅侧壁隔离层30。该隔离层在它们的最宽处(即氧化硅12的正上方)近似4-50nm厚。值得注意的是，优选，多晶硅层的厚度近似于氮化硅隔离层的厚度的1.5倍；还值得注意的是，优选，氮化硅隔离层具有与氧化硅12相同的总厚度。然而值得注意的是，这样的相互关系不是必需的。
如图2所示，值得注意的是，从顶视图上看，心轴20在作为最终形成的器件的函数的不同角度上取向。心轴20N如此取向，以至于FET的最终沟道区将沿着SOI晶片10上的硅层的{100}平面，并用于形成n型FinFET。心轴20P如此取向，以至于FET的最终沟道区将沿着SOI晶片10上的硅层的{110}平面，并用于形成p型FinFET。因为在硅中，{100}和{110}平面相互呈45度取向，所以心轴20N和20P也相互呈45度取向。如前所述，不同的半导体具有在其处空穴和电子迁移率最大的不同平面。因此，实际上，对于其它半导体，心轴20N和20P可以相互以除45度之外的角度设置。它们将以分别与最大化空穴和电子迁移率的各自结晶取向对准的任何角度设置。同样，虽然仅示出两个FinFET管体，实际上，可以在衬底上以与管体20N和20P的其中之一相同的取向或与其垂直的取向形成其它管体。
作为优选实施例使用硅来制造，值得注意的是，SOI晶片10具有槽口10A。该槽口通常用于限定晶片在处理期间的水平和垂直参考轴。因此，例如，当将晶片插入光刻工具中时，该槽口用于限定晶片的垂直参考轴，并使用该轴作为参考点来印刷图像。通常在CMOS工艺中将槽口与晶片的{110}结晶取向对准。在本发明中，取而代之地，在布置离{100}平面22.5度的位置处制作槽口。
因此，鳍片通常取向为离由晶片上的槽口限定的四个基本方向+/-22.5度。这将根据它们分别离垂直参考轴是顺时针方向22.5度还是逆时针方向22.5度来产生具有位于{110}或{100}平面中的平面的硅“鳍片”。
返回到工艺描述，在除去多晶硅心轴20N、20P之后，使用氮化硅侧壁30作为掩模，蚀刻二氧化硅层12和下面的硅层以形成鳍片管体。值得注意的是，氮化物隔离层30和下面的氧化硅12的结合共同地提供硬掩模，该硬掩模为了硅层的全蚀刻将保持其尺寸的完整性。然后，除去氮化硅侧壁隔离层30，产生FinFET硅管体40N、40P，各自在其上表面上具有氧化硅层12的余量。最终的结构在图3A(顶视图)和图3B(截面图)中示出。值得注意的是，由于管体40N、40P通过形成在心轴上的侧壁隔离层来限定，所以它们为环形。在这个环节可以使用各种掩模/蚀刻顺序来蚀刻掉环的连接部分，以形成分离的FinFET管体。为了本发明的目的，这些环的存在或不存在不重要。
然后根据产品的应用对FinFET管体40N、40P掺杂。假设硅层最初为p掺杂，则FinFET管体40N将在该环节被掩蔽，并将n型掺杂剂施加到FinFET管体40P。如图4A和4B所示，在适合的管体掺杂后，在FinFET管体中形成适合的氧化硅栅极介质50(通常为1-2.5nm厚，由热氧化形成)。可以使用其它栅极介质(氧化硅和氮化硅层、或氧氮化硅、或最近提出的诸如氧化铪、氧化铝、氧化锆和金属硅酸盐的高k栅氧化物介质中的任何一种)。然后，将栅电极材料，通常为多晶硅，沉积至50-150nm的厚度，然后蚀刻以形成具有7-180nm的给定栅极长度(在该取向中，在图4A的垂直平面中栅极60的宽度)的栅极60。栅极长度是确定FET特别是FinFET的速度和适当功能的重要参数。该栅极沿着参考轴取向，因此，栅极长度的控制不受FinFET管体的离轴取向影响。而且，值得注意的是，与有利于光刻控制的参考轴对准来执行这个和所有随后的掩模和蚀刻步骤。
在图5中，将源极和漏极的延伸和晕圈离子注入FinFET 40N中，掩模层70仅在其中设计nFET的区域上打开。随后对于pFET执行相同的工序而没有示出。值得注意的是，按照相对于晶片的水平参考轴呈近似150度(注入71)、30度(注入72)、210度(注入74)和330度(注入73)的取向的注入顺序来执行各延伸和晕圈注入，以便于完全掺杂FinFET管体40N的两侧。对于n型器件，延伸注入为以1E15(即，1×10的15次幂的离子/平方厘米)数量级的剂量和近似0.5-15kEV的能量的砷，而晕圈注入为以4E13数量级的剂量和近似0.4-10kEV的能量的硼(B11)。对于p型器件，延伸注入为以1E15数量级的剂量和近似.05-15kEV的能量的BF2，而晕圈注入为以5E13至1E14数量级的剂量和近似1-40kEV的能量的磷。应该理解，所有这些值为近似值并取决于技术和产品。
然后，在源极和漏极区75的顺序注入之后，利用常规平坦化的后段制程(BEOL)钝化层(例如硼磷硅酸盐玻璃、氟硅酸盐玻璃、以及诸如商标为SiLK和Black Diamond的那些可购买到的低k介质)和导体80(掺杂硅、铝、难熔金属和难熔金属合金、铜和铜基合金)，来互连FinFET。这些结构可以为单或双镶嵌(其中通过限定在其中沉积金属并随后被平坦化的通孔或凹槽来形成互连栓和金属线)，或产生与FinFET管体密度一致的互连密度的任何其它BEOL集成方案。
利用上述工艺，可以形成具有如图6所示结构的倒相电路。值得注意的是，栅电极60连接于接触栅电极台垫(landing pad)100A的覆层金属栓100B。本发明的工艺和结构的特征在于：本发明最大化了n型和p型器件的载流子迁移率，同时在除心轴限定掩模之外的所有设计层面上提供正交形状。通过使用边缘限定光刻(在该实施例中，通过利用侧壁隔离层作为掩模的侧壁图像转移(SIT))来在非正交方向上保持鳍片的临界图像控制。值得注意的是，在本发明中，最大化了载流子迁移率，而没有引入额外的掩模步骤或其它工艺复杂性。同时，虽然由于引入非正交特征而一定程度地损失了密度，但是密度减小小于通过现有技术的方法所提供的密度减小，因为其仅应用于单个掩模(限定独立管体的掩模)层面，并通过n型和p型器件所增加的载流子迁移率和独立FET管体的使用的结合来补偿。
在图7中，示出了本发明的第二实施例。在该实施例中，详细布局与在先实施例的不同之处在于：除了在其中栅电极和FET管体交叉的临近附近之外，独立FET管体40N、40P在与晶片的基本参考轴正交的方向上。这种“急转弯”布局结构提供了折衷，它在由第一实施例提供的FET密度上增加了密度，但是对于限定多晶硅心轴的掩模步骤引入了工艺复杂性。例如，该形状可以通过在氮化硅心轴上执行两次彼此呈急转弯角度偏移的顺序掩模/蚀刻步骤来形成。
图8示出了在根据本发明制造的独立FET的有效沟道长度与常规限定的FinFET的有效沟道长度之间的关系。栅极-层面光刻通常限制最小图像，通过该最小图像来确定FET的栅极长度。由于本发明的FinFET硅90的鳍片呈67.5度经过栅极，取代了通常的90度，所以由栅极覆盖的沟道平面的最小物理长度将为常规FET的正割(22.5度)倍，或9％更大。源极和漏极区的扩散通常在栅极边缘近似10％(即，栅极总长度的，其覆盖例如源极区的近似10％)下方延伸；因此，为了在图8的FinFET中获得可比较值的LEFF，必须修改工艺以增加在栅极近似15％下方的源极和漏极扩散的距离。实际上，利用本领域公知的各种技术(例如，在常规参数的基础上延长注入时间或提高注入温度)，本发明的源极和漏极延伸可以进一步在栅电极93的边缘之下扩散。因此，确定本发明的FinFET的电子性能的电有效沟道长度LEFF可以保持与常规的FinFET的相等。
很明显，在不脱离如下述权利要求所限定的本发明的精神和范围下，这里可以做出各种改变和/或修改。例如，虽然已经参考最大化n型和p型器件的迁移率描述了本发明，但是，可以存在其期望最大化一种器件的载流子迁移率而不最大化另一种器件的载流子迁移率的产品应用(诸如SRAM单元)。而且，如前所述，本发明应用于诸如电容器或电阻器的其它器件的制造，其中独立管体限定了半导体载流子路径，而“栅极”构成了通路导体或互连导体(取决于将要制造的元件属性)。

Claims (43)

1.一种金属氧化物半导体器件，包括：
在衬底上形成的第一与第二独立半导体管体，所述第一独立半导体管体具有相对于所述第二独立半导体管体的第一部分呈非直角、非平行取向设置的第一部分，所述第一和第二独立半导体管体的所述部分具有各自的第一和第二结晶取向；
第一栅电极，以相对于所述第一独立半导体管体的所述第一部分呈非直角的角度经过所述第一独立半导体管体的所述第一部分的至少一部分；
第二栅电极，以相对于所述第二独立半导体管体的所述第一部分呈非直角的角度经过所述第二独立半导体管体的所述第一部分的至少一部分；以及
受控电极，至少设置在分别通过所述第一栅电极和所述第二栅电极暴露的所述第一和第二独立半导体管体的各部分中。
2.根据权利要求1的器件，其中所述第一和第二独立半导体管体由选自如下的材料构成：硅、锗、硅或锗的化合物、以及III-V族材料和II-IV族材料。
3.根据权利要求2的器件，其中所述第一独立半导体管体以相对于所述第二独立半导体管体呈近似45度的角度取向。
4.根据权利要求3的器件，其中所述第一栅电极以近似67.5度的角度经过所述第一独立半导体管体的所述第一部分。
5.根据权利要求4的器件，其中所述第一独立半导体管体的沟道区与所述第一半导体管体的{100}平面对准，而所述第二独立半导体管体的沟道区与所述第二半导体管体的{110}平面对准。
6.根据权利要求5的器件，其中电子在所述第一独立半导体管体的所述沟道区中为多数载流子，而空穴在所述第二独立半导体管体的所述沟道区中为多数载流子。
7.一种互补金属氧化物半导体器件，包括：
第一独立硅管体，具有设置在第一结晶平面上的n型沟道区，以相对于所述沟道区呈非直角的角度经过所述沟道区的第一栅电极，以及源极和漏极区；以及
第二独立硅管体，具有设置在第二结晶平面上的p型沟道区，以相对于所述沟道区呈非直角的角度经过所述沟道区的第二栅电极，以及源极和漏极区。
8.根据权利要求7的器件，其中所述第一结晶平面为{100}平面，而所述第二结晶平面为{110}平面。
9.根据权利要求8的器件，其中所述第一独立半导体管体的所述源极和漏极区为n型掺杂剂区，而所述第二独立半导体管体的所述源极和漏极区为p型。
10.根据权利要求8的器件，其中所述第一和第二独立硅管体的至少一个具有相对于所述第一和第二栅电极中对应的一个形成直角的至少一个所述源极和漏极区。
11.根据权利要求9的器件，其中所述第一和第二独立硅管体的每一个具有分别相对于所述第一和第二栅电极形成直角的源极和漏极区。
12.根据权利要求8的器件，其中所述第一和第二独立硅管体的至少一个具有急转弯形状。
13.根据权利要求8的器件，其中所述第一结晶平面提供大于硅的至少一个其它结晶平面的电子迁移率，并且其中所述第二结晶平面提供大于所述第一结晶平面的空穴迁移率。
14.一种互补金属氧化物半导体器件，包括：
第一独立半导体管体，具有设置在第一结晶平面上的n型沟道区，以相对于所述沟道区呈非直角角度经过所述沟道区的第一栅电极，以及源极和漏极区，所述第一结晶平面的电子迁移率大于所述第一独立半导体管体的第二结晶平面的电子迁移率；以及
第二独立半导体管体，具有设置在第二结晶平面上的p型沟道区，以相对于所述沟道区呈非直角角度经过所述沟道区的第二栅电极，以及源极和漏极区，所述第二结晶平面的空穴迁移率大于所述第一独立半导体管体的所述第一结晶平面的空穴迁移率。
15.根据权利要求14的器件，其中所述半导体包括硅，所述第一结晶平面为{100}平面，而所述第二结晶平面为{110}平面。
16.根据权利要求15的器件，其中所述第一独立半导体管体的所述源极和漏极区为n型掺杂剂区，而所述第二独立半导体管体的所述源极和漏极区为p型。
17.根据权利要求14的器件，其中所述第一和第二独立硅管体的至少一个具有相对于所述第一和第二栅电极中对应的一个形成直角的至少一个所述源极和漏极区。
18.根据权利要求17的器件，其中所述第一和第二独立硅管体的每一个具有分别相对于所述第一和第二栅电极形成直角的源极和漏极区。
19.根据权利要求14的器件，其中所述第一和第二独立硅管体的至少一个具有急转弯形状。
20.一种形成金属氧化物半导体器件的方法，包括：
在衬底上形成形成第一和第二独立半导体管体，所述第一独立半导体管体具有相对于所述第二独立半导体管体的第一部分呈非直角、非平行取向设置的第一部分，所述第一和第二独立半导体管体的所述部分具有各自的第一和第二结晶取向；
形成第一栅电极，其以相对于所述第一独立半导体管体的所述第一部分呈非直角的角度经过所述第一独立半导体管体的所述第一部分的至少一部分；
形成第二栅电极，其以相对于所述第二独立半导体管体的所述第一部分呈非直角的角度经过所述第二独立半导体管体的所述第一部分的至少一部分；以及
形成受控电极，其在通过所述第一栅电极和所述第二栅电极暴露的所述第一和第二独立半导体管体的部分中。
21.根据权利要求20的方法，其中所述第一和第二独立半导体管体由选自如下的材料构成：硅、锗、硅或锗的化合物、以及III-V族材料和II-IV族材料。
22.根据权利要求20的方法，其中所述第一独立半导体管体以相对于所述第二独立半导体管体呈近似45度的角度取向。
23.根据权利要求22的方法，其中所述第一栅电极以近似67.5度的角度经过所述第一独立半导体管体的所述第一部分。
24.根据权利要求23的方法，其中所述第一独立半导体管体的沟道区与所述第一半导体管体的{100}平面对准，而所述第二独立半导体管体的沟道区与所述第二半导体管体的{110}平面对准。
25.根据权利要求24的方法，其中电子在所述第一独立半导体管体的所述沟道区中为多数载流子，而空穴在所述第二独立半导体管体的所述沟道区中为多数载流子。
26.一种形成互补金属氧化物半导体器件的方法，包括：
形成第一独立半导体管体，其具有设置在第一结晶平面上的n型沟道区，以及以相对于所述沟道区呈非直角角度经过所述沟道区的第一栅电极，所述第一结晶平面的电子迁移率大于所述第一独立半导体管体的第二结晶平面的电子迁移率；以及
形成第二独立硅管体，其具有设置在第二结晶平面上的p型沟道区，以及以相对于所述沟道区呈非直角角度经过所述沟道区的第二栅电极，所述第二结晶平面的空穴迁移率大于所述第一独立半导体管体的所述第一结晶平面的空穴迁移率。
27.根据权利要求26的方法，其中所述第一结晶平面为{100}平面，而所述第二结晶平面为{110}平面。
28.根据权利要求27的方法，其中所述第一独立半导体管体的源极和漏极区为n型掺杂剂区，而所述第二独立半导体管体的源极和漏极区为p型。
29.根据权利要求26的方法，其中所述第一和第二独立硅管体的至少一个具有相对于所述第一和第二栅电极中对应的一个形成直角的至少一个源极和漏极区。
30.根据权利要求29的方法，其中所述第一和第二独立硅管体的每一个具有分别相对于所述第一和第二栅电极形成直角的源极和漏极区。
31.根据权利要求26的方法，其中所述第一和第二独立硅管体的至少一个具有急转弯形状。
32.一种提供包括第一和第二FinFET的致密集成电路的方法，该第一和第二FinFET具有设置在第一和第二结晶平面上的沟道区，该方法包括：
在给定轴上取向半导体晶片；
形成相对于所述给定轴呈第一方位角的第一掩模形状组；
形成相对于所述给定轴呈第二方位角的第二掩模形状组；
通过蚀刻由所述第一和第二掩模形状组暴露的所述晶片的部分，在所述半导体晶片中形成FinFET管体；以及
在所述FinFET管体上以有利于光刻控制的取向形成栅电极。
33.根据权利要求32的方法，其中所述半导体包括选自如下的材料：硅、锗、硅或锗的化合物、以及III-V族材料和II-IV族材料。
34.根据权利要求33的方法，其中所述半导体包括硅。
35.根据权利要求32的方法，其中所述第一方位角处于其中电子迁移率高于第二结晶平面的电子迁移率的所述半导体的第一结晶平面；而所述第二方位角处于其中空穴迁移率高于所述第一结晶平面的空穴迁移率的所述半导体的第二结晶平面。
36.根据权利要求35的方法，其中所述半导体晶片具有从{110}平面以大体45度取向的{100}结晶平面。
37.根据权利要求32的方法，其中所述第一方位角等于并相反于所述第二方位角。
38.根据权利要求37的方法，其中所述第一和第二鳍片的取向自所述半导体晶片轴分别为+22.5度和-22.5度。
39.一种器件，包括：
第一独立半导体管体，其具有布置在第一结晶平面上的第一导电区；
第二独立半导体管体，其具有布置在第二结晶平面上的第二导电区；以及
第一和第二导体，分别相对于所述第一和第二导电区呈非直角、非平行的角度覆盖所述第一和第二导电区。
40.根据权利要求39的器件，其中将掺杂剂区分别设置在所述第一和第二独立半导体管体的至少一个中，所述第一和第二导体中至少对应的一个具有覆盖所述掺杂剂区的其总长度的近似15％。
41.根据权利要求40的器件，其中所述掺杂剂区包括FET的源极扩散，而所述第一和第二导体中所述至少对应的一个包括FET的栅电极。
42.根据权利要求40的器件，其中所述掺杂剂区包括FET的漏极扩散，而所述第一和第二导体中所述至少对应的一个包括FET的栅电极。
43.根据权利要求39的器件，还包括第三独立半导体管体，其相对于所述第一和第二独立半导体管体中的一个呈正交取向设置。
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US6794718B2 (en) 2004-09-21
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