CN1643697A - 应变翅片式场效应晶体管的结构和方法 - Google Patents

应变翅片式场效应晶体管的结构和方法 Download PDF

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CN1643697A
CN1643697A CNA038062879A CN03806287A CN1643697A CN 1643697 A CN1643697 A CN 1643697A CN A038062879 A CNA038062879 A CN A038062879A CN 03806287 A CN03806287 A CN 03806287A CN 1643697 A CN1643697 A CN 1643697A
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CN100334741C (zh
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威廉·F·克拉克
戴维·M·佛莱德
路易斯·D·兰泽洛蒂
爱德华·J·诺瓦克
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Abstract

一种用于晶体管的结构,包括绝缘体(10)和在所述绝缘体上的硅结构。所述硅结构包括中心部分(155)和从所述中心部分延伸的第一(250)和第二端(250)。第一栅极(50)位于所述结构的所述中心部分(155)的第一侧上。应变产生层(11)可以在所述第一栅极(50)和所述结构的所述中心部分(155)之间,第二栅极(160)在所述结构的所述中心部分(155)的第二侧上。

Description

应变翅片式场效应晶体管的结构和方法
技术领域
本发明涉及半导体制造领域,尤其涉及一种用于形成双栅极场效应晶体管的方法。
背景技术
在半导体器件的生产中,保持成本和性能的竞争性需求已经引发了集成电路中器件密度的持续增加。为了有利于器件密度的增加,经常需要新技术来使这些半导体器件的特征尺寸减小。
在互补金属氧化物半导体(CMOS)技术中,比如在场效应晶体管(FET)的设计和制造中,器件密度持续增加的推动作用尤其强烈。FET用于几乎所有类型的集成电路设计(即,微处理器、存储器等)。遗憾的是,CMOS FET器件密度的增大经常导致性能和/或可靠性的降低。
已经提出而有利于提高器件密度的一种类型的FET是双栅极场效应晶体管。双栅极FET使用两个栅极,所述本体的每侧有一个,以利于缩小CMOS的尺寸,同时保持可接受的性能。尤其是,双栅极的使用增大了栅极面积,使得晶体管无需增大器件的栅极长度,就有更好的电流控制。因此,所述双栅极FET能够具有更大晶体管的电流控制,而无需要求更大晶体管的器件空间。
遗憾的是,在设计和制造双栅极CMOS晶体管时,出现了几个困难。首先,双栅极晶体管的相对尺寸难以可靠地制造具有可靠性能和最小特征尺寸的晶体管。其次,双栅极晶体管的阈值电压在很大程度上取决于所述两个栅极的材料。尤其是,目前的制造技术通常产生具有较高的阈值电压或过低的阈值电压的双栅极晶体管。例如,如果栅极掺杂了与源极相同的极性,则所述阈值电压通常接近零。相反,如果所述栅极掺杂了与电源相反的极性,则所述阈值电压将接近1伏。在多数CMOS应用中,这两种结果都不是所希望的。
因此,需要双栅极CMOS器件的改进的器件结构及制造方法,所述结构和方法提供了所生成的双栅极CMOS的改进的阈值电压,而没有过分地增加制造的复杂性。
发明内容
非对称应变翅片式场效应晶体管具有绝缘体和在绝缘体上的半导体结构。所述结构包括中心部分和从所述中心部分延伸的第一和第二端。第一栅极位于所述结构的中心部分的第一侧,应变产生层在所述第一栅极和所述结构的中心部分的所述第一侧之间,第二栅极在所述结构的中心部分的第二侧。所述绝缘体是埋置的氧化物层,所述结构的中心部分是硅。所述应变产生层具有足够浓度的锗,而在所述中心部分内产生应变,增强载流子迁移率,而没有产生足以降低晶体管整体性能的位错。第一和第二端是源极区域和漏极区域。锗的浓度在10%和40%之间。不同的栅极可以不同地掺杂,以调节VT。所述栅极也可以类似地掺杂。
对称的应变翅片式场效应晶体管具有绝缘体和在所述绝缘体上的半导体结构。所述结构是翅片本体,所述本体具有含硅和硅锗的中心部分以及包含硅的端部部分。第一栅极位于所述硅结构的中心部分的第一侧,所述第二栅极位于所述结构的中心部分的第二侧。所述第一栅极和所述第二栅极仍然可以类似地或不同地掺杂(如同非对称应变情况)。
形成晶体管的方法包括在绝缘体上形成硅层,蚀刻所述硅层的第一部分形成第一开口,在所述第一开口上淀积第一栅极,蚀刻所述硅层的第二部分形成与所述第一开口相对的第二开口。在蚀刻了所述第二部分之后,所述硅层具有在绝缘体上的硅结构,该结构具有中心部分和从所述中心部分端部延伸的翅片。本发明在所述硅结构的面向所述第二开口的部分上形成应变产生层,该层在第二开口中形成第二栅极,然后从所述硅结构的除了所述中心部分之外的所有部分上去除所述第一栅极和第二栅极。
形成非对称应变翅片式场效应晶体管的方法包括在绝缘体上形成硅层,蚀刻所述硅层的第一部分形成第一开口,在所述第一开口上淀积第一栅极,蚀刻所述硅层的第二部分形成与所述第一开口相对的第二开口。在蚀刻了所述第二部分之后,所述硅层具有在绝缘层上的硅结构,该结构具有中心部分和从所述中心部分端部延伸的翅片。本发明在所述硅结构的面向所述第二开口的部分上形成硅锗层,在所述第二开口上形成不同于或类似于第一栅极掺杂的第二栅极,然后从所述硅结构的除了所述中心部分之外的所有部分上去除所述第一栅极和第二栅极。
形成应变翅片式场效应晶体管的方法包括在绝缘体上形成硅结构,在所述硅结构的一侧或两侧上形成应力,所述硅结构具有中心部分和从所述中心部分端部延伸的翅片,在所述硅结构的侧面上淀积第一栅极和第二栅极,然后从所述硅结构的除了所述中心部分之外的所有部分上去除所述第一栅极和第二栅极。
在FET中沟道材料的物理应变可以改善载流子迁移率。在平面P型金属氧化物半导体场效应晶体管(MOSFET)器件中诱发的应变已经表明将空穴迁移率提高了30%以上。本发明为竖直布置在衬底上的薄半导体本体提供了这些优点,并且,本发明综合了更大的沟道控制和更高的载流子迁移率。
附图说明
参照附图,从下面本发明的优选实施例的详细描述中,将能更好地理解前述及其他目的、方面和优点。
图1-20,22,24,和25是使用本发明第一实施例的方法生产的FET结构的第一实施例的剖面图。
图21,23和26-28是使用本发明第一实施例的方法生产的FET结构的第一实施例的透视图。
图29-31是使用本发明第二实施例的方法生产的FET结构的第二实施例的剖面图。
图32示出了本发明第一实施例的步骤顺序的流程图。
图33示出了本发明第二实施例的步骤顺序的流程图。
具体实施方式
本发明涉及增强的翅片式FET器件,并在这些器件中形成应变。本发明使用“翅片”型FET的双栅极结构。在翅片式FET型结构中,双栅极在所述本体的任一侧形成,所述本体水平地置于所述栅极之间。本发明生产的翅片式FET具有通过硅锗层的操作而产生应变的沟道本体。加工过程开始于晶片,所述晶片是通过晶片键合形成的,包括在底部的硅整体晶片,较厚的底部氧化物层和在顶部的松弛的SiGe层。然后在所述SiGe上蚀刻出薄翅片,停止于BOX层。外延生长的硅薄层可以在所述翅片上生长。由于硅和硅锗晶格常数的差异,所述外延生长层将在应变条件下生长。本发明还可以包括在对称或非对称的栅极功函翅片式FET器件中。
尽管上面针对非对称应变翅片式FET描述了本发明,但它同样可以应用于对称应变翅片式FET。具体而言,如图29-31所示,根据本发明的第二实施例,生成应变的对称应变翅片式FET所必须的加工过程开始于具有在上面的SiGe层300和绝缘体10的SOI结构(如图29所示)。SiGe层300可选择地形成图案,如图30所示。然后,在SiGe层300上生长硅层315而产生应变结构。然后,在硅层315上生长热氧化物320。接着,淀积、平面化和图形化栅极导体(例如多晶硅)310,而形成在本体结构155周围的所述栅极。在一个实施例中,栅极导体310具有相同的掺杂浓度和材料构成。然而,在不同的实施例中,栅电极310可以例如通过离子注入制成不对称的,而生成具有应变的非对称栅极功函翅片式FET。具体而言,在非对称栅极布置中,栅极导体310可以具有不同的掺杂浓度或使用不同的掺杂剂。如上所述,进行加工直到完成图18-28所示的结构。
本发明的一个重要特征在于它在很多不同形式的翅片式FET中提供了应变。在图1-28所示的应变翅片式FET实施例之一使用了SOI配置方案,而形成具有对称或不对称的栅极导体的应变翅片式FET。作为选择,如关于图15的解释,如果省略了氧化物150,那么形成动态阈值的翅片式FET。相反,图29-31所示的实施例使用SiGe-OI(绝缘体上硅锗)代替了图1-28所示的SOI结构。以类似的方式,根据所述栅导体的掺杂,所述SiGe-OI结构可以制成非对称栅极或对称栅极结构。上述实施例仅是本发明的示例,本发明并不仅限于这些特定的实施例。相反,上述实施例仅是示例,本领域的普通技术人员应当理解,通过包括本发明的应变结构,很多不同类型的翅片式FET将能够实现很好的结果。
根据本发明的第一实施例的翅片式FET的形成如图1-28所示。如图1所示开始加工,其中绝缘体上硅(SOI)结构包括绝缘体10,比如具有覆盖硅层11的埋置氧化物层。占位层12(比如氮化物等)淀积在硅层11上。然后,这一结构使用公知的普通图形化工艺形成图案,如图2所示,去除占位层12的一部分20。随后的蚀刻步骤去除硅层11的不受占位层12保护的任何对应部分30,如图3所示。
在图4中,氧化工艺在硅层11上生长栅极氧化层40。接着,在所述结构上淀积多晶硅50,如图5所示。多晶硅50是掺杂型的(例如,N+掺杂的多晶硅等)。在图6中,所述结构使用例如化学机械抛光(CMP)工艺平面化,形成平面层60。图7示出了氧化工艺,其中掺杂的多晶硅50以比所述占位材料12更快的速度氧化。因此,多晶硅50上的氧化层70比占位层12上的氧化层71更厚。
氧化层70,71在受控的速度下蚀刻,如图8所示。一旦占位层12暴露,那么蚀刻过程就停止。这样从占位层12的上表面去除了所有氧化物,同时在多晶硅50上留下部分氧化物70。接着,如图9所示,使用选择蚀刻工艺将占位层12去除,使硅11的上部90露出。
在图10中,将硬掩膜100(比如TEOS等)保形地淀积在所述结构的上层。然后,如图11所示,使用定向的各向异性蚀刻将硬掩模100从所有水平表面110上去除,而在多晶硅50和氧化物70的竖直表面上仍保留硬掩模100。在图12中,硅11图形化而去除所述部分120。在图形化工艺之后,仅保留硬掩模100以下的部分。
图13示出了选择性SiGe130的生长。尽管在这一示例中使用了SiGe,但本发明并不仅限于这种材料组分。任何能够表现出与硅晶格失配的物质都可以产生应力,且可以用于本发明。具体而言,所述结构在含有Ge的复合物中加热,使SiGe130从硅11上生长。这样在已经形成的硅沟道11上产生应变。所生成的硅层由于SiGe和较小晶格常数的硅层之间的晶格失配而产生应变。在FET的沟道材料中的物理应变可以改善载流子迁移率。在平面化p型金属氧化物半导体场效应晶体管(MOSFET)器件诱发的应变已经表明将空穴迁移率提高了超过30%。这是因为应变将导带和价带分开,且提高了低迁移率椭球的能量,减少了空穴。
同时,过量的Ge将产生不匹配的位错,这将降低器件的性能。本发明人已经发现Ge成分的最佳范围是10%至40%。
在普通的平面器件中使用浅沟槽隔离(STI)技术诱发应变。然而,在翅片式FET中,没有与工艺STI类似的工艺,因为埋置绝缘体层10(BOX)提供了器件隔离。本发明通过使用硅锗(SiGe)和硅侧壁膜在翅片式FET沟道上产生应变而克服了这一问题。
在图14中,从多晶硅50的上表面141去除氧化物70。这也减小了硬掩模100的高度142,且在绝缘体10上形成台阶140。另一热氧化步骤在SiGe130的表面上形成氧化物150,如图15所示。作为选择,氧化物150的形成可以省略,而形成动态阈值的翅片式FET。在没有氧化物150的实施例中(动态阈值(DT)翅片式FET),应变翅片式FET DT COMS器件由依赖于栅极的本体形成。这一结构,包括硅11、栅极氧化物40,硬掩模100,氧化物150和SiGe130,在下文中称为“本体”,且为了简化描述和图解,在附图中标记为155。
接着,在图16中,可以与第一多晶硅150不同或类似地掺杂的第二多晶硅160淀积在整个结构上。所述结构再次平面化,形成平坦的上表面170,如图17所示。因为第一多晶硅50是N+掺杂的多晶硅,所以可取的是第二多晶硅160是P+多晶硅。然而,对于对称的栅极器件,第一和第二多晶硅可以是相同的。两种类型的多晶硅可以互相替换,或者替换为其他已知类型和未来研制的掺杂类型。要点是存在于本体155两侧的多晶硅区50,160对于非对称结构来说不同地掺杂。多晶硅50,160可以是Ge掺杂的或任何其他导体。利用硅沟道结构11相对两侧掺杂不同的多晶硅,产生非对称栅极翅片式FET。
不同的导电材料具有相应的固有电位,经常称之为费米能级,在外部施加的电压作用下,决定了所述导体对电荷(或空穴)的相对亲和力。在金属中,所述费米能级是材料固有的,而在半导体中,比如硅,通过引入能够提供过多空穴或电子的杂质、费米能级可以调整为价带和导带之间的值。在非对称双栅极翅片FET中,两个栅电极,用相反的极性掺杂,一个栅极掺杂N型,另一栅极掺杂P型。这样,两个栅电极50,160具有不同的费米能级,因此,一个栅电极(强栅极,nFET的n栅极)对反型载流子具有更大的亲和力,而另一电极(弱栅极,pFET的p栅极)对反型载流子具有更小的新和力。结果,在半导体本体中靠近“强”栅极的位置形成反型沟道。因此,两栅电极有助于反型电势,导致较低的阈值电压(例如,0和0.5伏特之间)。
在所示和所述的实施例中,所述结构是非对称的翅片式FET器件,硅11仅在一侧30上蚀刻,在剩余的硅11上方占位层12保留。本发明在翅片式结构露出的一半(在与栅极氧化物相对的一侧上)上生长选择性单晶SiGe130。然而,本发明还可用于对称的翅片式FET,如下所示。
随着本征硅层180的淀积和生长,继续进行加工,如图18所示。然后,在图19中,另一绝缘体硬掩模190(比如TEOS等)淀积在本征硅18上,且使用普通的图形化技术形成图形,而去除部分200,如图20所示。在图21的透视图示出了上述结构。多晶硅电极50,160和本征硅180使用硬掩模190图形化,如图22所示(和在图23的透视图中)。然后,硬掩模190从区域220去除,如图24所示。可取的是,栅极50,160的图形化去除了所有的栅极多晶硅,向下直到埋置氧化物层10,且使用针对氮化物或氧化物选择的方向性蚀刻完成。因此,所述图形化过程不去除本体155的由前面形成的硬掩模100保护的部分。所述图形化过程保留了多晶硅50和多晶硅160的一部分,所述部分限定了双栅极晶体管的两个栅极。进行缓冲的HF清理,随后是用于在所有露出的硅表面上生长氧化物的热再氧化过程。可取的是,这样形成氧化物薄膜(50埃)当栅极接触本体时形成良好的界面。
然后,本发明在晶体管中执行已知的普通源极、漏极和光晕注入。可取的是,这些注入沿本体155的露出部分(翅片250)的全部四个方向进行,以确保在所述本体两侧均匀地注入。尤其是,源极和漏极注入从本体155的翅片250的两侧进行。然后,利用不同的注入能量和角度,进行另一注入,而在本体155中形成光晕注入,改善短沟道效应。光晕注入在较高的能量下和以相对于翅片250来说更尖锐的角度进行的,以便确保光晕掺杂剂的位置比源极/漏极掺杂剂在栅电极50,160下方更远。
接着,本发明淀积厚度大于组合的栅电极50,160和硬掩模的高度的电介质240,覆盖整个栅电极50,160和露出的翅片250,如图25所示。然后,该电介质平面化,并局部下凹,直到硬掩模232和栅电极50,160的一部分,但没有任何源极/漏极翅片区露出,如图25所示。如图26所示,电介质240蚀刻,而仅覆盖栅极50,160的侧面,且侧壁间隔层242在电介质240上方的栅极边缘上形成。可取的是,这利用电介质材料的保形淀积实现,随后是方向性蚀刻。可取的是,侧壁间隔层242由氮化物形成。电介质240,侧壁间隔层242和硬掩模232用于掩蔽方向性蚀刻,从而去除氧化物40,150,除了邻接所述栅极的区域。硬掩模232,侧壁间隔层242和侧壁部分240组合,而有效地将栅极50,160与源极和漏极250的接触280隔离,如图27所示。可取的是,源极和漏极接触280包含图形化的导电材料。接着,如图28所示,本征硅层180使用普通公知的硅化工艺硅化,形成硅化物层230。
在图32中,示出了概括本发明的第一实施例的流程图。首先,在320中,本发明在绝缘体10上形成硅层11。然后,在321中,本发明形成第一开口30。在322中,本发明在硅层11上生长第一氧化物层40。接着,在323中,本发明在第一开口内淀积第一栅极50。在324中,本发明蚀刻硅层11,而形成具有中心部分和翅片的硅结构155。本发明在325中形成应变产生层130。接着,在326中,本发明在应变产生层130上生长第二氧化物层150。在327中,本发明在第二开口140内形成第二栅极160。然后,在328中,本发明从所述硅结构除了中心部分之外的所有部分中去除第一栅极和第二栅极,。在329中,本发明掺杂翅片250,而使翅片250包含源极和漏极区域。最后,在330处,本发明在源极和漏极区域上形成源极和漏极接触280。
在操作中,栅极50,160内的电压改变被栅极50,160覆盖的半导体硅11的区域的导电性。该操作在源极和漏极翅片250之间形成或断开电连接。所以,所述器件可以用作执行逻辑操作的电子开关。
如上所述,本发明的一个重要特征是保留作为本体155的永久部分的SiGe层。具体而言,这种特征在硅沟道11内形成应变。FET中沟道材料上的物理应变可以改善载流子迁移率。
虽然上面针对非对称的应变翅片式FET描述了本发明,但它同样适用于对称的应变翅片式FET。具体而言,如图29-31所示,根据本发明的第二实施例,产生应变的对称应变翅片式FET所需的加工过程起始于具有在绝缘体10上方的SiGe层300的SOI结构(这在图29中示出)。SiGe层选择性地形成图案,如图30所示。然后,在SiGe层300上生长硅层315,而产生应变结构。然后,在硅层315上生长热氧化物320。接着,淀积、平面化和图形化栅极导体(例如多晶硅)310,而形成在本体结构155周围的所述栅极。在一个实施例中,栅极导体310具有相同的掺杂浓度和材料构成。然而,在不同的实施例中,栅电极310可以例如通过离子注入制成不对称的,而生成具有应变的非对称栅极功函翅片式FET。具体而言,在非对称栅极布置中,栅极导体310可以具有不同的掺杂浓度或使用不同的掺杂剂。如上所述,进行加工直到完成图18-28所示的结构。
本发明的一个重要特征在于它在很多不同形式的翅片式FET中提供了应变。在图1-28所示的应变翅片式FET实施例之一使用了SOI配置方案,而形成具有对称或不对称的栅极导体的应变翅片式FET。作为选择,如关于图15的解释,如果省略了氧化物150,那么形成动态阈值的翅片式FET。相反,图29-31所示的实施例使用SiGe-OI(绝缘体上硅锗)代替了图1-28所示的SOI结构。以类似的方式,根据所述栅导体的掺杂,所述SiGe-OI结构可以制成非对称栅极或对称栅极结构。上述实施例仅是本发明的示例,本发明并不仅限于这些特定的实施例。相反,上述实施例仅是示例,本领域的普通技术人员应当理解,通过包括本发明的应变结构,很多不同类型的翅片式FET将能够实现很好的结果。
在图33中,示出了概括了本发明的第二实施例的流程图。首先,在331中,所示在绝缘体10上形成硅锗层300。然后,在332中,所述方法蚀刻硅锗层而形成具有中心部分和翅片250的硅结构。在333中,所述方法在硅结构300上生长氧化物层320。在334中,所述方法在所述硅结构的侧面淀积栅极。接着,在336中,所述方法从所述硅结构除了中心部分之外的所有部分上去除第一栅极和第二栅极。在337中,所述方法掺杂翅片250,而使翅片250是源极和漏极区域。最后,在338中,所述方法在源极和漏极区域上形成源极和漏极接触280。
如上所述,SiGe层在已经形成的硅沟道11中产生应变。在FET中沟道材料的物理应变可以改善载流子迁移率。在平面化P型金属氧化物半导体场效应晶体管(MOSFET)器件中诱发的应变已经表明将空穴迁移率提高了30%以上。本发明为竖直布置在衬底上的薄半导体本体提供了这些优点,并且,本发明综合了更大的沟道控制和更高的载流子迁移率。
虽然已经就优选实施例描述了本发明,但本领域的技术人员将认识到,本发明可以在所附权利要求的主旨和范围内作出改进。例如,虽然本发明已经参照形成垂直的半导体本体的具体方法给出,但其他的在衬底上生产分离的半导体本体的方法也可以使用(例如,在SOI衬底上的硅岛)。而且,虽然SiGe给出作为主要的材料来诱发沟道区域的所需应变,但可以使用其他材料。最后,本发明可适用于其他半导体(例如III-IV族半导体,比如镓砷化物)。
工业应用性
在FET中沟道材料的物理应变可以改善载流子迁移率。在平面P型金属氧化物半导体场效应晶体管(MOSFET)器件中诱发的应变已经表明将空穴迁移率提高了30%以上。本发明为竖直布置在衬底上的薄半导体本体提供了这些优点,并且,本发明综合了更大的沟道控制和更高的载流子迁移率。

Claims (9)

1.一种晶体管,包含:
绝缘体(10);
在所述绝缘体上的半导体结构,其中所述结构包括中心部分(155)和从所述中心部分延伸的第一(250)和第二端(250);
位于所述结构的所述中心部分(155)的第一侧上的第一栅极(50);
在所述第一栅极(50)和所述结构的所述中心部分(155)的所述第一侧之间的应变产生层(11);以及
在所述结构的所述中心部分(155)的第二侧上的第二栅极(160)。
2.如权利要求1所述的晶体管,其特征在于所述绝缘体(10)包含埋置的氧化物层。
3.如权利要求1所述的晶体管,其特征在于所述结构的所述中心部分(155)包含硅。
4.如权利要求1所述的晶体管,其特征在于所述中心部分(155)包含硅和硅锗。
5.如权利要求1所述的晶体管,其特征在于所述应变诱发层(11)具有足够浓度的锗,以使在所述中心部分(155)内产生应变,增强载流子迁移率,而没有产生足以降低晶体管的整体性能的位错。
6.如权利要求1所述的晶体管,其特征在于所述第一和第二端(250)分别包含源极和漏极区域。
7.如权利要求5所述的晶体管,其特征在于所述锗的浓度在10%和40%之间。
8.如权利要求1所述的晶体管,其特征在于所述第一栅极(50)和所述第二栅极(160)不同地掺杂。
9.如权利要求1所述的晶体管,其特征在于所述第一栅极(50)和所述第二栅极(160)类似地掺杂。
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CN102412130A (zh) * 2011-03-30 2012-04-11 上海华力微电子有限公司 利用栅多晶硅提高晶体管载流子迁移率的方法
CN102931061B (zh) * 2011-08-09 2015-01-28 中芯国际集成电路制造(上海)有限公司 一种制作鳍式场效应管的翅片结构的方法
CN102931061A (zh) * 2011-08-09 2013-02-13 中芯国际集成电路制造(上海)有限公司 一种制作鳍式场效应管的翅片结构方法
CN103187290B (zh) * 2011-12-31 2015-10-21 中芯国际集成电路制造(北京)有限公司 鳍片式场效应晶体管及其制造方法
CN103187290A (zh) * 2011-12-31 2013-07-03 中芯国际集成电路制造(北京)有限公司 鳍片式场效应晶体管及其制造方法
CN104798179A (zh) * 2012-12-20 2015-07-22 英特尔公司 缺陷转移和晶格失配外延膜
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CN103985748A (zh) * 2013-02-08 2014-08-13 中国科学院微电子研究所 半导体设置及其制造方法
CN103985748B (zh) * 2013-02-08 2016-12-28 中国科学院微电子研究所 半导体设置及其制造方法

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US6849884B2 (en) 2005-02-01
US6767793B2 (en) 2004-07-27
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US20030178681A1 (en) 2003-09-25
WO2003081640A3 (en) 2004-03-11

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