CN1577889A - 具有应力施加层的非平面器件及制造方法 - Google Patents

具有应力施加层的非平面器件及制造方法 Download PDF

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CN1577889A
CN1577889A CNA200410050129XA CN200410050129A CN1577889A CN 1577889 A CN1577889 A CN 1577889A CN A200410050129X A CNA200410050129X A CN A200410050129XA CN 200410050129 A CN200410050129 A CN 200410050129A CN 1577889 A CN1577889 A CN 1577889A
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semiconductor body
gate
dielectric
silicon
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罗伯特·S·周
斯科特·A·黑尔兰德
布雷恩·S·多伊
休曼·达塔
贝恩-叶海·吉恩
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Abstract

本发明公开了具有应力施加层的非平面器件及制造方法。包括半导体主体的半导体器件被形成在绝缘衬底上,所述半导体主体具有顶表面和横向相对的侧壁。在半导体主体的顶表面上、在半导体主体的横向相对侧壁上形成栅极电介质层。在半导体主体顶表面上的栅极电介质上、以及与半导体主体的横向相对侧壁上的栅极电介质邻接来形成栅电极。然后与半导体主体邻接形成薄膜,其中该薄膜在半导体主体中产生应力。

Description

具有应力施加层的非平面器件及制造方法
技术领域
本发明涉及半导体集成电路制造的领域,更具体地,本发明涉及具有应力施加层(stress incorporation layer)的非平面晶体管。
背景技术
为了提高器件性能,人们已经提出了绝缘体上硅(SOI)晶体管,用于制造新型的集成电路。图1图示了标准的完全耗尽的绝缘体上硅(SOI)晶体管100。SOI晶体管100包括具有绝缘层104的单晶硅衬底102,所述绝缘层104例如是形成在单晶硅衬底102上的埋入氧化物。单晶硅主体106被形成在绝缘层104上。栅极电介质层108被形成在单晶硅主体106上,并且栅电极110被形成在栅极电介质108上。源极112和漏极114区域沿栅电极110横向相对的两侧形成在硅主体106中。
完全耗尽的SOI已经作为一种晶体管结构被提出,该晶体管结构利用理想的亚阈值梯度,以获得最优化的导通电流/关断电流比。为了利用晶体管100实现理想的亚阈值梯度,硅主体106的厚度必须是晶体管的栅极长度(Lg)的约1/3大小,或者Tsi=Lg/3。但是,当栅极长度缩减,特别是当栅极长度接近30nm时,对于不断减小硅膜厚度(Tsi)的需要使得此方法越来越不切实际。对于30纳米的栅极长度,所要求的硅主体厚度被认为需要小于10纳米,对于20纳米的栅极长度,所要求的硅主体厚度需要到约6纳米。制造厚度小于10纳米的薄硅膜被认为是极其困难的。一方面,获得一个纳米数量级的晶片均匀性是非常困难的挑战。另一方面,如下的情况,即能够接触这些薄膜来形成加高的源/漏区域以降低结电阻,变成几乎是不可能的,因为在栅极刻蚀以及栅极刻蚀和隔片刻蚀之后的各种清洗的过程中,源/漏区域中的薄硅层被消耗,留下的硅106不足以使硅在上面生长。
已经提出了诸如图2A和2B中示出的双栅极(DG)器件,来解决硅厚度的问题。双栅极(DG)器件200包括形成在绝缘衬底204上的硅主体202。栅极电介质206被形成在硅主体202的两侧,并且邻接被形成在硅主体202两侧的栅极电介质206来形成栅电极208。足够厚的诸如氮化硅的绝缘层209将栅电极208与硅主体202的顶部电隔离。
双栅极(DG)器件200实质上具有两个栅极,一个栅极位于器件沟道两侧中的一侧。因为双栅极器件200在沟道的每一侧都具有栅极,所以硅主体的厚度(Tsi)可以是单栅极器件的硅主体厚度的两倍,并仍然实现完全耗尽的晶体管的作用。也就是说,利用双栅极器件200,在Tsi=(2×Lg)/3的情况下可以形成完全耗尽的晶体管。但是,双栅极(DG)器件200最可能制造的形式,要求利用比用于图案化器件的栅极长度的光刻术小0.7倍的光刻术,来对主体202进行图案化。为了获得高密度的集成电路,通常理想的是对于栅电极208的栅极长度(Lg)进行最具侵蚀性的光刻术。虽然,双栅极结构使硅膜的厚度变为两倍(因为现在在沟道的两侧都存在栅极),但是这些结构极难制造。例如,硅主体202要求可以制造具有约5∶1的高宽比(高度比宽度)的硅主体202的硅主体刻蚀。
发明内容
为了解决上述问题,提出了本发明。根据本发明的一个方面,提供了一种半导体器件,其包括:形成在衬底之上的半导体主体,所述半导体主体具有顶表面与横向相对的侧壁;栅极电介质,所述栅极电介质在所述半导体主体的所述顶表面上、以及在所述半导体主体的所述横向相对的侧壁上形成;栅电极,所述栅电极在所述半导体主体的所述顶表面上的所述栅极电介质上、以及与所述半导体主体的所述横向相对的侧壁上的所述栅极电介质邻接形成;和膜,所述膜与所述半导体主体邻接形成,其中所述膜在所述半导体主体中产生应力。
根据本发明的另一个方面,提供了一种三栅极晶体管,其包括:在绝缘衬底上形成的单晶硅主体,所述硅主体具有与底表面相对的顶表面、以及第一和第二横向相对的侧壁;栅极电介质,所述栅极电介质在所述半导体主体的所述顶表面上、以及在所述半导体主体的所述第一和第二横向相对的侧壁上形成;栅电极,所述栅电极在所述硅主体的所述顶表面上的所述栅极电介质上、以及与所述硅主体的所述第一和第二横向相对的侧壁上的所述栅极电介质邻接形成;一对源/漏区,所述一对源/漏区形成在所述栅电极的相对两侧的所述半导体主体中;和围绕着所述硅主体和所述栅电极形成的应力产生膜,所述膜在所述器件的沟道区域中产生应力。
根据本发明的另一个方面,提供了一种形成半导体器件的方法,其包括:在绝缘衬底上形成具有顶表面和横向相对侧壁的半导体主体;在所述半导体主体的所述顶表面上、以及在所述半导体主体的所述横向相对的侧壁上形成栅极电介质;在所述半导体主体的所述顶表面上的所述栅极电介质上、以及与所述半导体主体的所述横向相对的侧壁上的所述栅极电介质邻接形成栅电极;以及与所述半导体主体邻接形成薄膜,其中所述薄膜在所述半导体主体中产生应力。
根据本发明的另一个方面,提供了一种形成非平面晶体管的方法,其包括:将在绝缘衬底上形成的单晶硅膜图案化成硅主体,所述硅主体具有与形成在所述绝缘膜上的底表面相对的顶表面、以及第一和第二横向相对的侧壁;在所述硅主体的所述顶表面上、以及在所述硅主体的所述侧壁上形成栅极电介质层;在所述硅主体之上以及所述绝缘衬底之上沉积栅极材料;图案化所述栅极材料,以在所述硅主体的所述顶表面上的所述栅极电介质层上、以及与所述硅主体的所述侧壁上的所述栅极电介质邻接形成栅电极,所述栅电极具有横向相对侧壁,所述栅电极的所述横向相对侧壁垂直于所述硅主体的所述横向相对侧壁延伸;在所述栅电极的所述横向相对侧壁的相对两侧上的所述半导体主体中形成一对源/漏区,其中在所述硅主体中所述源/漏区之间的区域形成沟道区域;从所述硅主体沟道区域的一部分之下以及所述硅主体的所述源区和漏区的一部分之下,去除所述绝缘衬底的一部分;以及在所述栅电极下方所述硅主体的所述暴露部分之下,以及所述栅电极下方所述源区和漏区的所述暴露部分之下,形成其中具有应力的膜。
附图说明
图1是耗尽的衬底晶体管的横截面视图的示图。
图2A和图2B图示了双栅极耗尽的衬底晶体管。
图3A和图3B是根据本发明具有应力施加膜的三栅极晶体管的图示。
图4是根据本发明实施例的三栅极晶体管的图示。
图5A-5E图示了根据本发明实施例制造具有应力施加膜的三栅极晶体管的方法。
图6是图示了可以被用来获得部分耗尽的和完全耗尽的三栅极晶体管的主体高度和主体宽度的曲线,所述三栅极晶体管具有30纳米和20纳米的栅极长度(Lg)。
具体实施方式
本发明是一种具有应力施加层的新型三栅极或非平面晶体管结构及其制造方法。在下面的描述中给出了很多具体细节,以便于充分理解本发明。在另外一些例子里,没有对公知的半导体工艺和制造技术进行详细的描述,以避免不必要地模糊本发明。
本发明是一种新型的非平面或三栅极晶体管结构及其制造方法。这种三栅极晶体管包括应力膜,所述应力膜围绕器件的沟道区域形成,来对沟道区域提供应力以提高载流子的迁移率。更大的载流子迁移率使得晶体管的驱动电流增大。在本发明的一个实施例中,在沟道区域之下形成应力膜,以使得其完全包围沟道。通过用应力膜完全包围沟道区域,应力膜对沟道的所有侧面提供应力,由此在大面积上提供应力,而最大化并提高器件性能。诸如应力类型(例如压应力或拉应力)和应力大小之类的膜应力特性可以变化,以优化不同晶体管类型(例如PMOS和NMOS)的性能。
在本发明的一个实施例中,三栅极晶体管是绝缘体上半导体(SOI)晶体管。三栅极晶体管理想地用于完全耗尽衬底晶体管应用中。三栅极晶体管包括在衬底上形成的薄半导体主体,该衬底可以是绝缘衬底或半导体衬底。栅极电介质被形成在半导体主体的顶表面和多个侧壁上。在半导体主体顶表面上的栅极电介质上、与在半导体主体侧壁上形成的栅极电介质邻接形成栅电极。在栅电极相对两侧的半导体主体中形成源区和漏区。因为栅电极和栅极电介质在三侧围绕半导体主体,所以晶体管实际上具有三个单独的沟道和栅极。晶体管的栅极“宽度”等于半导体主体这三侧中每一个之和。可以通过将几个三栅极晶体管连接到一起来形成更大“宽度”的晶体管。
因为在半导体主体中形成有三个单独的沟道,所以当晶体管被“导通”时,半导体主体可以被完全耗尽,由此可以形成栅极长度小于30纳米的完全耗尽的晶体管,而不需要使用超薄的半导体主体或者要求将半导体主体光刻图案化至小于器件的栅极长度(Lg)的尺寸。也就是说,本发明的三栅极晶体管的结构使得能够制造完全耗尽的晶体管,其中半导体主体的厚度和半导体主体的宽度等于器件的栅极长度。因为本发明的新型三栅极晶体管可以以完全耗尽的方式工作,所以该器件的特征在于理想的(即非常陡峭的)亚阈值斜率(理想的是在25℃下为60mV/decade),以及小于100mV/V(理想的是约60mV/V)的减小的漏极导致势垒下降(DIBL)短沟道效应,这导致当器件被“关断”时更低的漏电流,从而得到更低的功耗。
在图3A和3B中示出根据本发明实施例的具有应力施加膜的三栅极晶体管300的示例。(图3B是图3A穿过一个半导体主体308的栅电极324所取的横截面图。)在衬底302上形成三栅极晶体管300。在本发明的一个实施例中,衬底302是包括下部的单晶硅衬底304的绝缘衬底,诸如二氧化硅膜的绝缘层306被形成在所述单晶硅衬底304上。然而,三栅极晶体管300可以被形成在任何公知的绝缘衬底上,所述绝缘衬底例如是由二氧化硅、氮化物、氧化物和蓝宝石形成的衬底。在本发明的一个实施例中,衬底302可以是半导体衬底,例如但不限于单晶硅衬底和砷化镓衬底。
三栅极晶体管300包括半导体主体308,并通常包括在绝缘衬底302的绝缘体306上形成的多个半导体主体308。半导体主体308可以由任何公知的半导体材料形成,在所述半导体材料中可以通过施加应力来提高载流子的迁移率,所述半导体材料例如但不限于是硅(Si)和Ge含量少于约25%的锗化硅(SixGey)。三族—五族(III-V)半导体,例如砷化镓(GaAs)、InSb、GaP和GaSb也可通过向其施加应力而得到改善。人们认为直接带隙材料不会通过向其施加应力而得到改善,而非直接带隙的将得到改善。半导体主体308由这样的材料形成,即其可通过施加外部电控制而可逆地从绝缘状态变到导电状态。当希望晶体管300具有最佳的电性能时,半导体主体308理想地是单晶膜。例如,当晶体管300被用于高性能应用中,例如被用于诸如微处理器的高密度电路中时,半导体主体308是单晶膜。然而,当晶体管300被用于对性能的要求不那么苛刻的应用,例如用于液晶显示器中时,半导体主体308可以是多晶膜。绝缘体306使半导体主体308与单晶硅衬底302绝缘。在本发明的一个实施例中,半导体主体308是单晶硅膜。(多个)半导体主体308中的每个都具有一对横向相对的侧壁310和312,所述一对侧壁310和312被定义出半导体主体宽度314的距离所隔开。此外,每个半导体主体308具有顶表面316,所述顶表面316与形成在衬底302上的底表面318相对。顶表面316和底表面318之间的距离定义出主体高度320。在本发明的一个实施例中,主体高度320基本上等于主体宽度314。在本发明的一个实施例中,主体308具有小于30纳米并且理想的是小于20纳米的宽度314和高度320。在本发明的一个实施例中,主体高度320在主体宽度314的1/2到主体宽度314的两倍之间。
三栅极晶体管300具有栅极电介质层322。如图3A和3B所示,在各半导体主体308的三个侧面上并围绕这三个侧面来形成栅极电介质层322。如图3所示,在主体308的侧壁312上或者邻接侧壁312、顶表面316上、侧壁310上或者邻接侧壁310形成栅极电介质层322。栅极电介质层322可以是任何公知的栅极电介质层。在本发明的一个实施例中,栅极电介质层是二氧化硅(SiO2)、氧氮化硅(SiOxNy)或者氮化硅(Si3N4)电介质层。在本发明的一个实施例中,栅极电介质层322是厚度被形成至5到20埃之间的氧氮化硅膜。在本发明的一个实施例中,栅极电介质层322是诸如金属氧化物电介质的高K栅极电介质层,所述金属氧化物电介质例如但不限于是五氧化二钽(Ta2O5)、氧化钛(TiO2)、氧化铪(HfO2)、HfSiOxNy、氧化锆(ZrO2)和氧化镧(LaO2)。栅极电介质层322可以是其他类型的高K电介质,例如但不限于是PZT。
三栅极晶体管300具有栅电极324。如图3A和3B所示,在栅极电介质层322上并围绕其形成栅电极324。这样来形成栅电极324,即在半导体主体308的侧壁312上形成的栅极电介质322上或者邻接所述栅极电介质322、在半导体主体308的顶表面316上形成的栅极电介质322上、在半导体主体308的侧壁310上形成的栅极电介质层322上或者邻接所述栅极电介质层322来形成。栅电极324具有一对横向相对的侧壁326和328,所述一对侧壁326和328被定义出晶体管300的栅极长度(Lg)330的距离所隔开。在本发明的一个实施例中,栅电极324的横向相对的侧壁326和328在与半导体主体308的横向相对的侧壁310和312垂直的方向上延伸。
栅电极324可以由任何合适的栅电极材料形成。在本发明的一个实施例中,栅电极324由被掺杂至浓度为1×1019原子/cm3至1×1021原子/cm3之间的多晶硅组成。在本发明的一个实施例中,栅电极可以是金属栅电极,例如但不限于是钨、钽、钛以及它们的氮化物或者各种金属系统的合金。在本发明的一个实施例中,栅电极由具有3.9-5.3eV之间的功函数的材料所形成。应该理解,栅电极324不必是单一的材料,而可以是若干薄膜的复合堆叠,例如但不限于多晶硅/金属电极或者金属/多晶硅电极。
三栅极晶体管300具有源区330和漏区332。如图3A所示,源区330和漏区332被形成在栅电极324相对两侧的半导体主体308中。源区330和漏区332形成诸如N型或者P型导电性的同一导电类型。在本发明的一个实施例中,源区330和漏区332具有1×1019原子/cm3至1×1021原子/cm3之间的掺杂浓度。源区330和漏区332可以形成均一的浓度或者可以包括不同浓度或者掺杂分布(doping profile)的子区域,诸如尖端(tip)区域(例如,源/漏延伸区)。在本发明的一个实施例中,当晶体管300是对称的晶体管时,源区330和漏区332将具有相同的掺杂浓度和分布。在本发明的一个实施例中,当三栅极晶体管300被形成为非对称晶体管时,则源区330和漏区332的掺杂浓度和特征可以不同,以便获得特定的电特性。
半导体主体308位于源区330和漏区332之间的部分,限定出晶体管300的沟道区域350。沟道区域350还可以被限定为半导体主体308中由栅电极324所围绕的区域。但是,有时源/漏区可以通过例如扩散稍微地延伸到栅电极的下方,以限定出稍微小于栅电极长度(Lg)的沟道区域。在本发明的一个实施例中,沟道区域350是本征或者未掺杂的单晶硅。在本发明的一个实施例中,沟道区域350是掺杂的单晶硅。当沟道区域350被掺杂时,其通常被掺杂到1×1016原子/cm3至1×1019原子/cm3之间的导电水平。在本发明的一个实施例中,当沟道区域被掺杂时,其通常被掺杂成与源区330和漏区332相反的导电类型。例如,当源漏区是N型导电性时,沟道区域将被掺杂至P型导电性。类似地,当源漏区是P型导电性时,沟道区域将是N型导电性。这样,三栅极晶体管300可以分别被形成为NMOS晶体管或者PMOS晶体管。沟道区域350可以是被均匀掺杂的,或者可以是被非均匀掺杂的或者以不同的浓度进行掺杂,以提供特定的电特性和性能特性。例如,如果需要的话,沟道区域350可以包括公知的“晕圈(halo)”区域。
如图3A和3B所示,通过提供围绕半导体主体三个侧面的栅电极和栅极电介质,三栅极晶体管的特征在于具有三个沟道和三个栅极:在半导体主体308的侧面312上在源区和漏区之间延伸的第一个(g1);在半导体主体308的顶表面316上在源区和漏区之间延伸的第二个(g2);在半导体主体308的侧壁310上在源区和漏区之间延伸的第三个(g3)。晶体管300的栅极“宽度”(Gw)是三个沟道区域的宽度的总和。也就是说,晶体管300的栅极宽度等于硅主体308在侧壁310处的高度320,加上硅主体308在顶表面316处的宽度,加上硅主体308在侧壁312处的高度320。通过使用耦合到一起的多个器件(例如如图3A所示,由单个栅电极324所围绕的多个硅主体308),可以得到更大“宽度”的晶体管。
如上所述,晶体管300的栅极“宽度”等于由晶体管300的半导体主体308所生成的三个栅极宽度的总和。为了制造具有更大栅极宽度的晶体管,晶体管300可以包括如图3A中所示的附加的或者多个半导体主体或者指状物308。如图3A和3B所示,每一个半导体主体308具有形成在其顶表面和侧壁上的栅极电介质层322。在每一半导体主体308上的各个栅极电介质322上或者邻接所述各个栅极电介质322形成栅电极324。如图3A所示,每一个半导体主体308还包括源区330和漏区332,所述源区330和漏区332被形成在栅电极324的相对两侧的半导体主体308中。在本发明的一个实施例中,每一个半导体主体308形成有与其他的半导体主体308相同的宽度和高度(厚度)。在本发明的一个实施例中,如图3A所示,半导体主体308的每一个源区330和漏区332通过用来形成半导体主体308的半导体材料而被电耦合在一起,以形成源极焊盘(landingpad)460和漏极焊盘480。或者,可以通过用来将各种晶体管300电互连到一起成为功能电路的更高层面的金属化(例如,金属1、金属2、金属3...),将源区330和漏区332耦合在一起。如图3A所示的晶体管300的栅极宽度等于由每一个半导体主体308所产生的栅极宽度的总和。这样,可以形成具有任意所需栅极宽度的三栅极晶体管300。
此外,如图3A和3B所示,本发明的三栅极器件包括向器件的沟道区域350施加应力的膜360。通过向沟道区域施加合适的应力,器件载流子(即电子或空穴)的迁移率可以被增大并提高器件性能。在本发明的一个实施例中,如图3A和3B所示,在半导体主体308的暴露部分上并围绕该暴露部分形成应力施加膜360。此外,在本发明的一个实施例中,在栅电极324之上并围绕该栅电极324来形成应力施加膜360。在本发明的一个实施例中,直接在半导体主体308的暴露部分322上,以及直接在半导体主体308的侧面310和312上或与其邻接来形成应力施加膜360。此外,在本发明的一个实施例中,还直接在栅电极324上并邻接该栅电极324来形成应力施加膜360。
此外,在本发明的一个实施例中,如图3A和3B所示,应力施加膜360还被直接形成在半导体主体308的底表面318之下,包括形成在半导体主体308的沟道区域350之下。可以通过首先去除半导体主体之下埋入氧化物或绝缘体306的一部分,并随后用应力施加膜回填该区域,来在半导体主体之下形成应力施加膜。通过直接将应力施加膜纳入在半导体主体308沟道区域350的底表面之下,应力材料360就完全包围了沟道,并从沟道的所有侧面而不仅仅是顶部来提供应力。
在本发明的一个实施例中,膜360具有压应力,使得半导体主体尤其是半导体主体的沟道区域受拉应力。受拉应力的沟道区域提高了电子的迁移率,因此对用于载流子为电子的NMOS器件中是理想的。在本发明的一个实施例中,应力施加膜360是这样的膜,即其具有合适的压应力,以在半导体主体的沟道区域中产生0.5-5.0GPa之间并理想的是约1GPa的拉应力。在本发明的一个实施例中,应力施加膜360具有10-200纳米之间的厚度。在本发明的一个实施例中,应力膜360将载流子的迁移率提高20-80%。
在本发明的一个实施例中,膜360具有拉应力,使得半导体主体308尤其是半导体主体的沟道区域350受压应力。受压应力的沟道区域提高了空穴的迁移率,因此对用于载流子为空穴的PMOS器件中是理想的。在本发明的一个实施例中,应力施加膜360是这样的膜,即其具有合适的拉应力,以在半导体主体308的沟道区域中产生0.5-5.0GPa之间的压应力。在本发明的一个实施例中,薄膜360是具有拉应力的氮化硅膜。
在本发明的一个实施例中,在半导体主体的底侧318上形成薄氧化物或钝化膜319,以帮助减小寄生漏电效应。在本发明的一个实施例中,钝化膜319包括SiO2并可形成为大于约1纳米的厚度。
因为沟道区域350在三个侧面上被栅电极324和栅极电介质322所围绕,所以晶体管300可以以完全耗尽的方式工作,其中,当晶体管300被“导通”时,沟道区域350完全耗尽,由此提供完全耗尽的晶体管的有利电特性和性能。就是说,当晶体管300被“导通”时,在沟道区域350中形成耗尽区域,并同时在区域350的表面处形成反型层(即在半导体主体的侧表面和顶表面上形成反型层)。反型层具有与源漏区相同的导电类型,并且在源区和漏区之间形成导电沟道,以允许电流在其间流动。耗尽区域耗尽来自反型层下方的自由载流子。耗尽区域延伸到沟道区域350的底部,因此晶体管可以被称为是“完全耗尽的”晶体管。相对于非完全耗尽的或者部分耗尽的晶体管,完全耗尽的晶体管的电性能特性提高了。例如,使晶体管300在完全耗尽的方式下工作,为晶体管300提供了理想的或者非常陡峭的亚阈值斜率。即使当被制造成具有小于30nm的半导体主体厚度时,该三栅极晶体管也可以被制成具有小于80mV/decade并且理想的是约60mV/decade的非常陡峭的亚阈值斜率。此外,当使晶体管300在完全耗尽的方式下工作时,晶体管300具有改善的漏极导致势垒下降(DIBL)效应,这提供了更好的“关断”状态漏流,实现了更低的漏流并由此降低了功耗。在本发明的一个实施例中,三栅极晶体管300具有小于100mV/V且理想的是小于40mV/V的DIBL效应。
图6是两条曲线602和604的示图,所述两条图线602和604给出了将产生完全耗尽的(F.D)或者部分耗尽的(P.D)三栅极晶体管的主体高度和主体宽度,其中所述三栅极体管分别具有30nm(602)和20nm(604)的栅极长度(Lg)。在本发明的一个实施例中,主体高度、主体宽度和栅极长度被选择为具有将形成完全耗尽的晶体管的尺寸。在其他的实施例中,三栅极晶体管具有将形成部分耗尽的晶体管的主体高度、主体宽度和栅极长度。
本发明的三栅极晶体管可以被认为是非平面晶体管,因为沟道区域350的反型层被形成在半导体主体308中的水平方向上以及垂直方向上。本发明的半导体器件也可以被认为是非平面器件,因为来自栅电极324的电场被从水平侧(g2)以及垂直侧(g1和g3)上施加。
在本发明的一个实施例中,如图4所示,三栅极晶体管300可以包括其他膜或特征,例如在形成应力施加膜360之前形成的硅化物430、硅或其他半导体膜410和侧壁隔片420。例如在本发明的一个实施例中,在半导体主体308的源区330和漏区332上形成半导体膜410,以形成“加高”的源漏区。半导体膜410可以是硅膜或者例如锗化硅(SixGey)的硅合金。在本发明的一个实施例中,半导体膜410是被形成为与源区330和漏区332相同导电类型的单晶硅膜。在本发明的一个实施例中,半导体膜可以是硅合金,例如其中硅构成合金的大约1到99原子百分数的锗化硅。半导体膜410不必是单晶半导体膜,在一个实施例中可以是多晶膜。可以通过一对电介质侧壁隔片420,例如氮化硅或氧化硅或其复合物,来将半导体膜410与栅电极324电隔离。如图4所示,侧壁隔片420沿着栅电极324的横向相对侧壁326和328延伸,由此将半导体膜410与栅电极324隔离。在本发明的一个实施例中,侧壁隔片420具有20-200埃之间的厚度。通过向半导体主体的源区330和漏区332增加硅或半导体膜,并形成“加高”的源漏区,源漏区的厚度增加,由此降低了到晶体管300的源/漏接触电阻,而改善了其电特性和性能。
在本发明的一个实施例中,在源区330和漏区332上形成硅化物膜430,例如但不限于是硅化钛、硅化镍和硅化钴。在本发明的一个实施例中,如图4所示,在硅主体308的硅膜410上形成硅化物膜430。但是也可直接在硅主体308的顶表面316上形成硅化物膜430。例如,可以通过首先在硅主体上形成诸如未掺杂硅膜的硅膜,然后在硅化工艺过程中完全消耗该硅膜,来在硅主体308上形成硅化物膜430。电介质隔片420使得硅化物膜430能够以自对准工艺(即salicide工艺)形成在半导体主体308或硅膜410上。
此外,在本发明的一个实施例中,也可以在栅电极324顶部形成半导体或硅膜440,也可以在栅电极324的顶表面上形成硅化物膜450。硅化物膜450和硅膜440通常与硅主体308上的硅化物膜430和硅膜410同时形成。在栅电极上的硅化物膜450上形成硅膜440,降低了到栅极的接触电阻,由此提高了晶体管300的电性能。
在图5A-5E中图示了根据本发明实施例的制造三栅极晶体管的方法。三栅极晶体管的制造开始于衬底502。如图5A所示,在衬底502上形成硅或者半导体膜508。在本发明的一个实施例中,衬底502是绝缘衬底,例如图5A中所示的。在本发明的一个实施例中,绝缘衬底502包括下部的单晶硅衬底504和顶部的诸如二氧化硅膜或者氮化硅膜之类的绝缘层506。绝缘层506将半导体膜508与衬底504隔离,并且在实施例中被形成至200埃至2000埃之间的厚度。绝缘层506有时被称为“埋入氧化物,,层。当硅或者半导体膜508被形成在绝缘衬底502上时,就制造出了绝缘体上硅或者半导体(SOI)衬底500。在本发明的其他实施例中,衬底502可以是半导体衬底,例如但不限于单晶硅衬底和砷化镓衬底。
虽然半导体膜508理想的是硅膜,但是在其他实施例中它可以是其他类型的半导体膜,在所述半导体膜中当受应力作用时可以提高载流子的迁移率,所述半导体膜例如但不限于是Ge含量少于25%的锗化硅(SixGey),以及III-V材料,例如砷化镓(GaAs)、InSb、GaP、GaSb。在本发明的一个实施例中,半导体膜508是本征的(即未掺杂的)硅膜。在其他实施例中,半导体膜508被掺杂成具有1×1016原子/cm3至1×1019原子/cm3之间的浓度水平的p型或者n型导电性。半导体膜508可以被原位掺杂(即当被沉积时进行掺杂)或者在其被形成在衬底502上之后通过例如离子注入来进行掺杂。在形成之后进行掺杂可以允许在相同绝缘衬底上容易地制造出PMOS以及NMOS三栅极器件。此时的半导体主体掺杂水平就决定了器件的沟道区域的掺杂水平。
半导体膜508被形成至这样的厚度,即所述厚度近似地等于所制造三栅极晶体管的后续形成的(多个)半导体主体所期望的高度。在本发明的一个实施例中,半导体膜508具有小于30纳米且理想的是小于20纳米的厚度或者高度509。在本发明的一个实施例中,半导体膜508被形成至这样的厚度,即所述厚度近似地等于所制造三栅极晶体管的所期望的栅极“长度”。在本发明的一个实施例中,形成比器件所期望的栅极长度更厚的半导体膜508。在本发明的一个实施例中,半导体膜508被形成至这样的厚度,即所述厚度将可以使所制造的三栅极晶体管对于其所设计栅极长度(Lg)以完全耗尽的方式工作。半导体膜508可以以任何公知的方法被形成在绝缘衬底502上。在被称为SIMOX技术的、形成绝缘体上硅衬底的一种方法中,氧原子以高剂量被注入到单晶硅衬底中,然后进行退火以在衬底之中形成埋入氧化物506。单晶硅衬底中在埋入氧化物以上的部分成为硅膜508。目前用于形成SOI衬底的另一种技术是外延硅膜转移技术,其通常被称为键合SOI。在此技术中,第一硅晶片具有在其表面生长的薄氧化物,其将在以后作为SOI结构中的埋入氧化物506。接着,将高剂量的氢注入到第一硅晶片中,以在第一晶片的硅表面之下形成高应力区域。此第一晶片然后被翻转并被键合到第二硅晶片的表面。第一晶片随后沿着由氢注入所产生的高应力平面解理。这得到了在顶部具有薄硅层的SOI结构,而埋入氧化物位于在单晶硅衬底上面的所有结构之下。诸如HCl磨平或者化学机械抛光(CMP)之类的公知磨平技术可以被用来将半导体膜508的顶表面磨平至其所期望的厚度。
此时,如果需要的话,可以在SOI衬底502之中形成隔离区域(没有示出),以便将待形成于其中的各个晶体管相互隔离。可以通过将衬底膜508围绕三栅极晶体管的部分由例如公知的光刻和刻蚀技术刻蚀掉,并随后用诸如SiO2的绝缘膜回填被刻蚀区域,来形成隔离区域。
接着,如图5B所示,利用标准的光刻和刻蚀技术,在半导体膜508中定义出用于三栅极晶体管的半导体主体或者鳍状物520。在本发明的一个实施例中,鳍状物或者主体520被图案化成具有宽度518,所述宽度518等于或者大于所制造晶体管栅极长度(Lg)的所期望的宽度。这样,用于制造晶体管的最苛刻的光刻术约束与栅电极图案化相关联,而不是与半导体主体或者鳍状物定义相关联。在本发明的一个实施例中,半导体主体或者鳍状物将具有宽度518,所述宽度518小于或者等于30纳米且理想的是小于或者等于20纳米。在本发明的一个实施例中,半导体主体或者鳍状物具有近似地等于硅主体高度509的宽度518。在本发明的一个实施例中,鳍状物或者主体520具有宽度518,所述宽度518为半导体主体高度509的1/2到半导体主体高度509的两倍之间。
此外,如图5B所示,还可以使用光刻和刻蚀步骤来由半导体膜形成源极焊盘522和漏极焊盘524。焊盘可以被用来将所制造晶体管的各个源区连接起来,并将各个漏区连接起来。
半导体膜508可以通过公知的光刻和刻蚀技术而被图案化成鳍状物和焊盘,这些技术通常包括:通过本领域所熟知的掩蔽、曝光并显影毯覆(blanket)沉积的光刻胶膜来形成光刻胶掩模,然后对齐光刻胶掩模来刻蚀半导体膜,以分别形成一个或多个硅主体或者鳍状物520以及源极和漏极焊盘522和524。刻蚀半导体膜508,直至暴露出下面的埋入氧化物层506为止。可以使用诸如各向异性等离子体刻蚀或者反应离子刻蚀之类的公知半导体刻蚀技术,对齐光刻胶掩模来刻蚀半导体膜508。在半导体膜508被刻蚀以形成半导体主体或者鳍状物520(以及源极/漏极焊盘522和524,如果需要的话)之后,通过诸如化学剥离和O2灰化之类的公知技术去除光刻胶掩模,以制造出如图5B中所示的衬底。
接着,在每一个半导体主体520上并围绕其形成栅极电介质层526。也就是说,栅极电介质层526被形成在每一个半导体主体520的顶表面527上,并被形成在每一个半导体主体520的横向相对的侧壁528和529上。栅极电介质可以是沉积的电介质或者生长的电介质。在本发明的一个实施例中,栅极电介质层526是利用干法/湿法氧化工艺生长的二氧化硅电介质膜。在本发明的一个实施例中,使氧化硅膜生长到5埃至15埃之间的厚度。在本发明的一个实施例中,栅极电介质膜526是沉积的电介质,例如但不限于是诸如金属氧化物电介质之类的高介电常数膜,所述金属氧化物电介质例如为五氧化二钽(Ta2O5)、氧化钛(TiO2)、氧化铪(HfO2)、HfSiOxNy、氧化锆(ZrO2)和氧化镧(LaO2),或者为其他的高K电介质,例如PZT和BST。可以通过诸如化学气相沉积(CVD)之类的任何公知技术来形成高介电常数膜。
接着,还是如图5C所示,形成栅电极530。如图5C所示,这样来形成栅电极530,即在每个半导体主体520顶表面527上形成的栅极电介质层526上、在每个半导体主体侧壁528和529上形成或者与其邻接形成的栅极电介质526上或者邻接所述栅极电介质526来形成。栅电极530具有与在绝缘衬底502上形成的底表面相对的顶表面532,并具有一对横向相对的侧壁534和536。横向相对的侧壁534和536之间的距离定义出三栅极晶体管的栅极长度(Lg)538。通过将合适的栅电极材料毯覆沉积在衬底之上,并随后将该材料图案化成电极530,可以形成栅电极530。栅电极可以被形成为200埃到3000埃之间的厚度533。在实施例中,栅电极的厚度或者高度533至少是半导体主体520高度509的至少三倍。然后利用公知的光刻和刻蚀技术来图案化栅电极材料,以由栅电极材料来形成栅电极530。在本发明的一个实施例中,栅电极材料包括多晶硅。在本发明的另一个实施例中,栅电极材料包括多晶态的锗化硅。在本发明的又一个实施例中,栅电极材料可以包括诸如钨、钽及其氮化物的金属膜。可以通过公知技术来形成栅电极530,例如通过将栅电极材料毯覆沉积在图5B的衬底之上,并随后用公知的光刻和刻蚀技术将该栅电极材料图案化。在本发明的一个实施例中,用于定义出栅电极530的光刻工艺,利用了用于制造三栅极晶体管的最小值的或者最小尺寸的光刻工艺。(就是说,在本发明的一个实施例中,栅电极530的栅极长度(Lg)538具有由光刻术所限定的晶体管最小特征尺寸。)在本发明的一个实施例中,栅极长度538小于或者等于30纳米,且理想的是小于或者等于20纳米。
接着,在栅电极530相对两侧的半导体主体520中形成晶体管的源漏区。在本发明的一个实施例中,源漏区包括尖端或源/漏延伸区域。如图5D所示,通过为形成尖端区域540和542而将掺杂剂544置于栅电极530两侧532、534的半导体主体520之中,可以分别形成源和漏延伸区域540和542。对于PMOS三栅极晶体管,半导体鳍状物或者主体520被掺杂成P型导电性并被掺杂至1×1020原子/cm3至1×1021原子/cm3的浓度。对于NMOS三栅极晶体管,半导体鳍状物或者主体520被n型导电性离子掺杂至1×1020原子/cm3至1×1021原子/cm3的浓度。在本发明的一个实施例中,通过离子注入来掺杂硅膜。在本发明的一个实施例中,离子注入发生在垂直方向上(即垂直于衬底502的方向)。当栅电极530是多晶硅栅电极时,其可以在离子注入工艺过程中被掺杂。栅电极530起到掩模的作用,以防止离子注入步骤掺杂三栅极晶体管的(多个)沟道区域548。沟道区域548是半导体主体520位于栅电极530下方或者被栅电极530所围绕的部分。如果栅电极530是金属电极,则可以使用电介质硬掩模来防止离子注入工艺过程中的掺杂。在其他的实施例中,可以使用诸如固体源扩散之类的其他方法来掺杂半导体主体,以形成源极和漏极延伸。
在本发明的实施例中,在形成源/漏区或者源/漏延伸区域之前,可以在硅主体中形成“晕圈”区域。晕圈区域是形成在器件的沟道区域548中的掺杂区域,并且晕圈区域具有与器件的沟道区域的掺杂相同的导电性,但是具有比器件的沟道区域稍高的掺杂浓度。晕圈区域可以通过利用大角度的离子注入技术,由栅电极下方的离子注入掺杂剂来形成。
接着,如果需要的话,图5C中所示的衬底可以被进一步处理,以形成附加的特征,例如重掺杂的源极/漏极接触区域、为形成加高的源漏区而在源漏区和栅电极上沉积的硅、以及在源极/漏极接触区域和栅电极上形成硅化物。
接着,如图5D所示,位于半导体鳍状物或者主体之下并与其邻接的埋入氧化物层506被去除,以在埋入氧化物层中形成气隙560。可以通过使用选择性刻蚀来去除埋入氧化物层,该选择性刻蚀优选地刻蚀埋入绝缘膜,而不会明显地刻蚀掉半导体主体。当半导体主体是硅并且埋入绝缘层506是氧化硅时,可以利用缓冲HF刻蚀剂来选择性地刻蚀掉埋入氧化硅层。应该认识到可以利用任何合适的湿法或干法刻蚀技术来形成气隙560,该技术可以选择性地刻蚀掉埋入绝缘层,而不会刻蚀掉半导体主体。选择性大于10的刻蚀剂是所期望的。
埋入绝缘体刻蚀可以在有或没有图案化层的晶片上进行,这取决于器件的布局。通常将利用被图案化的光刻胶掩模,其使随后要接收应力膜的晶体管暴露出来,并覆盖将不包括应力膜的那些晶体管。
在本发明的一个实施例中,在从半导体鳍状物或者主体之下去除埋入绝缘膜之后,可以进行快速的氧化或钝化步骤来钝化被暴露的鳍状物的底部,以减小寄生漏电效应。可以使用任何合适的氧化或钝化工艺来形成钝化电介质。在本发明的一个实施例中,鳍状物的底部被SiO2钝化,以形成厚度大于约1纳米的钝化氧化物膜。
在去除下面的绝缘膜506并完成钝化或氧化之后,可以开始应力施加膜560的填充步骤。应力施加膜560必须是绝缘膜,以防止从源极到漏极的短路。应力施加膜的目的是在器件的沟道区域中提供应力。应力施加膜中的应力类型取决于被制造器件的类型。对于载流子是电子的NMOS器件,沟道区域需要受拉应力,以提高电子的迁移率。为了使沟道区域受拉应力,应力施加膜560需要是受压膜。此外,用于形成应力施加膜560的工艺应该是例如气相沉积的保形工艺,该工艺可以将膜均等地毯覆沉积在垂直和水平表面上,并能够填充在半导体主体之下。所期望的是,应力施加膜能够完全填充器件鳍状物或者主体之下的区域。通过以下可以有助于这一点,即让鳍状物更窄或者让下面的绝缘膜层506更厚,以提高沟道区域之下填充的高宽比。在本发明的一个实施例中,应力施加膜是受压氮化硅膜。在本发明的一个实施例中,NMOS器件被制造成具有受压氮化硅膜,通过利用反应物气体混合物的化学气相沉积(CVD)来形成该氮化硅膜,所述混合物包括二氯硅烷(DCS)和氨(NH3)。也可以使用BTBAS来代替DCS。这样一种工艺将可以通过在垂直和水平表面上进行等同的沉积来将氮化硅膜毯覆沉积在衬底上,并使得能够填充半导体主体之下的气隙。
对于载流子是空穴的PMOS器件,沟道区域需要受压,以增加空穴的迁移率。为了使沟道受压,应力施加膜需要是受拉膜。在本发明的一个实施例中,应力施加膜是受拉氮化硅膜。
在本发明的一个实施例中,如图5E所示,应力施加膜被形成为这样的厚度,其足以完全填充沟道区域和半导体主体之下的气隙区域,并完全包围半导体主体和栅电极。应力施加膜完全包围器件并在大范围内提供应力,这导致沟道中提高迁移率的所期望应力。此外,在本发明的一个实施例中,在沉积过程中调制膜的应力特性,从而为器件性能而对膜进行优化。
在沉积完成之后,可以使用掩蔽和刻蚀步骤将应力施加膜从不需要的区域去除,并且可以以正常的方式继续处理以形成“后端(back end)”特征,例如将单个晶体管电耦合成功能电路的金属互连和层间电介质。
这样,就描述了具有应力施加膜的新型非平面器件及其制造方法。

Claims (29)

1.一种半导体器件,包括:
形成在衬底之上的半导体主体,所述半导体主体具有顶表面与横向相对的侧壁;
栅极电介质,所述栅极电介质在所述半导体主体的所述顶表面上、以及在所述半导体主体的所述横向相对的侧壁上形成;
栅电极,所述栅电极在所述半导体主体的所述顶表面上的所述栅极电介质上、以及与所述半导体主体的所述横向相对的侧壁上的所述栅极电介质邻接形成;和
膜,所述膜与所述半导体主体邻接形成,其中所述膜在所述半导体主体中产生应力。
2.如权利要求1所述的半导体器件,其中,所述膜在所述半导体主体中产生压应力。
3.如权利要求1所述的半导体器件,其中,所述膜在所述半导体主体中产生拉应力。
4.如权利要求1所述的半导体器件,其中,所述膜具有拉应力。
5.如权利要求1所述的半导体器件,其中,所述膜具有压应力。
6.如权利要求5所述的半导体器件,其中,所述受压膜包括氮化硅。
7.如权利要求1所述的半导体器件,其中,所述半导体主体是单晶硅膜。
8.如权利要求1所述的半导体器件,其中,所述半导体主体选自由硅、锗、锗化硅、砷化镓、InSb、GaP、GaSb以及碳纳米管所组成的组。
9.一种三栅极晶体管,包括:
在绝缘衬底上形成的单晶硅主体,所述硅主体具有与底表面相对的顶表面、以及第一和第二横向相对的侧壁;
栅极电介质,所述栅极电介质在所述半导体主体的所述顶表面上、以及在所述半导体主体的所述第一和第二横向相对的侧壁上形成;
栅电极,所述栅电极在所述硅主体的所述顶表面上的所述栅极电介质上、以及与所述硅主体的所述第一和第二横向相对的侧壁上的所述栅极电介质邻接形成;
一对源/漏区,所述一对源/漏区形成在所述栅电极的相对两侧的所述硅主体中;和
围绕着所述硅主体和所述栅电极形成的应力产生膜,所述膜在所述器件的沟道区域中提供应力。
10.如权利要求9所述的三栅极晶体管,其中,所述薄膜具有压应力并在所述沟道区域中产生拉应力。
11.如权利要求10所述的三栅极晶体管,其中,所述薄膜包括氮化硅膜。
12.如权利要求9所述的三栅极晶体管,其中,所述薄膜具有拉应力并在所述半导体主体的所述沟道区域中施加压应力。
13.如权利要求10所述的三栅极晶体管,其中,所述半导体主体沟道区域被掺杂成具有1×1016原子/cm3至1×1019原子/cm3之间的浓度水平的P型导电性。
14.如权利要求12所述的三栅极晶体管,其中,所述半导体主体的所述沟道区域被掺杂成具有1×1016原子/cm3至1×1019原子/cm3之间的浓度水平的N型导电性。
15.如权利要求9所述的三栅极晶体管,其中,所述薄膜完全包围所述半导体主体和所述栅电极。
16.如权利要求9所述的三栅极晶体管,其中,在所述薄膜和所述半导体主体的底部之间形成薄的生长氧化物层。
17.一种形成半导体器件的方法,包括:
在绝缘衬底上形成具有顶表面和横向相对侧壁的半导体主体;
在所述半导体主体的所述顶表面上、以及在所述半导体主体的所述横向相对的侧壁上形成栅极电介质;
在所述半导体主体的所述顶表面上的所述栅极电介质上、以及与所述半导体主体的所述横向相对的侧壁上的所述栅极电介质邻接形成栅电极;以及
与所述半导体主体邻接形成薄膜,其中所述薄膜在所述半导体主体中产生应力。
18.如权利要求17所述的方法,其中,所述薄膜在所述半导体主体中产生压应力。
19.如权利要求17所述的方法,其中,所述薄膜在所述半导体主体中产生拉应力。
20.如权利要求17所述的方法,其中,所述薄膜具有拉应力。
21.如权利要求17所述的方法,其中,所述薄膜具有压应力。
22.如权利要求17所述的方法,其中,所述半导体主体包括单晶硅膜。
23.如权利要求17所述的方法,其中,所述半导体主体选自由硅、锗、锗化硅、砷化镓、InSb、GaP、GaSb以及碳纳米管所组成的组。
24.一种形成非平面晶体管的方法,包括:
将在绝缘衬底上形成的单晶硅膜图案化成硅主体,所述硅主体具有与形成在所述绝缘膜上的底表面相对的顶表面、以及第一和第二横向相对的侧壁;
在所述硅主体的所述顶表面上、以及在所述硅主体的所述侧壁上形成栅极电介质层;
在所述硅主体之上以及所述绝缘衬底之上沉积栅极材料;
图案化所述栅极材料,以在所述硅主体的所述顶表面上的所述栅极电介质层上、以及与所述硅主体的所述侧壁上的所述栅极电介质邻接形成栅电极,所述栅电极具有横向相对侧壁,所述栅电极的所述横向相对侧壁垂直于所述硅主体的所述横向相对侧壁延伸;
在所述栅电极的所述横向相对侧壁的相对两侧上的所述半导体主体中形成一对源/漏区,其中在所述硅主体中所述源/漏区之间的区域形成沟道区域;
从所述硅主体沟道区域的一部分之下以及所述硅主体的所述源区和漏区的一部分之下,去除所述绝缘衬底的一部分;以及
在所述栅电极下方所述硅主体的所述暴露部分之下,以及所述栅电极下方所述源区和漏区的所述暴露部分之下,形成其中具有应力的膜。
25.如权利要求24所述的方法,其中,所述薄膜具有压应力,所述压应力在所述沟道区域中产生拉应力。
26.如权利要求24所述的方法,其中,所述薄膜具有拉应力,所述拉应力在所述半导体主体的所述沟道区域中产生压应力。
27.如权利要求24所述的方法,还包括与所述硅主体的所述横向相对侧壁和所述栅电极的所述横向相对侧壁邻接来形成所述薄膜。
28.如权利要求24所述的方法,其中,所述形成所述薄膜的步骤被持续,直到所述硅主体和所述栅电极被所述薄膜完全包围。
29.如权利要求24所述的方法,还包括在暴露所述半导体主体之后,以及形成所述薄膜之前,对所述半导体主体的所述底部进行氧化。
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CN103594513A (zh) * 2012-08-16 2014-02-19 中国科学院微电子研究所 半导体器件及其制造方法
CN105409018A (zh) * 2013-06-29 2016-03-16 英特尔公司 具有多栅极晶体管的压阻谐振器
CN105409018B (zh) * 2013-06-29 2018-01-19 英特尔公司 具有多栅极晶体管的压阻谐振器

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WO2005010997A2 (en) 2005-02-03
US20060261411A1 (en) 2006-11-23
EP1639652B1 (en) 2013-01-23
EP1639652A2 (en) 2006-03-29
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US8405164B2 (en) 2013-03-26
US6909151B2 (en) 2005-06-21
CN1577889B (zh) 2010-05-26
US20050242406A1 (en) 2005-11-03
US6974738B2 (en) 2005-12-13
US20040266083A1 (en) 2004-12-30
US20040262692A1 (en) 2004-12-30
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US7241653B2 (en) 2007-07-10
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US20100200917A1 (en) 2010-08-12
US7714397B2 (en) 2010-05-11

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