CN1577850A - 有部分或全包围栅电极的非平面半导体器件及其制造方法 - Google Patents

有部分或全包围栅电极的非平面半导体器件及其制造方法 Download PDF

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CN1577850A
CN1577850A CN200410050127.0A CN200410050127A CN1577850A CN 1577850 A CN1577850 A CN 1577850A CN 200410050127 A CN200410050127 A CN 200410050127A CN 1577850 A CN1577850 A CN 1577850A
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斯科特·A·黑尔兰德
罗伯特·S·周
布雷恩·S·多伊
拉斐尔·里奥斯
汤姆·林顿
休曼·达塔
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

本发明描述了非平面半导体器件及其制造方法。非平面半导体器件包括具有顶表面的半导体主体，顶表面与形成在绝缘衬底之上的底表面相对，其中半导体主体具有一对横向相对的侧壁。在半导体主体的顶表面上、在半导体主体的横向相对的侧壁上以及在半导体主体的底表面的至少一部分上形成栅极电介质。在半导体主体顶表面上的栅极电介质上、与半导体主体的横向相对的侧壁上的栅极电介质邻接、以及在半导体主体的底表面上的栅极电介质的下方形成栅电极。在栅电极的相对两侧的半导体主体中形成一对源/漏区域。

Description

有部分或全包围栅电极的非平面半导体器件及其制造方法
技术领域
本发明涉及半导体集成电路制造的领域，更具体地，本发明涉及具有部分或者完全包围的栅电极的非平面完全耗尽衬底晶体管及其制造方法。
背景技术
为了提高器件性能，人们已经提出了绝缘体上硅(SOI)晶体管，用于制造新型的集成电路。图1图示了标准的完全耗尽的绝缘体上硅(SOI)晶体管100。SOI晶体管100包括具有绝缘层104的单晶硅衬底102，所述绝缘层104例如是形成在单晶硅衬底102上的埋入氧化物。单晶硅主体106被形成在绝缘层104上。栅极电介质层108被形成在单晶硅主体106上，并且栅电极110被形成在栅极电介质108上。源极112和漏极114区域沿栅电极110横向相对的两侧形成在硅主体106中。
完全耗尽的SOI已经作为一种晶体管结构被提出，该晶体管结构利用理想的亚阈值梯度，以获得最优化的导通电流/关断电流比。为了利用晶体管100实现理想的亚阈值梯度，硅主体106的厚度必须是晶体管的栅极长度(Lg)的约1/3大小，或者Tsi＝Lg/3。但是，当栅极长度缩减，特别是当栅极长度接近30nm时，对于不断减小硅膜厚度(Tsi)的需要使得此方法越来越不切实际。对于30纳米的栅极长度，所要求的硅主体厚度被认为需要小于10纳米，对于20纳米的栅极长度，所要求的硅主体厚度需要到约6纳米。制造厚度小于10纳米的薄硅膜被认为是极其困难的。一方面，获得一个纳米数量级的晶片均匀性是非常困难的挑战。另一方面，如下的情况，即能够接触这些薄膜来形成加高的源/漏区域以降低结电阻，变成几乎是不可能的，因为在栅极刻蚀以及栅极刻蚀和隔片刻蚀之后的各种清洗的过程中，源/漏区域中的薄硅层被消耗，留下的硅106不足以使硅在上面生长。
已经提出了诸如图2A和2B中示出的双栅极(DG)器件，来解决硅厚度的问题。双栅极(DG)器件200包括形成在绝缘衬底204上的硅主体202。栅极电介质206被形成在硅主体202的两侧，并且邻接被形成在硅主体202两侧的栅极电介质206来形成栅电极208。足够厚的诸如氮化硅的绝缘层209将栅电极208与硅主体202的顶部电隔离。
双栅极(DG)器件200实质上具有两个栅极，一个栅极位于器件沟道两侧中的一侧。因为双栅极器件200在沟道的每一侧都具有栅极，所以硅主体的厚度(Tsi)可以是单栅极器件的硅主体厚度的两倍，并仍然实现完全耗尽的晶体管的作用。也就是说，利用双栅极器件200，在Tsi＝(2×Lg)/3的情况下可以形成完全耗尽的晶体管。但是，双栅极(DG)器件200最可能制造的形式，要求利用比用于图案化器件的栅极长度(Lg)的光刻术小0.7倍的光刻术，来对主体202进行图案化。为了获得高密度的集成电路，通常理想的是对于栅电极208的栅极长度(Lg)进行最具侵蚀性的光刻术。虽然，双栅极结构使硅膜的厚度变为两倍(因为现在在沟道的两侧都存在栅极)，但是这些结构极难制造。例如，硅主体202要求可以制造具有约5∶1的高宽比(高度比宽度)的硅主体202的硅主体刻蚀。
图3图示了柱状的MOSFET 300。柱状的MOSFET 300包括形成在半导体衬底中的漏区域302。圆形硅柱303被形成在半导体衬底上。围绕该圆柱来形成栅极电介质层306和栅电极304。源区域308被形成在硅柱的顶部。电流在垂直于衬底的方向上在源漏区域之间流动。柱状MOSFET300的问题在于其是利用复杂的非常规的处理技术形成的。柱状MOSFET的另一个问题是源漏区域是被单独处理的，导致这些区域具有不同的电特性。
发明内容
为了解决上述问题，提出了本发明。根据本发明的一个方面，提供了一种非平面半导体器件，包括：半导体主体，所述半导体主体具有顶表面，所述顶表面与形成在绝缘衬底之上的底表面相对，其中所述半导体主体具有一对横向相对的侧壁；栅极电介质，在所述半导体主体的所述顶表面上、在所述半导体主体的所述底表面上以及在所述半导体主体的所述横向相对的侧壁上形成所述栅极电介质；栅电极，在所述半导体主体的所述顶表面上的所述栅极电介质上、与所述半导体主体的所述横向相对的侧壁上的所述栅极电介质邻接、以及在所述半导体主体的所述底表面上的所述栅极电介质的下方形成所述栅电极；以及一对源/漏区域，所述一对源/漏区域形成在所述栅电极的相对两侧的所述半导体主体中。
根据本发明的另一个方面，提供了一种非平面半导体器件，包括：半导体主体，所述半导体主体具有顶表面，所述顶表面与底表面相对，所述底表面具有形成在绝缘衬底上的一部分，所述半导体主体具有形成在所述绝缘衬底上方的横向相对的侧壁；栅极电介质，在所述半导体主体的所述顶表面上、在所述半导体主体的所述横向相对的侧壁上、在所述半导体主体的底表面中不在所述绝缘衬底上的部分上形成所述栅极电介质；栅电极，在所述半导体主体的所述顶表面上的所述栅极电介质上、与所述半导体主体的所述横向相对的侧壁上的所述栅极电介质邻接、以及在所述半导体主体的所述底表面上的所述栅极电介质的下方形成所述栅电极；以及一对源/漏区域，所述一对源/漏区域形成在所述栅电极的相对两侧的所述半导体主体中。
根据本发明的另一个方面，提供了一种形成非平面半导体器件的方法，包括：在绝缘衬底上方形成半导体主体，所述半导体主体具有一对横向相对的侧壁和与底表面相对的顶表面；在所述半导体主体的所述顶表面上、在所述半导体主体的所述横向相对的侧壁上以及在所述半导体主体的所述底表面的至少一部分上形成栅极电介质；在所述半导体主体的所述顶表面上的所述栅极电介质上、与所述半导体主体的所述横向相对的侧壁上的所述栅极电介质邻接、以及下邻接形成在所述半导体主体的所述底表面的至少一部分上的所述栅极电介质来形成栅电极；以及在所述栅电极的相对两侧的所述半导体主体中形成一对源/漏区域。
根据本发明的另一个方面，提供了一种形成非平面晶体管的方法，包括：在绝缘衬底上形成半导体主体，所述半导体主体具有一对横向相对的侧壁、顶表面以及底表面；从所述半导体主体的下方去除所述绝缘衬底的一部分，以底切所述半导体主体并暴露出所述半导体主体的所述底表面的一部分；在所述半导体主体的所述顶表面上、在所述半导体主体的所述侧壁上、以及在所述半导体主体的所述暴露底部上形成栅极电介质；在所述半导体主体的上方并围绕所述半导体主体、以及在所述半导体主体的所述暴露部分的下方沉积栅极材料；利用第一各向异性刻蚀并随后进行各向同性刻蚀，将栅电极材料刻蚀成栅电极，以形成栅电极，其中在所述半导体主体的所述顶表面上的所述栅极电介质之上、与形成在所述半导体主体的所述侧壁上的所述栅极电介质形成所述栅电极邻接、以及在形成在所述半导体主体的所述底表面的所述暴露部分上的所述栅极电介质的下方形成所述栅电极；以及将掺杂剂置于所述栅电极的相对两侧的所述半导体主体中，以形成一对源/漏区域。
根据本发明的另一个方面，提供了一种形成非平面晶体管的方法，包括：在绝缘衬底上形成半导体主体，所述半导体主体具有顶表面、底表面以及一对横向相对的侧壁；在所述半导体主体上方并围绕所述半导体主体形成电介质膜，其中所述电介质膜具有开口，所述开口暴露出所述半导体主体的沟道区域；去除所述绝缘衬底在所述开口中位于所述半导体主体下方的一部分，以暴露出所述半导体主体的所述底表面的至少一部分；在所述开口中的所述半导体主体的所述顶表面上和所述侧壁上、以及在所述半导体主体的所述底表面的所述暴露部分上形成栅极电介质层；在所述电介质膜的上方、在所述开口之中、以及在所述半导体主体的所述顶表面上的所述栅极电介质上、与所述半导体主体的所述侧壁上的所述栅极电介质邻接、以及在所述半导体主体的所述暴露部分上的所述栅极电介质的下方，毯覆沉积栅电极材料；从所述电介质膜的所述顶表面去除所述栅电极材料，以形成栅电极；去除所述电介质膜；以及将掺杂剂置于所述电极的相对两侧的所述半导体主体中，以形成一对源/漏区域。
根据本发明的另一个方面，提供了一种形成非平面晶体管的方法，包括：在绝缘衬底上形成半导体主体，所述半导体主体具有顶表面、底表面以及一对横向相对的侧壁；在所述半导体主体的所述顶表面之上并且邻接所述半导体主体的所述横向相对侧壁形成牺牲栅电极，所述牺牲栅电极具有一对横向相对的侧壁；将掺杂剂置于所述牺牲栅电极的相对两侧的所述半导体主体中，以在所述栅电极的相对两侧形成一对源极/漏极延伸；沿着所述牺牲栅电极的横向相对的侧壁，形成一对侧壁隔片；邻接所述侧壁隔片在所述半导体主体上形成硅；对齐所述侧壁隔片将掺杂剂置于所述硅和所述半导体主体之中；在邻接所述侧壁隔片而在所述半导体主体上所形成的硅上，形成硅化物；在所述硅化物、所述牺牲栅极和所述侧壁隔片上形成电介质层；对所述电介质层进行平坦化，直至所述电介质层的所述顶表面与所述牺牲栅电极的顶表面平齐，并且暴露出所述牺牲栅电极为止；去除所述牺牲栅电极，以暴露出所述半导体主体的沟道区域和所述绝缘衬底；去除所述绝缘衬底在所述开口中的位于所述半导体主体下方的一部分，以暴露出所述半导体主体的所述底表面的至少一部分；在所述开口中的所述半导体主体的所述顶表面上和所述侧壁上、以及在所述半导体主体的所述暴露底表面的所述部分上形成栅极电介质层；在所述栅极电介质层上、在所述开口之中、以及在所述半导体主体的所述顶表面上的所述栅极电介质层上、与所述半导体主体的所述侧壁上的所述栅极电介质邻接、以及在所述半导体主体所述底表面的所述暴露部分上的所述栅极电介质的下方，毯覆沉积栅电极材料；以及从所述电介质膜的所述顶表面去除所述栅电极材料，以形成栅电极。
附图说明
图1是耗尽的衬底晶体管的横截面视图的示图。
图2A和图2B图示了双栅极耗尽的衬底晶体管。
图3是柱状MOSFET的示图。
图4A-4C图示了具有完全包围的或者几乎包围的栅电极的非平面晶体管。
图5是具有多个半导体主体的非平面晶体管的示图，其中所述半导体主体具有完全包围的或者部分包围的栅电极。
图6A-6G图示了利用减成制造工艺制造具有完全包围的或者几乎包围的栅电极的非平面晶体管的方法。
图7A-7D图示了利用替换栅极制造工艺形成具有完全包围的或者几乎包围的栅电极的非平面晶体管的方法。
图8A-8G图示了利用替换栅极制造工艺形成具有完全包围的或者几乎包围的栅电极的非平面晶体管的方法。
图9是图示了可以被用来获得部分耗尽的和完全耗尽的非平面晶体管的主体高度和主体宽度的曲线，所述非平面晶体管分别具有20纳米和30纳米的栅极长度(Lg)。
具体实施方式
本发明是一种新型的非平面器件结构及其制造方法，其中，所述非平面器件结构具有完全包围沟道区域的栅电极或者几乎完全包围沟道区域的栅电极。在下面的详细描述中阐述了很多具体细节，以便于充分理解本发明。在另外一些例子里，没有对公知的半导体工艺和制造技术进行详细的描述，以避免不必要地模糊本发明。
本发明是一种新型的非平面晶体管结构。在本发明的实施例中，非平面晶体管具有完全包围沟道区域的栅电极。在本发明的另一个实施例中，非平面晶体管具有部分或者几乎完全包围晶体管沟道区域的栅电极。具有完全包围沟道区域或者几乎完全包围沟道区域的栅电极的晶体管的优点是，更容易耗尽器件的沟道区域，并由此放宽对于半导体主体厚度(Tsi)和宽度(Wsi)的尺寸限制。此外，通过完全或者部分地围绕器件的沟道，由于在器件中提供了两个额外的角部，这增大了载流子的密度，从而增大了器件的驱动电流。
图4A是非平面晶体管400的俯视图，所述非平面晶体管400根据本发明的实施例具有完全包围栅电极或者部分包围栅电极。图4B是当栅电极部分包围器件沟道区域时穿过栅电极所取的图4A的横截面视图。图4C是当栅电极完全包围器件沟道区域时穿过栅电极所取的图4A的横截面视图。非平面器件结构理想地用于在完全耗尽的衬底晶体管应用中。非平面器件结构包括形成在绝缘衬底402上的薄半导体主体408。栅极电介质422被形成在半导体主体的顶表面、侧壁以及底表面的至少一部分上。在位于半导体主体的顶表面上的栅极电介质422上、与被形成在半导体主体的侧壁上的栅极电介质邻接以及在被形成在半导体主体的底表面上的栅极电介质的下方形成栅电极424。在栅电极424相对两侧的半导体主体408中形成源漏区域。因为栅电极和栅极电介质在三个侧面和第四侧面的至少一部分上围绕半导体主体408的沟道区域，所以当晶体管被“导通”时，半导体主体可以容易地被完全耗尽，由此可以形成栅极长度小于30纳米的完全耗尽的晶体管，而不需要使用超薄的半导体主体或者要求将半导体主体光刻图案化至小于器件的栅极长度(Lg)的尺寸。也就是说，本发明的非平面晶体管的结构可以制造完全耗尽的晶体管，其中半导体主体的厚度和半导体主体的宽度等于器件的栅极长度。因为本发明的新型非平面晶体管可以以完全耗尽的方式工作，所以该器件的特征在于理想的(即非常陡峭的)亚阈值斜率(理想的是在25℃下为60mV/decade)，以及小于100mV/V(理想的是约60mV/V)的减小的漏极导致势垒下降(DIBL)短沟道效应，这导致当器件被“关断”时更低的漏电流，从而得到更低的功耗。
根据本发明的实施例的非平面晶体管400的示例被图示在图4A-4C中。非平面晶体管400被形成在绝缘衬底402上。在本发明的实施例中，绝缘衬底402包括下部的单晶硅衬底404，其中诸如二氧化硅膜的绝缘层406被形成在所述单晶硅衬底404上。然而，非平面晶体管400可以被形成在任何公知的绝缘衬底上，所述绝缘衬底例如是由二氧化硅、氮化物、氧化物和蓝宝石形成的衬底。
非平面晶体管400包括半导体主体408。半导体主体408提供器件的源区域430、漏区域432和沟道区域450。半导体主体408可以由任何公知的半导体材料形成，所述半导体材料例如但不限于是硅(Si)、锗(Ge)、硅锗合金(SixGey)、砷化镓(GaAs)、InSb、GaP、GaSb和碳纳米管。半导体主体408可以由任何公知的材料形成，所述公知的材料可以通过施加外部电控制从绝缘状态转变至导电状态。当希望晶体管400具有最佳的电性能时，半导体主体408理想地是单晶膜。例如，当晶体管400被用于高性能应用中，例如被用于诸如微处理器的高密度电路中时，半导体主体408是单晶膜。然而，当晶体管400被用于对性能的要求不那么苛刻的应用，例如用于液晶显示器中时，半导体主体408可以是多晶膜。绝缘体406使半导体主体408与单晶硅衬底402绝缘。在本发明的实施例中，半导体主体408由单晶硅膜所形成。
半导体主体408具有一对横向相对的侧壁410和412，所述一对侧壁410和412被定义出半导体主体宽度(Wsi)414的距离所隔开。此外，半导体主体408具有顶表面416，所述顶表面416与形成在衬底402上的底表面418相对。顶表面416和底表面418之间的距离定义出主体高度(Tsi)420。在本发明的实施例中，主体高度420基本上等于主体宽度(Wsi)414。在本发明的实施例中，主体408具有小于30纳米并且理想的是小于20纳米的宽度414和高度(Tsi)420。在本发明的实施例中，主体高度420在主体宽度414的1/2到主体宽度414的两倍之间。
非平面器件400具有栅极电介质层422。如图4A-4C所示，这样来形成栅极电介质层422，即在半导体主体408沟道区域350的三个侧面上并围绕沟道区域350的三个侧面、以及在半导体主体408沟道区域450的底表面418的至少一部分上或者下邻接该至少一部分来形成。在本发明的部分交叠的实施例中，如图4B所示，在侧壁412上或者邻接侧壁412、在顶表面416上、在侧壁410上或者邻接侧壁410，并且在半导体主体408底表面418的从侧壁412向底表面中心延伸的一部分上形成栅极电介质层422，并且栅极电介质层422覆盖从侧壁410向底表面418中心部分延伸的第二部分。在图4B中示出的几乎包围的实施例中，栅极电介质层422至少覆盖半导体主体408的下角部423，在另一个实施例中，栅极电介质层422在每一侧延伸半导体主体408宽度的约1/3。在图4C中示出的完全包围的实施例中，在半导体主体408的沟道区域的侧壁412上或者邻接侧壁412、在顶表面416上、在侧壁410上或者邻接侧壁410、以及在整个底表面418上形成栅极电介质层422。栅极电介质层422可以是任何公知的栅极电介质层。在本发明的实施例中，栅极电介质层是二氧化硅(SiO2)、氧氮化硅(SiOxNy)或者氮化硅(Si3N4)电介质层。在本发明的实施例中，栅极电介质层422是厚度被形成至5埃到20埃之间的氧氮化硅膜。在本发明的实施例中，栅极电介质层422是诸如金属氧化物电介质的高K值栅极电介质层，所述金属氧化物电介质例如但不限于是五氧化二钽(Ta2O5)、氧化钛(TiO2)、氧化铪(HfO2)、HfSiOxNy、氧化锆(ZrO2)和氧化镧(LaO2)。栅极电介质层422可以是其他类型的高K值电介质，例如但不限于是PZT。
非平面器件400具有栅电极424。如图4A-4C所示，在栅极电介质层422上并围绕其形成栅电极424。在图4B中示出的本发明的部分交叠的实施例中，这样来形成栅电极424，即在形成在半导体主体408沟道区域450的侧壁412上的栅极电介质422上或者邻接所述栅极电介质422、在半导体主体408沟道区域的顶表面416上形成的栅极电介质层422上、在半导体主体408沟道区域的侧壁410上形成的栅极电介质层422上或者邻接所述电介质层422、以及在半导体主体408沟道区域的底表面418的下方形成的栅极电介质层422的下方或者在所述栅极电介质层422之下与其紧邻来形成。在本发明的几乎全围绕栅电极晶体管的实施例中，栅电极424在半导体主体的沟道区域450的每一侧，在底表面418的下方延伸半导体主体408的宽度的约1/3。其目标是使栅电极围绕器件的角部423，以便足以提供良好的角部控制。在几乎全围绕的实施例中，底表面的剩余部分被形成埋入绝缘层406上。在图4C中示出的完全包围的实施例中，这样来形成栅电极424，即在形成在半导体主体408沟道区域的侧壁412上的栅极电介质层422上或者邻接所述栅极电介质422、在半导体主体408沟道区域的顶表面416上形成的栅极电介质层422上、与在半导体主体408沟道区域的侧壁410上形成的栅极电介质层422邻接或者在所述电介质层422上、以及在半导体主体408沟道区域形成的栅极电介质层422的下方或者在所述栅极电介质层422之下与其紧邻来形成。栅电极424具有一对横向相对的侧壁426和428，所述一对侧壁426和428被定义出晶体管400的栅极长度(Lg)430的距离所隔开。在本发明的实施例中，栅电极424的横向相对的侧壁426和428在与半导体主体408的横向相对的侧壁410和412垂直的方向上延伸。
栅电极424可以由任何合适的栅电极材料形成。在本发明的实施例中，栅电极424由被掺杂至浓度为1×1019原子/cm3至1×1021原子/cm3之间的多晶硅组成。在本发明的实施例中，栅电极可以是金属栅电极，例如但不限于是钨、钽、钛以及它们的氮化物。在本发明的实施例中，栅电极由具有与沟道材料相一致的功函数(例如，对于硅为4.0-5.2eV)的材料所形成。应该理解，栅电极424不必是单一的材料，而可以是若干薄膜的复合堆叠，例如但不限于多晶硅/金属电极或者金属/多晶硅电极。
非平面晶体管400具有源区域430和漏区域432。如图4A所示，源区域430和漏区域432被形成在栅电极424相对两侧的半导体主体408中。源区域430和漏区域432形成诸如N型或者P型导电性的同一导电类型。在本发明的实施例中，源区域430和漏区域432具有1×1019原子/cm3至1×1021原子/cm3之间的掺杂浓度。源区域430和漏区域432可以形成均一的浓度或者可以包括不同浓度或者掺杂分布(doping profile)的子区域，诸如尖端(tip)区域(例如，源/漏延伸区)。在本发明的实施例中，当晶体管400是对称的晶体管时，源区域430和漏区域432具有相同的掺杂浓度和分布。在本发明的实施例中，当非平面晶体管400被形成为非对称晶体管时，源区域430和漏区域432的掺杂浓度和特征可以不同，以便获得特定的电特性。源和漏区域还可以包括外延硅再生长物和/或硅化物，以提高器件的性能。
半导体主体408位于源区域430和漏区域432之间的部分，限定出晶体管400的沟道区域450。沟道区域450还可以被限定为半导体主体408中由栅电极424所围绕的区域。但是，有时源/漏区域可以通过例如扩散稍微地延伸到栅电极的下方，以限定出稍微小于栅电极长度(Lg)的沟道区域。在本发明的实施例中，沟道区域450是本征或者未掺杂的单晶硅。在本发明的实施例中，沟道区域450是掺杂的单晶硅。当沟道区域450被掺杂时，其通常被掺杂到1×1016原子/cm3至1×1019原子/cm3之间的导电水平。在本发明的实施例中，当沟道区域被掺杂时，其通常被掺杂成与源区域430和漏区域432相反的导电类型。例如，当源漏区域是N型导电性时，沟道区域450将被掺杂至P型导电性。类似地，当源漏区域是P型导电性时，沟道区域450将是N型导电性。这样，非平面晶体管400可以分别被形成为NMOS晶体管或者PMOS晶体管。沟道区域450可以是被均匀掺杂的，或者可以是被非均匀掺杂的或者以不同的浓度进行掺杂，以提供特定的电特性和性能特性。例如，如果需要的话，沟道区域450可以包括公知的“晕圈(halo)”区域。当晶体管被“导通”时，电流在源区域430和漏区域之间通过被栅控的沟道区域450而在平行于衬底402平面的方向上流动。
通过提供围绕半导体主体所有侧面的栅极电介质和栅电极，非平面晶体管可以具有下列特征，即具有四个沟道和四个栅极：在半导体主体408的侧面412上在源漏区域之间延伸的第一栅极(g1)和第一沟道；在半导体主体408的顶表面416上在源漏区域之间延伸的第二栅极(g2)和第二沟道；在半导体主体408的侧壁410上在源漏区域之间延伸的第三栅极(g3)和第三沟道；以及在半导体主体408的底表面418上位于源漏区域之间的第四栅极(g4)和第四沟道。晶体管400的栅极“宽度”(Gw)是四个栅极的宽度的总和。也就是说，晶体管400的栅极宽度等于硅主体408在侧壁410处的高度420，加上硅主体408在顶表面416处的宽度，加上硅主体408在侧壁412处的高度420，加上半导体主体408在栅电极424之上的底表面的量。通过使用耦合到一起的多个器件(例如，由单个栅电极424所围绕的多个硅主体408)，可以得到更大“宽度”的晶体管。
如上所述，晶体管400的栅极“宽度”等于由晶体管400的半导体主体408所生成的四个栅极宽度的总和。为了制造具有更大栅极宽度的晶体管，晶体管400可以包括如图5中所示的附加的或者多个半导体主体或者指状物408。如图5所示，每一个半导体主体408具有栅极电介质层422，所述栅极电介质层422被形成在其顶表面、侧壁以及底表面或者底表面的一部分上。在每一半导体主体408上的各个栅极电介质422上并且邻接所述各个栅极电介质422形成栅电极424。如图5所示，每一个半导体主体408还包括源区域430和漏区域432，所述源区域430和漏区域432被形成在栅电极424的相对两侧的半导体主体408中。在本发明的实施例中，每一个半导体主体408形成有与其他的半导体主体408相同的宽度和高度(厚度)。在本发明的实施例中，如图5所示，半导体主体408的每一个源区域430和漏区域432通过源极焊盘(landing pad)560和漏极焊盘580被电耦合在一起。或者，可以通过用来将各种晶体管400电互连到一起成为功能电路的更高层面的金属化(例如，金属1、金属2、金属3...)，将源区域430和漏区域432耦合在一起。如图5所示的晶体管400的栅极宽度等于由每一个半导体主体408所产生的栅极宽度的总和。这样，可以形成具有任意所需栅极宽度的三栅极(trigate)晶体管400。
因为沟道区域450在所有侧面上被栅电极424和栅极电介质422所围绕，所以晶体管400可以以完全耗尽的方式工作，其中，当晶体管400被“导通”时，沟道区域450完全耗尽，由此提供完全耗尽的晶体管的有利电特性和性能。就是说，当晶体管400被“导通”时，在沟道区域450中形成耗尽区域，并同时在区域450的表面处形成反型层(即在半导体主体的侧表面410和412、顶表面416和底表面418上形成反型层)。反型层具有与源漏区域相同的导电类型，并且在源漏区域之间形成导电沟道，以允许电流在其间流动。耗尽区域耗尽来自反型层下方的自由载流子。除反型层以外的整个沟道区域450被耗尽了载流子，因此晶体管可以被称为是“完全耗尽的”晶体管。相对于非完全耗尽的或者部分耗尽的晶体管，完全耗尽的晶体管的电性能特性提高了。例如，使晶体管400在完全耗尽的方式下工作，为晶体管400提供了理想的或者非常陡峭的亚阈值斜率。即使当非平面晶体管被制造成具有小于30nm的半导体主体厚度时，该非平面晶体管也可以被制成具有小于80mV/decade并且理想的是约60mV/decade的非常陡峭的亚阈值斜率。此外，当使晶体管400在完全耗尽的方式下工作时，晶体管400具有改善的漏极导致势垒下降(DIBL)效应，这提供了更好的“关断”状态漏流，实现了更低的漏流并由此降低了功耗。在本发明的实施例中，三栅极晶体管400具有小于100mV/V且理想的是小于40mV/V的DIBL效应。
图9是两条曲线902和904的示图，所述两条图线902和904给出了将产生完全耗尽的(F.D)或者部分耗尽的(P.D)非平面晶体管的主体高度和主体宽度，其中所述非平面晶体管分别具有30nm(902)和20nm(904)的栅极长度(Lg)。在本发明的实施例中，主体高度、主体宽度和栅极长度被选择为具有将形成完全耗尽的晶体管的尺寸。在其他的实施例中，非平面晶体管具有将形成部分耗尽的晶体管的主体高度、主体宽度和栅极长度。
本发明的非平面晶体管可以被认为是非平面晶体管，因为沟道区域450的反型层被形成在半导体主体408中的水平方向上以及垂直方向上。本发明的半导体器件也可以被认为是非平面器件，因为来自栅电极424的电场被从水平侧(g2和g4)以及垂直侧(g1和g3)上施加。
在图6A-6G中图示了根据本发明实施例制造具有部分或者完全包围的栅电极的非平面晶体管的方法。图6A-6G的方法可以被称为减成制造工艺。非平面晶体管的制造开始于绝缘衬底602。如图6A所示，在绝缘衬底602上形成硅或者半导体膜608。在本发明的实施例中，绝缘衬底602包括下部的单晶硅衬底604和顶部的诸如二氧化硅膜或者氮化硅膜之类的绝缘层606。绝缘层606将半导体膜608与衬底604隔离，并且在实施例中被形成至200埃至2000埃之间的厚度。绝缘层606有时被称为“埋入氧化物”层。当硅或者半导体膜608被形成在绝缘衬底602上时，制造出了绝缘体上硅或者半导体(SOI)衬底。
虽然半导体膜608理想的是硅膜，但是在其他实施例中它可以是其他类型的半导体膜，例如但不限于是锗(Ge)、硅锗合金(SixGey)、砷化镓(GaAs)、InSb、GaP、GaSb以及碳纳米管。在本发明的实施例中，半导体膜608是本征的(即未掺杂的)硅膜。在其他实施例中，半导体膜608被掺杂成具有1×1016原子/cm3至1×1019原子/cm3之间的浓度水平的p型或者n型导电性。半导体膜608可以被原位掺杂(即当被沉积时进行掺杂)或者在形成在衬底602上之后通过例如离子注入来进行掺杂。在形成之后进行掺杂可以允许在同一绝缘衬底上容易地同时制造出PMOS以及NMOS非平面器件。此时的半导体主体掺杂水平就决定了器件的沟道区域的掺杂水平。
半导体膜608被形成至这样的厚度，即所述厚度近似地等于所制造非平面晶体管的后续形成的(多个)半导体主体所期望的高度。在本发明的实施例中，半导体膜608具有小于30纳米且理想的是小于20纳米的厚度或者高度609。在本发明的实施例中，半导体膜608被形成至这样的厚度，即所述厚度近似地等于所制造非平面晶体管的所期望的栅极“长度”。在本发明的实施例中，形成比器件的所期望的栅极长度更厚的半导体膜608。在本发明的实施例中，半导体膜608被形成至这样的厚度，即所述厚度将可以使所制造的非平面晶体管对其设计栅极长度(Lg)以完全耗尽的方式工作。
半导体膜608可以以任何公知的方法被形成在绝缘衬底602上。在被称为SIMOX技术的、形成绝缘体上硅衬底的一种方法中，氧原子以高剂量被注入到单晶硅衬底中，然后进行退火以在衬底之中形成埋入氧化物606。单晶硅衬底中在埋入氧化物以上的部分成为硅膜608。目前用于形成SOI衬底的另一种技术是外延硅膜转移技术，其通常被称为键合SOI。在此技术中，第一硅晶片具有在其表面生长的薄氧化物，其将在以后作为SOI结构中的埋入氧化物606。接着，将高剂量的氢注入到第一硅晶片中，以在第一晶片的硅表面之下形成高应力区域。此第一晶片然后被翻转并被键合到第二硅晶片的表面。第一晶片随后沿着由氢注入所产生的高应力平面解理。这得到了在顶部具有薄硅层的SOI结构，而埋入氧化物位于在单晶硅衬底上面的所有结构之下。诸如HCl磨平或者化学机械抛光(CMP)之类的公知磨平技术可以被用来将半导体膜608的顶表面磨平至其所期望的厚度。
此时，如果需要的话，可以在SOI半导体膜608之中形成隔离区域(没有示出)，以便将待形成于其中的各个晶体管相互隔离。可以通过将衬底膜608围绕非平面晶体管的部分由例如公知的光刻和刻蚀技术刻蚀掉，并随后用诸如SiO2的绝缘膜回填被刻蚀区域，来形成隔离区域。
接着，如图6B所示，利用标准的光刻和刻蚀技术，在半导体膜608中定义出用于三栅极晶体管的半导体主体或者鳍状物620。在本发明的实施例中，鳍状物或者主体620被图案化成具有宽度618，所述宽度618等于或者大于所制造晶体管栅极长度(Lg)的所期望的宽度。这样，使用于制造晶体管的最苛刻的光刻术约束与栅电极图案化相关联，而不是与半导体主体或者鳍状物定义相关联。在本发明的实施例中，半导体主体或者鳍状物将具有宽度618，所述宽度618小于或者等于30纳米且理想的是小于或者等于20纳米。在本发明的实施例中，半导体主体或者鳍状物具有近似地等于硅主体高度609的宽度618。在本发明的实施例中，鳍状物或者主体620具有宽度618，所述宽度618为半导体主体高度609的1/2到半导体主体高度609的两倍之间。
此外，可以使用光刻和刻蚀步骤来形成如图5中所示的用于单个晶体管的多个半导体主体或者鳍状物。这样，在整个晶片上，可以制造具有不同栅极宽度(Gw)的若干晶体管。还可以使用光刻和刻蚀步骤来由半导体膜形成源极焊盘622和漏极焊盘624，以便为晶体管提供接触区域。此外，当多个半导体主体被用于非平面晶体管中时，焊盘可以被用来将各个源区域连接起来，以及将各个漏区域连接起来。
半导体膜608可以通过公知的光刻和刻蚀技术而被图案化成鳍状物和焊盘，这些技术通常包括：通过掩蔽、曝光并显影毯覆(blanket)沉积的光刻胶膜来形成光刻胶掩模，然后对齐光刻胶掩模来刻蚀半导体膜，以分别形成一个或多个硅主体或者鳍状物620以及源漏极焊盘622和624。刻蚀半导体膜608，直至暴露出下面的埋入绝缘层606为止。可以使用诸如各向异性等离子体刻蚀或者反应离子刻蚀之类的公知半导体刻蚀技术，对齐光刻胶掩模来刻蚀半导体膜608。在半导体膜608被刻蚀以形成半导体主体或者鳍状物620(以及源极/漏极焊盘622和624，如果需要的话)之后，通过诸如化学剥离和O2灰化之类的公知技术去除光刻胶掩模，以制造出如图6B中所示的衬底。
接着，如图6C所示的，埋入氧化层606中形成在半导体主体620下方的一部分被去除。可以进行快速各向同性氧化物刻蚀来对半导体主体620进行“底切”并去除埋入氧化层606在半导体主体620下方的一部分或者全部。在制造几乎包围的栅电极时，绝缘刻蚀(底切刻蚀)仅仅去除绝缘膜在半导体主体620下方的一部分。在本发明的实施例中，刻蚀自半导体主体620每侧的下方去除绝缘膜606的主体宽度的约1/3。当形成具有完全包围的栅电极的晶体管时，自半导体主体620的下方去除埋入绝缘层606的整个部分。在这种情况下，半导体主体620可以由形成在埋入绝缘层剩余部分上的源漏极焊盘622和624来支撑。可以使用任何公知的对于半导体材料具有选择性的各向同性氧化物刻蚀(即，可以优选刻蚀绝缘膜606而不会明显刻蚀半导体膜608的刻蚀)。具有至少10∶1的选择性的刻蚀是所希望的。当半导体膜608是硅而绝缘膜606是氧化硅时，可以使用包含氟化氢(HF)的缓冲氧化物刻蚀(BOE)。
接着，在每一个半导体主体620上并围绕其形成栅极电介质层626。也就是说，栅极电介质层626被形成在半导体主体620的顶表面627上，并被形成在每一个半导体主体620的横向相对的侧壁628和629上。当形成部分包围的栅电极时，栅极电介质层626被形成在半导体主体620的底侧的暴露部分631上。当形成完全包围的栅电极时，栅极电介质层被形成在被暴露的半导体主体的整个底表面上。栅极电介质可以是沉积的电介质或者生长的电介质。栅极电介质层626应该通过保形工艺形成，其中所述保形工艺可以允许在半导体主体620的底侧上形成电介质626。在本发明的实施例中，栅极电介质层626是利用干法/湿法氧化工艺生长的二氧化硅电介质膜。在本发明的实施例中，使氧化硅膜生长到5埃至15埃之间的厚度。在本发明的实施例中，栅极电介质膜626是沉积的电介质，例如但不限于是诸如金属氧化物电介质之类的高介电常数膜，所述金属氧化物电介质例如为五氧化二钽(Ta2O5)、氧化钛(TiO2)、氧化铪(HfO2)、HfSiOxNy、氧化锆(ZrO2)和氧化镧(LaO2)，或者为其他的高K值电介质，例如通过化学气相沉积(CVD)或者原子层沉积(ALD)形成的PZT和BST。
接着，还是如图6D所示，栅电极材料630被毯覆沉积在衬底上方。这样来形成栅电极630，即在半导体主体620顶表面627上形成的栅极电介质层626上、在半导体主体620侧壁628和629上形成或者与其邻接形成的栅极电介质626上或者邻接所述栅极电介质626、以及在主体620的底部上的栅极电介质下方或者下邻接所述电介质来形成。通过诸如CVD或者ALD之类的保形工艺形成栅电极材料630，以便确保栅电极材料可以填充半导体主体的底切部分的下方，使得栅电极可以部分地或者完全地包围半导体主体620。栅电极材料630可以被沉积至200埃到3000埃之间的厚度。在实施例中，栅电极材料被沉积到足够形成这样的栅电极的厚度或者高度，所述栅电极具有半导体主体620高度609的至少三倍的高度。在本发明的实施例中，栅电极材料包括多晶硅。在本发明的另一个实施例中，栅电极材料包括多晶态的硅锗合金。在本发明的又一个实施例中，栅电极材料可以包括诸如钨、钽及其氮化物的金属膜。
接着，如图6D所示，硬掩模材料被沉积并被定义成图案化的硬掩模632，所述图案化的硬掩模632定义出将形成栅电极的位置。硬掩模材料可以由任何材料形成，其中所述的材料在随后将栅电极材料刻蚀成栅电极时，将不会被明显地刻蚀掉。在本发明的实施例中，硬掩模材料是被形成至20纳米到100纳米之间的厚度的氮化硅。可以利用标准的光刻和刻蚀技术将硬掩模材料形成为图案化的硬掩模634。图案化的硬掩模634被形成至这样的宽度，其中所述宽度是器件的栅电极长度所期望的。
接着，对齐硬掩模634刻蚀栅电极材料，以形成栅电极636。在本发明的实施例中，首先如图6E所示对齐硬掩模来各向异性地刻蚀栅电极，以形成一对横向相对的侧壁639和641。在本发明的实施例中，所述各向异性刻蚀被持续至刚好差不多所有没有被掩蔽的栅电极材料630被去除并且恰好在埋入绝缘层606露出之前为止。在本发明的另一个实施例中，所述各向异性刻蚀被持续至所有没有被掩蔽的栅电极材料630被去除并且露出埋入绝缘层606为止。在本发明的实施例中，利用适当的刻蚀来进行所述各向异性刻蚀，所述刻蚀在栅电极的侧壁639和641上形成钝化聚合物膜，以助于确保形成与硬掩模634对齐的垂直侧壁。可以使用任何合适的各向异性刻蚀技术和刻蚀剂，其可以各向异性地刻蚀栅电极材料，而不会明显地刻蚀硬掩模和半导体膜608。当半导体膜和栅电极由诸如硅的相同材料形成时，诸如氮化硅的硬掩模可以被用来将半导体膜图案化为主体，在栅极图案化刻蚀过程中留下的硬掩模用于保护(多个)半导体主体在栅极刻蚀过程中不被刻蚀。横向相对的侧壁639和641之间的距离定义出器件的栅极长度(Lg)。当硬掩模材料是氮化硅且栅电极材料是硅或者多晶硅时，可以对栅电极进行各向异性的刻蚀，并且可以通过使用HBr/Cl2/O2化学品的等离子刻蚀来形成钝化聚合物膜。
接着，如图6F所示，在各向异性刻蚀之后，将刻蚀换成各向同性刻蚀。各向同性刻蚀将栅电极材料从将半导体主体下方不形成栅电极的区域去除。很重要的是从半导体主体620的下方去除栅电极材料的不需要的部分，从而可以使源漏区域与栅电极短路的“纵梁(stringer)”不被留下。可以在各向异性刻蚀完全向下刻蚀至下面的绝缘层之后，或者可以在各向异性刻蚀几乎到达下面的绝缘层之后，进行被用来去除“纵梁”的各向同性刻蚀。栅电极上的聚合物侧壁钝化保护栅电极在各向同性刻蚀步骤过程中不被横向地刻蚀。虽然在栅电极的底部附近可能发生栅电极634的某种横向底切635，但是栅电极的钝化顶部应当保持其原来的外形。通过修改绝缘层底切的量以及向绝缘层中凹入的深度，可以控制底切的程度。刻蚀栅电极634，直至栅电极完全与被用于形成主体620和源漏区域焊盘的半导体膜608隔离为止。在本发明的实施例中，利用热磷酸湿法刻蚀来实施各向同性刻蚀。在本发明的实施例中，用于定义出硬掩模并因此定义出栅电极636的光刻工艺，利用了用于制造非平面晶体管的最小值的或者最小尺寸的光刻工艺。(就是说，在本发明的实施例中，栅电极636的栅极长度(Lg)具有由光刻术所限定的晶体管最小特征尺寸。)在本发明的实施例中，栅极长度小于或者等于30纳米，且理想的是小于或者等于20纳米。
接着，如图6G所示，晶体管的源极640和漏极642区域被形成在栅电极636相对两侧的半导体主体620中。如图6G所示，通过为形成区域640和642而将掺杂剂644置于栅电极630两侧639、641的半导体主体620之中，可以分别形成源漏区域640和642。如果使用了源漏极焊盘622和624，则它们也可以在此时被掺杂。对于PMOS三栅极晶体管，栅电极相对两侧的半导体鳍状物或者主体620被掺杂成P型导电性并被掺杂至1×1020原子/cm3至1×1021原子/cm3的浓度，以形成源漏区域。对于NMOS三栅极晶体管，栅电极相对两侧的半导体鳍状物或者主体620被n型导电性离子掺杂至1×1020原子/cm3至1×1021原子/cm3的浓度，以形成源漏区域。在本发明的实施例中，通过离子注入来掺杂主体。在本发明的实施例中，如图6G所示，离子注入发生在垂直方向上(即垂直于衬底600的方向)。当栅电极630是多晶硅栅电极时，其可以通过首先去除硬掩模634而在离子注入工艺过程中被掺杂。多晶硅栅电极630将起到掩模的作用，以防止离子注入步骤掺杂非平面晶体管的沟道区域648。沟道区域648是半导体主体620位于栅电极636下方或者被栅电极636所围绕的部分。如果栅电极636是金属电极，则可以使用电介质硬掩模634来防止离子注入工艺过程中的掺杂。在其他的实施例中，可以使用诸如固体源扩散之类的其他方法来掺杂半导体主体，以形成源漏极延伸。此时，就完成了对具有部分或者完全包围的栅电极的非平面晶体管的制造。
在本发明的实施例中，在形成源/漏区域或者源/漏延伸区域之前，可以在硅主体中形成“晕圈”区域。晕圈区域是形成在器件的沟道区域648中的掺杂区域，并且晕圈区域具有与器件的沟道区域的掺杂相同的导电性，但是具有比器件的沟道区域的掺杂稍高的掺杂浓度。晕圈区域可以通过利用大角度的离子注入技术，由栅电极下方的离子注入掺杂剂来形成。
此外，如果需要的话，图6G中所示的衬底可以被进一步处理，以形成附加的公知特征，例如重掺杂的源极/漏极接触区域、源漏区域和栅电极上的沉积硅、以及在源极/漏极接触区域和栅电极上形成硅化物。
图7A-7D图示了用于形成具有几乎包围或者完全包围的栅电极的非平面晶体管的替换栅极方法。当金属栅电极是所期望的时，使用替换栅极技术是理想的。替换栅极方法开始于如上述的减成法的图6A和6B所示出的相同的衬底和处理步骤。在将半导体膜图案化成半导体主体或者鳍状物620，并且形成了源漏极焊盘之后，电介质膜702被毯覆沉积在半导体主体和焊盘上方，并被毯覆沉积在埋入绝缘层606的暴露部分上方。绝缘层被形成为栅极高度所需的厚度。绝缘层702可以是诸如氮化硅或者二氧化硅之类的任何合适的绝缘层。电介质膜702由可以相对于半导体膜608进行选择性刻蚀的材料形成。此外，电介质膜理想地可以相对于下面的埋入绝缘层606被选择性刻蚀。当埋入绝缘层是二氧化硅并且半导体层608是硅时，绝缘层702可以是氮化硅。然后利用公知的光刻和刻蚀技术对毯覆沉积的绝缘膜702进行图案化，以在电介质膜702中形成开口或者沟槽704，所述开口或者沟槽704定义出将形成栅电极的位置。图案化的绝缘膜702形成定义掩模，用于通过镶嵌图案化方法(damascene patterningapproach)形成栅电极。利用任何合适的刻蚀剂来刻蚀电介质膜702，所述刻蚀剂可以各向异性地刻蚀电介质膜702而不会刻蚀半导体主体620。如图7A所示，刻蚀绝缘层702，直至暴露出下面的埋入绝缘层606以及半导体主体的将提供器件沟道区域的部分。开口704形成非平面晶体管的栅极长度(Lg)所需的宽度706。
接着，如图7B所示，从半导体主体620的下方刻蚀掉埋入绝缘层606以形成开口705，其中所述开口705底切半导体主体620的有效沟道区域。当形成具有几乎包围的栅电极的非平面晶体管时，绝缘层的底切刻蚀从半导体主体每一侧的下方去除绝缘层的一部分。在本发明的实施例中，底切刻蚀对半导体主体底切这样的量，即所述的量可以允许后续形成的栅电极至少包围半导体主体620的下角部并由此控制在所述角部中的电流。在本发明的实施例中，当形成具有几乎包围的栅电极的非平面晶体管时，底切刻蚀去除半导体主体620每一侧628和629下方的绝缘层的约1/3。当形成具有完全包围的栅电极的非平面器件时，埋入绝缘层的底切刻蚀被持续至半导体主体620的暴露部分(即沟道区域)下方的整个绝缘层被完全去除为止。可以使用任何公知的各向同性刻蚀，该各向同性刻蚀可以刻蚀埋入绝缘层而不会明显地刻蚀半导体主体。当埋入绝缘层是氧化硅并且半导体主体是硅时，可以利用包含缓冲的HF的湿法刻蚀，以形成底切开口705。此外，如图7B所示，底切刻蚀将轻微地底切图案化的绝缘层702，得到稍微更大的开口705以及沟槽704。
接着，如上所述，在半导体主体620的暴露部分(即沟道区域)上并围绕所述暴露部分形成栅极电介质层624。就是说，这样来形成栅极电介质层，即在半导体主体620的顶表面上、在半导体主体620的侧壁628和629上、以及在半导体主体的底侧631的暴露部分的下方或者下邻接所述暴露部分来形成。在完全包围的栅电极的情况下，栅极电介质层624被形成在沟道区域或者半导体主体的整个底侧631上。如上所述，栅极电介质层可以是任何合适的材料，并且应该利用诸如原子层沉积(ALD)或者化学气相沉积(CVD)之类的保形沉积工艺来形成，以确保在半导体主体620的底侧631上形成足够的栅极电介质层。
接着，栅电极材料被毯覆沉积在衬底上方，包括在电介质层702之上沉积，在半导体主体620上并围绕所述半导体主体620形成的栅极电介质上并围绕所述栅极电介质沉积，以及在绝缘层608上沉积。栅电极材料被沉积到足够完全填充开口705和706的厚度。栅电极材料可以是如上所述的用来形成栅电极的任何合适材料。在本发明的实施例中，栅电极材料是金属膜，例如但不限于是钨(W)、氮化钛(TiN)和硅化钴(CoSi2)。栅电极材料应由诸如化学气相沉积(CVD)或者原子层沉积(ALD)之类的沉积技术来形成，以形成保形膜，而使得整个沟槽开口706以及电介质掩模702和半导体主体620下方的底切区域705被填充。
接着，利用平坦化技术将多余的栅极材料从电介质层702的顶部去除，这样形成如图7C中所示的平坦化的顶表面。可以使用诸如化学机械抛光或者等离子体回蚀之类的任何公知的且合适的平坦化技术，来将多余的栅极材料从电介质膜702的顶部去除。
接着，如图7D所示，电介质膜702被去除。此时，可以如上所述的对半导体主体620的若干部分进行掺杂来形成源漏区域。这就利用替换栅极工艺完成了对具有部分或者完全包围的栅电极的非平面器件的制造。如果需要的话，此时可以添加公知的附加的特征，例如侧壁隔片、重掺杂的源极/漏极接触区域以及硅化物。
图8A-8G描述了形成具有包围或者完全包围的栅电极的非平面器件的方法，藉此，在形成了附加的特征之后使用了替换栅极工艺，其中所述附加的特征例如是尖端区域、隔片、附加的用于放射状源/漏区域的半导体和源/漏区域上的硅化物。
该工艺开始于如图6A和6B所示出的相同的衬底和处理步骤。如图8A所示，在将半导体膜608图案化以形成一个或者多个半导体主体620以及源极/漏极焊盘622和624之后，在硅主体620的顶表面和侧壁上形成牺牲栅极氧化层802和牺牲栅电极804。为了形成牺牲栅极电介质和电极，首先将牺牲栅极电介质层材料毯覆沉积在衬底上，包括沉积在绝缘层606的暴露表面上，沉积在半导体主体620以及半导体焊盘622和624的顶表面和侧壁上。接着，将牺牲栅电极材料毯覆沉积在衬底栅极电介质层上方。牺牲栅电极材料被沉积到后续形成用于非平面器件的栅电极的高度805所需的厚度。然后通过公知的技术，例如利用光刻和刻蚀，对牺牲栅电极材料和牺牲栅极电介质材料进行图案化，以形成如图8A中所示的牺牲栅电极804和牺牲栅极电介质802。牺牲栅电极和牺牲栅极电介质被图案化成相同的形状，并被图案化在相同的位置，其中后续形成的栅电极和栅极电介质将在所述位置处形成。在本发明的实施例中，牺牲栅电极材料由诸如氮化硅或者多晶硅之类的材料形成。
接着，如果需要的话，通过利用将用来形成源/漏区域的具有相同导电性类型的杂质，对牺牲栅电极804相对两侧的半导体主体620进行掺杂，可以形成尖端或者源极/漏极延伸。尖端区域可以通过任何公知的技术形成，例如通过离子注入来形成，其中如图8A所示，所述离子注入将掺杂剂806注入到半导体主体620中。牺牲栅极804防止半导体主体620的沟道区域在尖端形成步骤的过程中被掺杂。在本发明的实施例中，形成具有1×1019原子/cm3至1×1021原子/cm3之间的掺杂浓度的尖端区域。
接着，如果需要的话，如图8B所示，可以沿着牺牲栅电极804相对的两个侧壁形成电介质侧壁隔片808。侧壁隔片可以通过任何公知的技术来形成，例如通过将保形的侧壁隔片电介质毯覆沉积到衬底的上方，包括沉积在牺牲栅电极804的顶表面和侧壁，沉积在半导体主体620以及焊盘622和624的顶表面和侧壁上，并沉积到绝缘衬底602的暴露的表面上。电介质隔片材料被沉积到这样的厚度，即所述厚度近似等于隔片808所需的宽度。在本发明的实施例中，电介质隔片材料被沉积到20纳米至100纳米之间的厚度。隔片材料可以是氮化硅、氧化硅、氧氮化硅及其组合。然后对电介质隔片材料进行各向异性的回蚀，以将电介质隔片材料从所有的水平表面(例如，牺牲栅电极804的顶表面以及半导体主体620和绝缘层606的顶表面)去除，同时留下垂直表面(例如，牺牲栅电极804的侧壁)上的隔片材料，以形成如图8B所示的侧壁隔片808。通过使牺牲栅电极804的高度805充分地高于(例如3倍)半导体主体620的厚度或者高度，可以使用各向异性回蚀的“过刻蚀”来将隔片材料从半导体主体620以及焊盘622和624的侧壁上去除，同时留下足够的隔片材料，以在牺牲栅电极804的侧壁上提供隔片808。
接着，如图8C所示，可以将附加的硅810和/或硅化物812形成到半导体主体620以及焊盘622和624的暴露顶表面和侧壁上。可以利用选择性沉积工艺在半导体主体620的暴露表面上形成附加的硅。选择性硅沉积工艺将诸如外延硅之类的硅沉积到例如半导体主体620以及焊盘622和624的含硅区域，而不会将硅沉积到不含硅区域，例如牺牲栅电极804、电介质隔片808和绝缘层606。可以使用任何公知的选择性沉积工艺来提供附加的外延硅。在本发明的实施例中，50埃至500埃之间的附加外延硅倍选择性地沉积到半导体主体620和焊盘622和624上，以形成加高的源/漏区域。
接着，如果需要的话，可以在栅电极相对两侧的半导体主体(和附加的硅，如果使用了的话)以及焊盘622和624中形成高浓度源/漏区域。侧壁隔片808防止下面的在先形成的尖端区域和半导体主体620被高浓度源极/漏极注入物810掺杂。此外，同前面一样，牺牲栅电极804掩蔽沟道区域，以使其在高浓度源极/栅极的形成步骤的过程中不被掺杂。
此外，如果需要的话，如图8C所示，硅化物812可以被形成到半导体主体的暴露表面上，或者被形成到另外附加的硅膜上，其中所述硅化物812例如但不限于是硅化钴、硅化镍和硅化钛。通过自对准的或者“金属硅化”工艺，可以将硅化物形成到暴露的半导体主体的顶表面和侧表面上或者形成到附加的硅上。在自对准的或者“金属硅化”工艺中，难熔金属膜可以被毯覆沉积在包括硅区域和电介质区域的衬底上，其中所述难熔金属例如但不限于是钛、镍以及钴。然后，将衬底退火到这样的温度，即所述温度足够使毯覆沉积的金属层与含硅区域发生反应，以形成硅化物。诸如侧壁隔片808之类的区域以及绝缘层606将不与金属发生反应，并且金属在这些区域中将保持为未反应的金属。接着，可以使用选择性湿法刻蚀来去除未反应的金属，同时留下金属硅化物812。这样，如图8C所示，可以将硅化物仅仅选择性地形成到衬底的硅或者半导体区域上。
接着，如图8D所示，电介质层814被毯覆沉积到衬底上。电介质层被形成到足够完全覆盖包括牺牲栅电极804的衬底的厚度。电介质层814由这样的材料形成，即所述材料可以相对于牺牲栅极材料以及半导体主体620被选择性地刻蚀。就是说，电介质材料由这样的材料形成，藉此，可以将牺牲栅电极804去除，而不会明显地刻蚀掉电介质层814。在毯覆沉积电介质后，该电介质层被平坦化，例如进行化学机械平坦化，直至电介质膜的顶表面与牺牲栅电极平齐，并且牺牲栅电极的顶表面被暴露出来，如图8D所示。
接着，如图8E所示出的，牺牲栅极804和栅极电介质802被刻蚀掉，以在将形成栅电极的位置处形成开口816。如图8E所示出的，去除牺牲栅极808和牺牲栅极电介质层802，就暴露出了非平面器件的半导体主体620的沟道区域。去除牺牲栅电极在将形成栅电极的位置处形成了开口816。
接着，如图8F所示出的，对衬底进行底切刻蚀，以如上所述的形成底切开口818。如图8F所示的，底切刻蚀将绝缘层606的一部分从半导体主体620的沟道区域下方去除。为了形成完全包围的栅电极，可以使用底切刻蚀来将绝缘层606从半导体主体620的沟道下方完全去除，以暴露出半导体主体620沟道区域的整个底侧。或者，如上所述的，底切刻蚀可以从半导体主体620的沟道区域的每一侧下方仅仅去除绝缘层606的一部分，这样可以制造部分包围的栅电极。
接着，如图8G所示出的，在开口816和818中形成栅极电介质820和栅电极824。首先，将栅极电介质膜820毯覆沉积到衬底上。如上所述，栅极电介质材料覆盖半导体主体620的沟道区域的顶表面和侧壁，并覆盖半导体主体620的暴露下表面。栅极电介质材料通过诸如CVD或者ALD之类的保形工艺形成，以便确保在半导体主体620沟道区域的暴露底侧上形成栅极电介质材料。接着，栅极电极材料被毯覆沉积到栅极电介质上。栅电极材料可以是如上所述的任何公知的栅电极材料。然后对栅电极材料和栅极电介质进行化学机械平坦化，直至露出电介质层814的顶表面，如图8G所示。一旦栅电极材料和栅极电介质材料被向下抛光或者被从电介质材料814的顶部去除，栅电极824和栅极电介质层820就被形成了。如上所述，栅极电介质和栅电极部分包围或者完全包围半导体主体620的沟道区域。如图8G所示，电介质层814可以被留在非平面器件上，并成为用于将各种非平面器件电耦合在一起成为功能电路的“后端(backend)”或者层间电介质(ILD)及金属化系统的一部分。或者，此时电介质层814可以被去除，并用其他类型的用于“后端”的层间电介质来代替。这就完成了形成具有完全包围的或者部分包围的栅电极的非平面器件的方法。
这样，就描述了具有部分或者完全包围的栅电极的非平面器件及其制造方法。

Claims (29)

1.一种非平面半导体器件，包括：
半导体主体，所述半导体主体具有顶表面，所述顶表面与形成在绝缘衬底之上的底表面相对，其中所述半导体主体具有一对横向相对的侧壁；
栅极电介质，在所述半导体主体的所述顶表面上、在所述半导体主体的所述底表面上以及在所述半导体主体的所述横向相对的侧壁上形成所述栅极电介质；
栅电极，在所述半导体主体的所述顶表面上的所述栅极电介质上、与所述半导体主体的所述横向相对的侧壁上的所述栅极电介质邻接、以及在所述半导体主体的所述底表面上的所述栅极电介质的下方形成所述栅电极；和
一对源/漏区域，所述一对源/漏区域形成在所述栅电极的相对两侧的所述半导体主体中。
2.如权利要求1所述的半导体器件，其中，所述半导体主体是单晶硅膜。
3.如权利要求1所述的半导体器件，其中，所述半导体主体选自由锗、锗化硅、砷化镓、InSb、GaP、GaSb以及碳纳米管所组成的组。
4.如权利要求1所述的半导体器件，其中，所述栅电极包含选自由多晶硅、钨、钽、钛以及金属氮化物所组成的组中的材料。
5.如权利要求1所述的半导体器件，其中，所述绝缘衬底包含形成在单晶硅衬底上的氧化物膜。
6.如权利要求1所述的半导体器件，其中，所述半导体器件还包括至少一个附加的半导体主体，所述至少一个附加的半导体主体具有顶表面、底表面以及一对横向相对的侧壁，其中栅极电介质层被形成在所述至少一个其他的半导体主体的所述顶表面、所述底表面以及所述侧壁上，并且其中，在所述至少一个其他的半导体主体的所述顶表面上的所述栅极电介质上、与所述至少一个其他的半导体主体的所述横向相对的侧壁上的所述栅极电介质邻接、以及在所述至少一个其他的半导体主体的所述底表面上的所述栅极电介质的下方形成所述栅电极。
7.一种非平面半导体器件，包括：
半导体主体，所述半导体主体具有顶表面，所述顶表面与底表面相对，所述底表面具有形成在绝缘衬底上的一部分，所述半导体主体具有形成在所述绝缘衬底上方的横向相对的侧壁；
栅极电介质，在所述半导体主体的所述顶表面上、在所述半导体主体的所述横向相对的侧壁上、在所述半导体主体的所述底表面中不在所述绝缘衬底上的部分上形成所述栅极电介质；
栅电极，在所述半导体主体的所述顶表面上的所述栅极电介质上、与所述半导体主体的所述横向相对的侧壁上的所述栅极电介质邻接、以及在所述半导体主体的所述底表面上的所述栅极电介质的下方形成所述栅电极；和
一对源/漏区域，所述一对源/漏区域形成在所述栅电极的相对两侧的所述半导体主体中。
8.如权利要求7所述的半导体器件，其中，所述半导体主体是单晶硅膜。
9.如权利要求7所述的半导体器件，其中，所述半导体主体选自由锗、锗化硅、砷化镓、InSb、GaP、GaSb以及碳纳米管所组成的组。
10.如权利要求7所述的半导体器件，其中，所述栅电极包含选自由多晶硅、钨、钽、钛以及金属氮化物所组成的组中的材料。
11.如权利要求7所述的半导体器件，其中，所述绝缘衬底包含形成在单晶硅衬底上的氧化物膜。
12.如权利要求7所述的半导体器件，其中，所述半导体器件还包括至少一个附加的半导体主体，所述至少一个附加的半导体主体具有顶表面、底表面以及一对横向相对的侧壁，其中栅极电介质层被形成在所述至少一个其他的半导体主体的所述顶表面、所述底表面以及所述侧壁上，并且其中，在所述至少一个其他的半导体主体的所述顶表面上的所述栅极电介质上、与所述至少一个其他的半导体主体的所述横向相对的侧壁上的所述栅极电介质邻接、以及在所述至少一个其他的半导体主体的所述底表面上的所述栅极电介质的下方形成所述栅电极。
13.一种形成非平面半导体器件的方法，包括：
在绝缘衬底上方形成半导体主体，所述半导体主体具有一对横向相对的侧壁和与底表面相对的顶表面；
在所述半导体主体的所述顶表面上、在所述半导体主体的所述横向相对的侧壁上以及在所述半导体主体的所述底表面的至少一部分上形成栅极电介质；
在所述半导体主体的所述顶表面上的所述栅极电介质上、与所述半导体主体的所述横向相对的侧壁上的所述栅极电介质邻接、以及下邻接形成在所述半导体主体的所述底表面的至少一部分上的所述栅极电介质来形成栅电极；以及
在所述栅电极的相对两侧的所述半导体主体中形成一对源/漏区域。
14.如权利要求13所述的形成所述半导体器件的方法，其中，所述栅极电介质和所述栅电极被形成在所述半导体主体的整个沟道区域的下方。
15.如权利要求13所述的方法，其中，所述半导体主体的所述底表面的一部分被形成在所述绝缘衬底上，其中所述绝缘衬底上的所述部分位于处在所述半导体主体的所述顶表面上方的所述栅电极之下。
16.如权利要求13所述的方法，其中，所述半导体主体是单晶硅膜。
17.如权利要求13所述的方法，其中，所述半导体主体选自由锗、锗化硅、砷化镓、InSb、GaP、GaSb以及碳纳米管所组成的组。
18.如权利要求13所述的方法，其中，所述栅电极包含选自由多晶硅、钨、钽、钛以及金属氮化物所组成的组中的材料。
19.如权利要求13所述的方法，其中，所述绝缘衬底包含形成在单晶硅衬底上的氧化物膜。
20.如权利要求13所述的方法，还包括形成至少一个附加的半导体主体，所述至少一个附加的半导体主体具有顶表面、底表面以及一对横向相对的侧壁，并且在所述至少一个其他的半导体主体的所述顶表面、所述底表面以及所述侧壁上形成栅极电介质层，并且其中，在所述至少一个其他的半导体主体的所述顶表面上的所述栅极电介质上、与所述至少一个其他的半导体主体的所述横向相对的侧壁上的所述栅极电介质邻接、以及在所述至少一个其他的半导体主体的所述底表面上的所述栅极电介质的下方形成所述栅电极。
21.一种形成非平面晶体管的方法，包括：
在绝缘衬底上形成半导体主体，所述半导体主体具有一对横向相对的侧壁、顶表面以及底表面；
从所述半导体主体的下方去除所述绝缘衬底的一部分，以底切所述半导体主体并暴露出所述半导体主体的所述底表面的一部分；
在所述半导体主体的所述顶表面上、在所述半导体主体的所述侧壁上、以及在所述半导体主体的所述暴露底部上形成栅极电介质；
在所述半导体主体的上方并围绕所述半导体主体、以及在所述半导体主体的所述暴露部分的下方沉积栅极材料；
利用第一各向异性刻蚀并随后进行各向同性刻蚀，将栅电极材料刻蚀成栅电极，以形成栅电极，其中在所述半导体主体的所述顶表面上的所述栅极电介质之上、与形成在所述半导体主体的所述侧壁上的所述栅极电介质邻接、以及在形成在所述半导体主体的所述底表面的所述暴露部分上的所述栅极电介质的下方形成所述栅电极；以及
将掺杂剂置于所述栅电极的相对两侧的所述半导体主体中，以形成一对源/漏区域。
22.如权利要求21所述的方法，其中所述半导体主体由单晶硅形成。
23.如权利要求22所述的方法，其中所述绝缘衬底包含下部的单晶硅衬底和顶部的氧化硅。
24.一种形成非平面晶体管的方法，包括：
在绝缘衬底上形成半导体主体，所述半导体主体具有顶表面、底表面以及一对横向相对的侧壁；
在所述半导体主体上方并围绕所述半导体主体形成电介质膜，其中所述电介质膜具有开口，所述开口暴露出所述半导体主体的沟道区域；
去除所述绝缘衬底在所述开口中位于所述半导体主体下方的一部分，以暴露出所述半导体主体的所述底表面的至少一部分；
在所述开口中的所述半导体主体的所述顶表面上和所述侧壁上、以及在所述半导体主体的所述底表面的所述暴露部分上形成栅极电介质层；
在所述电介质膜的上方、在所述开口之中、以及在所述半导体主体的所述顶表面上的所述栅极电介质上、与所述半导体主体的所述侧壁上的所述栅极电介质邻接、以及在所述半导体主体的所述暴露部分上的所述栅极电介质的下方，毯覆沉积栅电极材料；
从所述电介质膜的所述顶表面去除所述栅电极材料，以形成栅电极；
去除所述电介质膜；以及
将掺杂剂置于所述电极的相对两侧的所述半导体主体中，以形成一对源/漏区域。
25.如权利要求24所述的方法，其中所述半导体主体由单晶硅形成。
26.如权利要求25所述的方法，其中所述绝缘衬底包含下部的单晶硅衬底和顶部的氧化硅绝缘膜。
27.一种形成非平面晶体管的方法，包括：
在绝缘衬底上形成半导体主体，所述半导体主体具有顶表面、底表面以及一对横向相对的侧壁；
在所述半导体主体的所述顶表面之上并且邻接所述半导体主体的所述横向相对侧壁形成牺牲栅电极，所述牺牲栅电极具有一对横向相对的侧壁；
将掺杂剂置于所述牺牲栅电极的相对两侧的所述半导体主体中，以在所述栅电极的相对两侧形成一对源极/漏极延伸；
沿着所述牺牲栅电极的横向相对的侧壁，形成一对侧壁隔片；
邻接所述侧壁隔片在所述半导体主体上形成硅；
对齐所述侧壁隔片将掺杂剂置于所述硅和所述半导体主体之中；
在邻接所述侧壁隔片而在所述半导体主体上所形成的硅上，形成硅化物；
在所述硅化物、所述牺牲栅极和所述侧壁隔片上形成电介质层；
对所述电介质层进行平坦化，直至所述电介质层的所述顶表面与所述牺牲栅电极的顶表面平齐，并且暴露出所述牺牲栅电极为止；
去除所述牺牲栅电极，以暴露出所述半导体主体的沟道区域和所述绝缘衬底；
去除所述绝缘衬底在所述开口中的位于所述半导体主体下方的一部分，以暴露出所述半导体主体的所述底表面的至少一部分；
在所述开口中的所述半导体主体的所述顶表面上和所述侧壁上、以及在所述半导体主体的所述暴露底表面的所述部分上形成栅极电介质层；
在所述栅极电介质层上、在所述开口之中、以及在所述半导体主体的所述顶表面上的所述栅极电介质层上、与所述半导体主体的所述侧壁上的所述栅极电介质邻接、以及在所述半导体主体所述底表面的所述暴露部分上的所述栅极电介质的下方，毯覆沉积栅电极材料；以及
从所述电介质膜的所述顶表面去除所述栅电极材料，以形成栅电极。
28.如权利要求27所述的方法，其中所述半导体主体由单晶硅形成。
29.如权利要求28所述的方法，其中所述绝缘衬底包含下部的单晶硅衬底和顶部的硅化物绝缘膜。
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Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7638398B2 (en) 2006-03-31 2009-12-29 Hynix Semiconductor Inc. Semiconductor device with increased channel area and fabrication method thereof
CN101047206B (zh) * 2006-03-31 2010-04-07 海力士半导体有限公司 具有增加的沟道面积的半导体器件及其制造方法
CN101228634B (zh) * 2005-07-27 2010-06-02 国际商业机器公司 虚拟体接触的三栅极及其制造方法
CN101556922B (zh) * 2008-04-10 2010-07-28 北京大学 一种纳米环栅mosfet晶体管及其制备方法
CN102244102A (zh) * 2011-06-28 2011-11-16 复旦大学 一种基于电子隧穿的围栅型栅控金属-绝缘体器件
CN102301482A (zh) * 2009-02-04 2011-12-28 国际商业机器公司 用于悬浮和细化纳米线的无掩模制程
CN102544010A (zh) * 2012-02-28 2012-07-04 上海华力微电子有限公司 双层隔离三维阵列式半导体纳米线mosfet
CN103022136A (zh) * 2012-12-26 2013-04-03 电子科技大学 一种t型栅结构的mos晶体管
CN103035708A (zh) * 2011-09-30 2013-04-10 中国科学院微电子研究所 一种半导体结构及其制造方法
CN103811320A (zh) * 2012-11-09 2014-05-21 中国科学院微电子研究所 半导体器件及其制造方法
CN103855091A (zh) * 2012-12-03 2014-06-11 国际商业机器公司 半导体结构及其形成方法
CN104246994A (zh) * 2012-04-17 2014-12-24 国际商业机器公司 具有鳍结构的半导体器件和形成具有鳍结构的半导体器件的方法
CN104465354A (zh) * 2014-12-24 2015-03-25 上海集成电路研发中心有限公司 全包围栅极结构及其制造方法
CN105023846A (zh) * 2014-04-15 2015-11-04 台湾积体电路制造股份有限公司 在金属栅极线端中具有t形的器件和制造半导体器件的方法
CN105390442A (zh) * 2014-08-28 2016-03-09 格罗方德半导体公司 于非平面输出晶体管的非平面静电放电装置及其共同制造
CN105405888A (zh) * 2014-09-11 2016-03-16 台湾积体电路制造股份有限公司 半导体结构及其制造方法
CN105789306A (zh) * 2015-01-12 2016-07-20 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN105845726A (zh) * 2015-01-14 2016-08-10 中国科学院微电子研究所 全包围栅场效应晶体管及其制造方法
CN105895695A (zh) * 2015-02-13 2016-08-24 台湾积体电路制造股份有限公司 具有延伸的栅极结构的半导体结构及其形成方法
CN106158878A (zh) * 2014-12-31 2016-11-23 意法半导体公司 制作增强utbb fdsoi器件的方法和结构
CN106711194A (zh) * 2016-12-28 2017-05-24 中国科学院微电子研究所 一种环栅场效应晶体管及其制备方法
CN107068756A (zh) * 2015-11-30 2017-08-18 格罗方德半导体公司 通过栅极自对准结改进结分布的替代体finfet
CN108074819A (zh) * 2017-12-18 2018-05-25 深圳市晶特智造科技有限公司 环栅型鳍式场效应晶体管及其制作方法
CN108109967A (zh) * 2013-04-04 2018-06-01 意法半导体公司 集成电路器件和制作技术
US10714581B2 (en) 2015-01-12 2020-07-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
WO2021098546A1 (zh) * 2019-11-19 2021-05-27 北京元芯碳基集成电路研究院 一种碳纳米管器件及其制造方法

Families Citing this family (387)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7473947B2 (en) * 2002-07-12 2009-01-06 Intel Corporation Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
FR2858876B1 (fr) * 2003-08-12 2006-03-03 St Microelectronics Sa Procede de formation sous une couche mince d'un premier materiau de portions d'un autre materiau et/ou de zones de vide
US6946377B2 (en) * 2003-10-29 2005-09-20 Texas Instruments Incorporated Multiple-gate MOSFET device with lithography independent silicon body thickness and methods for fabricating the same
US6962843B2 (en) * 2003-11-05 2005-11-08 International Business Machines Corporation Method of fabricating a finfet
KR100605497B1 (ko) * 2003-11-27 2006-07-28 삼성전자주식회사 에스오아이 기판들을 제조하는 방법들, 이를 사용하여반도체 소자들을 제조하는 방법들 및 그에 의해 제조된반도체 소자들
KR100598099B1 (ko) * 2004-02-24 2006-07-07 삼성전자주식회사 다마신 게이트를 갖는 수직 채널 핀 전계효과 트랜지스터 및 그 제조방법
KR100612415B1 (ko) * 2004-04-09 2006-08-16 삼성전자주식회사 올 어라운드된 채널 영역을 갖는 트랜지스터 및 그 제조방법
US7153784B2 (en) * 2004-04-20 2006-12-26 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
DE102005026228B4 (de) * 2004-06-08 2010-04-15 Samsung Electronics Co., Ltd., Suwon Transistor vom GAA-Typ und Verfahren zu dessen Herstellung
KR100541657B1 (ko) * 2004-06-29 2006-01-11 삼성전자주식회사 멀티 게이트 트랜지스터의 제조방법 및 이에 의해 제조된멀티 게이트 트랜지스터
US7098507B2 (en) * 2004-06-30 2006-08-29 Intel Corporation Floating-body dynamic random access memory and method of fabrication in tri-gate technology
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7598516B2 (en) * 2005-01-07 2009-10-06 International Business Machines Corporation Self-aligned process for nanotube/nanowire FETs
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) * 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7606499B2 (en) * 2005-08-01 2009-10-20 Massachusetts Institute Of Technology Bidirectional transceiver assembly for POF application
US7348642B2 (en) * 2005-08-03 2008-03-25 International Business Machines Corporation Fin-type field effect transistor
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
KR100707208B1 (ko) * 2005-12-24 2007-04-13 삼성전자주식회사 Ｇａａ 구조의 핀-펫 및 그 제조 방법
FR2895835B1 (fr) 2005-12-30 2008-05-09 Commissariat Energie Atomique Realisation sur une structure de canal a plusieurs branches d'une grille de transistor et de moyens pour isoler cette grille des regions de source et de drain
KR100718149B1 (ko) * 2006-02-07 2007-05-14 삼성전자주식회사 게이트-올-어라운드 구조의 반도체 소자
JP2007299991A (ja) * 2006-05-01 2007-11-15 Toshiba Corp 半導体装置及びその製造方法
US7422960B2 (en) 2006-05-17 2008-09-09 Micron Technology, Inc. Method of forming gate arrays on a partial SOI substrate
KR100718159B1 (ko) * 2006-05-18 2007-05-14 삼성전자주식회사 와이어-타입 반도체 소자 및 그 제조 방법
US20080014689A1 (en) * 2006-07-07 2008-01-17 Texas Instruments Incorporated Method for making planar nanowire surround gate mosfet
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US7537994B2 (en) 2006-08-28 2009-05-26 Micron Technology, Inc. Methods of forming semiconductor devices, assemblies and constructions
US20080090348A1 (en) * 2006-09-28 2008-04-17 Chang Peter L D Gate-assisted silicon-on-insulator on bulk wafer and its application to floating body cell memory and transistors
US8389976B2 (en) * 2006-12-29 2013-03-05 Intel Corporation Methods of forming carbon nanotube transistors for high speed circuit operation and structures formed thereby
US7772048B2 (en) * 2007-02-23 2010-08-10 Freescale Semiconductor, Inc. Forming semiconductor fins using a sacrificial fin
US7435636B1 (en) * 2007-03-29 2008-10-14 Micron Technology, Inc. Fabrication of self-aligned gallium arsenide MOSFETs using damascene gate methods
US7821061B2 (en) * 2007-03-29 2010-10-26 Intel Corporation Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications
US7935599B2 (en) * 2007-04-04 2011-05-03 Sharp Laboratories Of America, Inc. Nanowire transistor and method for forming same
US9299568B2 (en) 2007-05-25 2016-03-29 Cypress Semiconductor Corporation SONOS ONO stack scaling
US7960243B2 (en) * 2007-05-31 2011-06-14 Freescale Semiconductor, Inc. Method of forming a semiconductor device featuring a gate stressor and semiconductor device
WO2009028235A1 (ja) * 2007-08-24 2009-03-05 Sharp Kabushiki Kaisha 回路基板及び表示装置
KR101263648B1 (ko) * 2007-08-31 2013-05-21 삼성전자주식회사 핀 전계 효과 트랜지스터 및 그 제조 방법.
TW200913162A (en) * 2007-09-11 2009-03-16 Univ Nat Chiao Tung Nonvolatile memory device with nanowire channel and a method for fabricating the same
WO2009036273A2 (en) * 2007-09-12 2009-03-19 Arizona Board Of Regents For And On Behalf Of Arizona State University Horizontally depleted metal semiconductor field effect transistor
FR2921757B1 (fr) 2007-09-28 2009-12-18 Commissariat Energie Atomique Structure de transistor double-grille dotee d'un canal a plusieurs branches.
US7781825B2 (en) * 2007-10-18 2010-08-24 Macronix International Co., Ltd. Semiconductor device and method for manufacturing the same
US9431549B2 (en) 2007-12-12 2016-08-30 Cypress Semiconductor Corporation Nonvolatile charge trap memory device having a high dielectric constant blocking region
US8030163B2 (en) * 2007-12-26 2011-10-04 Intel Corporation Reducing external resistance of a multi-gate device using spacer processing techniques
US7982269B2 (en) * 2008-04-17 2011-07-19 International Business Machines Corporation Transistors having asymmetric strained source/drain portions
WO2009130629A1 (en) * 2008-04-23 2009-10-29 Nxp B.V. A fin fet and a method of manufacturing a fin fet
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US20100019322A1 (en) * 2008-07-23 2010-01-28 International Business Machines Corporation Semiconductor device and method of manufacturing
JP2010040630A (ja) * 2008-08-01 2010-02-18 Toshiba Corp 半導体装置
JP5391688B2 (ja) * 2008-12-26 2014-01-15 富士通セミコンダクター株式会社 半導体装置の製造方法と半導体装置
US8305829B2 (en) 2009-02-23 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Memory power gating circuit for controlling internal voltage of a memory array, system and method for controlling the same
US8305790B2 (en) 2009-03-16 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical anti-fuse and related applications
US8629506B2 (en) * 2009-03-19 2014-01-14 International Business Machines Corporation Replacement gate CMOS
JP2010225768A (ja) * 2009-03-23 2010-10-07 Toshiba Corp 半導体装置
US8957482B2 (en) 2009-03-31 2015-02-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical fuse and related applications
US8427200B2 (en) 2009-04-14 2013-04-23 Monolithic 3D Inc. 3D semiconductor device
US8912602B2 (en) 2009-04-14 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US9577642B2 (en) 2009-04-14 2017-02-21 Monolithic 3D Inc. Method to form a 3D semiconductor device
US20110199116A1 (en) * 2010-02-16 2011-08-18 NuPGA Corporation Method for fabrication of a semiconductor device and structure
US20110031997A1 (en) * 2009-04-14 2011-02-10 NuPGA Corporation Method for fabrication of a semiconductor device and structure
US8405420B2 (en) 2009-04-14 2013-03-26 Monolithic 3D Inc. System comprising a semiconductor device and structure
US9711407B2 (en) 2009-04-14 2017-07-18 Monolithic 3D Inc. Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer
US8395191B2 (en) 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure
US8378715B2 (en) 2009-04-14 2013-02-19 Monolithic 3D Inc. Method to construct systems
US8373439B2 (en) 2009-04-14 2013-02-12 Monolithic 3D Inc. 3D semiconductor device
US8058137B1 (en) 2009-04-14 2011-11-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8362800B2 (en) 2010-10-13 2013-01-29 Monolithic 3D Inc. 3D semiconductor device including field repairable logics
US8669778B1 (en) 2009-04-14 2014-03-11 Monolithic 3D Inc. Method for design and manufacturing of a 3D semiconductor device
US8384426B2 (en) * 2009-04-14 2013-02-26 Monolithic 3D Inc. Semiconductor device and structure
US7986042B2 (en) 2009-04-14 2011-07-26 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8754533B2 (en) 2009-04-14 2014-06-17 Monolithic 3D Inc. Monolithic three-dimensional semiconductor device and structure
US8362482B2 (en) 2009-04-14 2013-01-29 Monolithic 3D Inc. Semiconductor device and structure
US9509313B2 (en) 2009-04-14 2016-11-29 Monolithic 3D Inc. 3D semiconductor device
US8461015B2 (en) 2009-07-08 2013-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. STI structure and method of forming bottom void in same
KR100956798B1 (ko) 2009-07-14 2010-05-11 국민대학교산학협력단 다중 비트 저장이 가능한 비휘발성 메모리 셀 제조 방법 및 이를 이용한 노어 타입 메모리 아키텍처
US8440517B2 (en) 2010-10-13 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US8629478B2 (en) 2009-07-31 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure for high mobility multiple-gate transistor
US8759943B2 (en) 2010-10-08 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor having notched fin structure and method of making the same
US8482073B2 (en) * 2010-03-25 2013-07-09 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including FINFETs and methods for forming the same
US8264032B2 (en) * 2009-09-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Accumulation type FinFET, circuits and fabrication method thereof
US8980719B2 (en) 2010-04-28 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for doping fin field-effect transistors
US8264021B2 (en) 2009-10-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets and methods for forming the same
US8472227B2 (en) 2010-01-27 2013-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits and methods for forming the same
US8623728B2 (en) 2009-07-28 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high germanium concentration SiGe stressor
US8497528B2 (en) 2010-05-06 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a strained structure
US9484462B2 (en) 2009-09-24 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of fin field effect transistor
US8298925B2 (en) 2010-11-08 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming ultra shallow junction
US8536023B2 (en) 2010-11-22 2013-09-17 Monolithic 3D Inc. Method of manufacturing a semiconductor device and structure
US9099424B1 (en) 2012-08-10 2015-08-04 Monolithic 3D Inc. Semiconductor system, device and structure with heat removal
US10354995B2 (en) 2009-10-12 2019-07-16 Monolithic 3D Inc. Semiconductor memory device and structure
US11018133B2 (en) 2009-10-12 2021-05-25 Monolithic 3D Inc. 3D integrated circuit
US10388863B2 (en) 2009-10-12 2019-08-20 Monolithic 3D Inc. 3D memory device and structure
US8581349B1 (en) 2011-05-02 2013-11-12 Monolithic 3D Inc. 3D memory semiconductor device and structure
US10043781B2 (en) 2009-10-12 2018-08-07 Monolithic 3D Inc. 3D semiconductor device and structure
US10366970B2 (en) 2009-10-12 2019-07-30 Monolithic 3D Inc. 3D semiconductor device and structure
US10157909B2 (en) 2009-10-12 2018-12-18 Monolithic 3D Inc. 3D semiconductor device and structure
US8742476B1 (en) 2012-11-27 2014-06-03 Monolithic 3D Inc. Semiconductor device and structure
US10910364B2 (en) 2009-10-12 2021-02-02 Monolitaic 3D Inc. 3D semiconductor device
US8294159B2 (en) 2009-10-12 2012-10-23 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US11374118B2 (en) 2009-10-12 2022-06-28 Monolithic 3D Inc. Method to form a 3D integrated circuit
US8450804B2 (en) 2011-03-06 2013-05-28 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US8476145B2 (en) 2010-10-13 2013-07-02 Monolithic 3D Inc. Method of fabricating a semiconductor device and structure
US8384065B2 (en) * 2009-12-04 2013-02-26 International Business Machines Corporation Gate-all-around nanowire field effect transistors
US8129247B2 (en) * 2009-12-04 2012-03-06 International Business Machines Corporation Omega shaped nanowire field effect transistors
US8143113B2 (en) 2009-12-04 2012-03-27 International Business Machines Corporation Omega shaped nanowire tunnel field effect transistors fabrication
US8309991B2 (en) * 2009-12-04 2012-11-13 International Business Machines Corporation Nanowire FET having induced radial strain
US8455334B2 (en) * 2009-12-04 2013-06-04 International Business Machines Corporation Planar and nanowire field effect transistors
US8097515B2 (en) * 2009-12-04 2012-01-17 International Business Machines Corporation Self-aligned contacts for nanowire field effect transistors
US8173993B2 (en) * 2009-12-04 2012-05-08 International Business Machines Corporation Gate-all-around nanowire tunnel field effect transistors
US8313990B2 (en) * 2009-12-04 2012-11-20 International Business Machines Corporation Nanowire FET having induced radial strain
CN102104069B (zh) * 2009-12-16 2012-11-21 中国科学院微电子研究所 鳍式晶体管结构及其制作方法
CN102117829B (zh) * 2009-12-30 2012-11-21 中国科学院微电子研究所 鳍式晶体管结构及其制作方法
US8722492B2 (en) * 2010-01-08 2014-05-13 International Business Machines Corporation Nanowire pin tunnel field effect devices
US9040393B2 (en) 2010-01-14 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor structure
US8492886B2 (en) 2010-02-16 2013-07-23 Monolithic 3D Inc 3D integrated circuit with logic
US8026521B1 (en) 2010-10-11 2011-09-27 Monolithic 3D Inc. Semiconductor device and structure
US8461035B1 (en) 2010-09-30 2013-06-11 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8541819B1 (en) 2010-12-09 2013-09-24 Monolithic 3D Inc. Semiconductor device and structure
US8373230B1 (en) 2010-10-13 2013-02-12 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9099526B2 (en) 2010-02-16 2015-08-04 Monolithic 3D Inc. Integrated circuit device and structure
US8324940B2 (en) 2010-04-13 2012-12-04 International Business Machines Corporation Nanowire circuits in matched devices
US8361907B2 (en) 2010-05-10 2013-01-29 International Business Machines Corporation Directionally etched nanowire field effect transistors
US8324030B2 (en) 2010-05-12 2012-12-04 International Business Machines Corporation Nanowire tunnel field effect transistors
US9029834B2 (en) * 2010-07-06 2015-05-12 International Business Machines Corporation Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric
US8642416B2 (en) 2010-07-30 2014-02-04 Monolithic 3D Inc. Method of forming three dimensional integrated circuit devices using layer transfer technique
US8901613B2 (en) 2011-03-06 2014-12-02 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US9953925B2 (en) 2011-06-28 2018-04-24 Monolithic 3D Inc. Semiconductor system and device
US9219005B2 (en) 2011-06-28 2015-12-22 Monolithic 3D Inc. Semiconductor system and device
US10217667B2 (en) 2011-06-28 2019-02-26 Monolithic 3D Inc. 3D semiconductor device, fabrication method and system
US8835231B2 (en) 2010-08-16 2014-09-16 International Business Machines Corporation Methods of forming contacts for nanowire field effect transistors
US8268689B2 (en) * 2010-08-23 2012-09-18 International Business Machines Corporation Multiple threshold voltages in field effect transistor devices
US8536563B2 (en) 2010-09-17 2013-09-17 International Business Machines Corporation Nanowire field effect transistors
US11482440B2 (en) 2010-12-16 2022-10-25 Monolithic 3D Inc. 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits
US8163581B1 (en) 2010-10-13 2012-04-24 Monolith IC 3D Semiconductor and optoelectronic devices
US8273610B2 (en) 2010-11-18 2012-09-25 Monolithic 3D Inc. Method of constructing a semiconductor device and structure
US10497713B2 (en) 2010-11-18 2019-12-03 Monolithic 3D Inc. 3D semiconductor memory device and structure
US8114757B1 (en) 2010-10-11 2012-02-14 Monolithic 3D Inc. Semiconductor device and structure
US11024673B1 (en) 2010-10-11 2021-06-01 Monolithic 3D Inc. 3D semiconductor device and structure
US11469271B2 (en) 2010-10-11 2022-10-11 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11227897B2 (en) 2010-10-11 2022-01-18 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US10290682B2 (en) 2010-10-11 2019-05-14 Monolithic 3D Inc. 3D IC semiconductor device and structure with stacked memory
US11600667B1 (en) 2010-10-11 2023-03-07 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11018191B1 (en) 2010-10-11 2021-05-25 Monolithic 3D Inc. 3D semiconductor device and structure
US10896931B1 (en) 2010-10-11 2021-01-19 Monolithic 3D Inc. 3D semiconductor device and structure
US11257867B1 (en) 2010-10-11 2022-02-22 Monolithic 3D Inc. 3D semiconductor device and structure with oxide bonds
US11315980B1 (en) 2010-10-11 2022-04-26 Monolithic 3D Inc. 3D semiconductor device and structure with transistors
US11158674B2 (en) 2010-10-11 2021-10-26 Monolithic 3D Inc. Method to produce a 3D semiconductor device and structure
US11063071B1 (en) 2010-10-13 2021-07-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11855100B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US10978501B1 (en) 2010-10-13 2021-04-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US10833108B2 (en) 2010-10-13 2020-11-10 Monolithic 3D Inc. 3D microdisplay device and structure
US11164898B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11327227B2 (en) 2010-10-13 2022-05-10 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US11404466B2 (en) 2010-10-13 2022-08-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11437368B2 (en) 2010-10-13 2022-09-06 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US9197804B1 (en) 2011-10-14 2015-11-24 Monolithic 3D Inc. Semiconductor and optoelectronic devices
US10998374B1 (en) 2010-10-13 2021-05-04 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11605663B2 (en) 2010-10-13 2023-03-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11043523B1 (en) 2010-10-13 2021-06-22 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11163112B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US10943934B2 (en) 2010-10-13 2021-03-09 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11694922B2 (en) 2010-10-13 2023-07-04 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US10679977B2 (en) 2010-10-13 2020-06-09 Monolithic 3D Inc. 3D microdisplay device and structure
US11929372B2 (en) 2010-10-13 2024-03-12 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US8379458B1 (en) 2010-10-13 2013-02-19 Monolithic 3D Inc. Semiconductor device and structure
US11869915B2 (en) 2010-10-13 2024-01-09 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11855114B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11133344B2 (en) 2010-10-13 2021-09-28 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US8603924B2 (en) 2010-10-19 2013-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming gate dielectric material
US8524546B2 (en) 2010-10-22 2013-09-03 International Business Machines Corporation Formation of multi-height MUGFET
US8524545B2 (en) 2010-10-22 2013-09-03 International Business Machines Corporation Simultaneous formation of FinFET and MUGFET
US8232164B2 (en) 2010-10-29 2012-07-31 International Business Machines Corporation Damascene method of forming a semiconductor structure and a semiconductor structure with multiple fin-shaped channel regions having different widths
US9048181B2 (en) 2010-11-08 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming ultra shallow junction
US8769446B2 (en) 2010-11-12 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method and device for increasing fin device density for unaligned fins
US11610802B2 (en) 2010-11-18 2023-03-21 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes
US11355380B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. Methods for producing 3D semiconductor memory device and structure utilizing alignment marks
US11443971B2 (en) 2010-11-18 2022-09-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11862503B2 (en) 2010-11-18 2024-01-02 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11355381B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11482438B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11018042B1 (en) 2010-11-18 2021-05-25 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11521888B2 (en) 2010-11-18 2022-12-06 Monolithic 3D Inc. 3D semiconductor device and structure with high-k metal gate transistors
US11615977B2 (en) 2010-11-18 2023-03-28 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11495484B2 (en) 2010-11-18 2022-11-08 Monolithic 3D Inc. 3D semiconductor devices and structures with at least two single-crystal layers
US11569117B2 (en) 2010-11-18 2023-01-31 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11107721B2 (en) 2010-11-18 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure with NAND logic
US11121021B2 (en) 2010-11-18 2021-09-14 Monolithic 3D Inc. 3D semiconductor device and structure
US11735462B2 (en) 2010-11-18 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11804396B2 (en) 2010-11-18 2023-10-31 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11854857B1 (en) 2010-11-18 2023-12-26 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11508605B2 (en) 2010-11-18 2022-11-22 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11164770B1 (en) 2010-11-18 2021-11-02 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11482439B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors
US11004719B1 (en) 2010-11-18 2021-05-11 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11211279B2 (en) 2010-11-18 2021-12-28 Monolithic 3D Inc. Method for processing a 3D integrated circuit and structure
US11923230B1 (en) 2010-11-18 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11094576B1 (en) 2010-11-18 2021-08-17 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11784082B2 (en) 2010-11-18 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11901210B2 (en) 2010-11-18 2024-02-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11031275B2 (en) 2010-11-18 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US8633082B2 (en) * 2010-11-23 2014-01-21 International Business Machines Corporation Method for fabricating high-gain MOSFETs with asymmetric source/drain doping for analog and RF applications
DE102010064283B4 (de) * 2010-12-28 2012-12-27 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Verfahren zur Herstellung eines selbstjustierten Steg-Transistors auf einem Vollsubstrat durch eine späte Stegätzung
US8592915B2 (en) 2011-01-25 2013-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Doped oxide for shallow trench isolation (STI)
US8877602B2 (en) 2011-01-25 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms of doping oxide for forming shallow trench isolation
US8975670B2 (en) 2011-03-06 2015-03-10 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US8649209B1 (en) * 2011-03-25 2014-02-11 Altera Corporation Memory element circuitry with reduced oxide definition width
US8431453B2 (en) 2011-03-31 2013-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure
US8853790B2 (en) * 2011-04-05 2014-10-07 International Business Machines Corporation Semiconductor nanowire structure reusing suspension pads
US9041099B2 (en) * 2011-04-11 2015-05-26 Nanya Technology Corp. Single-sided access device and fabrication method thereof
JP5325932B2 (ja) * 2011-05-27 2013-10-23 株式会社東芝 半導体装置およびその製造方法
US10388568B2 (en) 2011-06-28 2019-08-20 Monolithic 3D Inc. 3D semiconductor device and system
CN102956457B (zh) * 2011-08-22 2015-08-12 中国科学院微电子研究所 半导体器件结构及其制作方法、及半导体鳍制作方法
US8969154B2 (en) * 2011-08-23 2015-03-03 Micron Technology, Inc. Methods for fabricating semiconductor device structures and arrays of vertical transistor devices
US8687399B2 (en) 2011-10-02 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
US8723272B2 (en) * 2011-10-04 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
US9029173B2 (en) 2011-10-18 2015-05-12 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8575013B2 (en) * 2011-10-25 2013-11-05 GlobalFoundries, Inc. Replacement gate fabrication methods
KR101926356B1 (ko) 2011-12-06 2018-12-07 삼성전자주식회사 백-바이어스 영역을 갖는 반도체 소자
CN104137265B (zh) 2011-12-22 2017-11-17 英特尔公司 具有颈状半导体主体的半导体器件以及形成不同宽度的半导体主体的方法
US9281378B2 (en) * 2012-01-24 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Fin recess last process for FinFET fabrication
US9171925B2 (en) 2012-01-24 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate devices with replaced-channels and methods for forming the same
US20130193513A1 (en) * 2012-02-01 2013-08-01 International Business Machines Corporation Multi-Gate Field Effect Transistor with a Tapered Gate Profile
US8809178B2 (en) * 2012-02-29 2014-08-19 Globalfoundries Inc. Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currents
US9000557B2 (en) 2012-03-17 2015-04-07 Zvi Or-Bach Semiconductor device and structure
US10600888B2 (en) 2012-04-09 2020-03-24 Monolithic 3D Inc. 3D semiconductor device
US11476181B1 (en) 2012-04-09 2022-10-18 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11735501B1 (en) 2012-04-09 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11616004B1 (en) 2012-04-09 2023-03-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11694944B1 (en) 2012-04-09 2023-07-04 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11410912B2 (en) 2012-04-09 2022-08-09 Monolithic 3D Inc. 3D semiconductor device with vias and isolation layers
US11164811B2 (en) 2012-04-09 2021-11-02 Monolithic 3D Inc. 3D semiconductor device with isolation layers and oxide-to-oxide bonding
US11594473B2 (en) 2012-04-09 2023-02-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11881443B2 (en) 2012-04-09 2024-01-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11088050B2 (en) 2012-04-09 2021-08-10 Monolithic 3D Inc. 3D semiconductor device with isolation layers
US8557632B1 (en) 2012-04-09 2013-10-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
KR20130126036A (ko) * 2012-05-10 2013-11-20 삼성전자주식회사 트랜지스터를 구비한 반도체 소자
US9024355B2 (en) * 2012-05-30 2015-05-05 International Business Machines Corporation Embedded planar source/drain stressors for a finFET including a plurality of fins
US20130320422A1 (en) * 2012-05-31 2013-12-05 International Business Machines Corporation Finfet contacting a conductive strap structure of a dram
US9385131B2 (en) 2012-05-31 2016-07-05 Globalfoundries Inc. Wrap-around fin for contacting a capacitor strap of a DRAM
US8809131B2 (en) * 2012-07-17 2014-08-19 International Business Machines Corporation Replacement gate fin first wire last gate all around devices
US9041106B2 (en) * 2012-09-27 2015-05-26 Intel Corporation Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates
US8716751B2 (en) 2012-09-28 2014-05-06 Intel Corporation Methods of containing defects for non-silicon device engineering
US9093376B2 (en) 2012-10-24 2015-07-28 International Business Machines Corporation Replacement metal gate FinFET
US9443962B2 (en) 2012-11-09 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Recessing STI to increase fin height in fin-first process
US8574929B1 (en) 2012-11-16 2013-11-05 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US8686428B1 (en) 2012-11-16 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
CN103824775B (zh) * 2012-11-16 2018-04-24 中国科学院微电子研究所 FinFET及其制造方法
US8822320B2 (en) 2012-11-20 2014-09-02 International Business Machines Corporation Dense finFET SRAM
US8759874B1 (en) 2012-11-30 2014-06-24 Stmicroelectronics, Inc. FinFET device with isolated channel
US8956942B2 (en) 2012-12-21 2015-02-17 Stmicroelectronics, Inc. Method of forming a fully substrate-isolated FinFET transistor
US11784169B2 (en) 2012-12-22 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11309292B2 (en) 2012-12-22 2022-04-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11018116B2 (en) 2012-12-22 2021-05-25 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11217565B2 (en) 2012-12-22 2022-01-04 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US8674470B1 (en) 2012-12-22 2014-03-18 Monolithic 3D Inc. Semiconductor device and structure
US11063024B1 (en) 2012-12-22 2021-07-13 Monlithic 3D Inc. Method to form a 3D semiconductor device and structure
US11916045B2 (en) 2012-12-22 2024-02-27 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US9224849B2 (en) * 2012-12-28 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Transistors with wrapped-around gates and methods for forming the same
US11087995B1 (en) 2012-12-29 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US11430668B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US10115663B2 (en) 2012-12-29 2018-10-30 Monolithic 3D Inc. 3D semiconductor device and structure
US10651054B2 (en) 2012-12-29 2020-05-12 Monolithic 3D Inc. 3D semiconductor device and structure
US11430667B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US9385058B1 (en) 2012-12-29 2016-07-05 Monolithic 3D Inc. Semiconductor device and structure
US10903089B1 (en) 2012-12-29 2021-01-26 Monolithic 3D Inc. 3D semiconductor device and structure
US10892169B2 (en) 2012-12-29 2021-01-12 Monolithic 3D Inc. 3D semiconductor device and structure
US11004694B1 (en) 2012-12-29 2021-05-11 Monolithic 3D Inc. 3D semiconductor device and structure
US9871034B1 (en) 2012-12-29 2018-01-16 Monolithic 3D Inc. Semiconductor device and structure
US10600657B2 (en) 2012-12-29 2020-03-24 Monolithic 3D Inc 3D semiconductor device and structure
US11177140B2 (en) 2012-12-29 2021-11-16 Monolithic 3D Inc. 3D semiconductor device and structure
US8802512B2 (en) 2013-01-11 2014-08-12 International Business Machines Corporation Overlap capacitance nanowire
US9076813B1 (en) * 2013-01-15 2015-07-07 Stc.Unm Gate-all-around metal-oxide-semiconductor transistors with gate oxides
US20140231914A1 (en) * 2013-02-19 2014-08-21 Applied Materials, Inc. Fin field effect transistor fabricated with hollow replacement channel
US8906759B2 (en) * 2013-02-25 2014-12-09 International Business Machines Corporation Silicon nitride gate encapsulation by implantation
CN104008974A (zh) * 2013-02-26 2014-08-27 中国科学院微电子研究所 半导体器件及其制造方法
US10325651B2 (en) 2013-03-11 2019-06-18 Monolithic 3D Inc. 3D semiconductor device with stacked memory
US9006045B2 (en) * 2013-03-11 2015-04-14 Globalfoundries Inc. Transistor including a gate electrode extending all around one or more channel regions
US11935949B1 (en) 2013-03-11 2024-03-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US11869965B2 (en) 2013-03-11 2024-01-09 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US8902663B1 (en) 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state
US8994404B1 (en) 2013-03-12 2015-03-31 Monolithic 3D Inc. Semiconductor device and structure
US11923374B2 (en) 2013-03-12 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US10840239B2 (en) 2014-08-26 2020-11-17 Monolithic 3D Inc. 3D semiconductor device and structure
US11088130B2 (en) 2014-01-28 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US11398569B2 (en) 2013-03-12 2022-07-26 Monolithic 3D Inc. 3D semiconductor device and structure
WO2014142950A1 (en) 2013-03-15 2014-09-18 Intel Corporation Nanowire transistor fabrication with hardmask layers
US9117749B1 (en) 2013-03-15 2015-08-25 Monolithic 3D Inc. Semiconductor device and structure
US10224279B2 (en) 2013-03-15 2019-03-05 Monolithic 3D Inc. Semiconductor device and structure
US8859379B2 (en) 2013-03-15 2014-10-14 International Business Machines Corporation Stress enhanced finFET devices
US20140264490A1 (en) * 2013-03-18 2014-09-18 International Business Machines Corporation Replacement gate electrode with a self-aligned dielectric spacer
US10438856B2 (en) 2013-04-03 2019-10-08 Stmicroelectronics, Inc. Methods and devices for enhancing mobility of charge carriers
US11574109B1 (en) 2013-04-15 2023-02-07 Monolithic 3D Inc Automation methods for 3D integrated circuits and devices
US11720736B2 (en) 2013-04-15 2023-08-08 Monolithic 3D Inc. Automation methods for 3D integrated circuits and devices
US11341309B1 (en) 2013-04-15 2022-05-24 Monolithic 3D Inc. Automation for monolithic 3D devices
US11030371B2 (en) 2013-04-15 2021-06-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11270055B1 (en) 2013-04-15 2022-03-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US9021414B1 (en) 2013-04-15 2015-04-28 Monolithic 3D Inc. Automation for monolithic 3D devices
US11487928B2 (en) 2013-04-15 2022-11-01 Monolithic 3D Inc. Automation for monolithic 3D devices
US9006842B2 (en) 2013-05-30 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Tuning strain in semiconductor devices
US9349850B2 (en) 2013-07-17 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally tuning strain in semiconductor devices
US9263455B2 (en) 2013-07-23 2016-02-16 Micron Technology, Inc. Methods of forming an array of conductive lines and methods of forming an array of recessed access gate lines
TWI632688B (zh) * 2013-07-25 2018-08-11 半導體能源研究所股份有限公司 半導體裝置以及半導體裝置的製造方法
US9349863B2 (en) * 2013-08-07 2016-05-24 Globalfoundries Inc. Anchored stress-generating active semiconductor regions for semiconductor-on-insulator finfet
US9219153B2 (en) * 2013-08-21 2015-12-22 Globalfoundries Inc. Methods of forming gate structures for FinFET devices and the resulting semiconductor products
CN104576383B (zh) * 2013-10-14 2017-09-12 中国科学院微电子研究所 一种FinFET结构及其制造方法
CN104576381B (zh) * 2013-10-14 2018-01-09 中国科学院微电子研究所 一种非对称超薄soimos晶体管结构及其制造方法
EP2866264A1 (en) 2013-10-22 2015-04-29 IMEC vzw Method for manufacturing a field effect transistor of a non-planar type
US9257641B2 (en) 2013-11-08 2016-02-09 Industrial Technology Research Institute Via structure, memory array structure, three-dimensional resistance memory and method of forming the same
US9252272B2 (en) * 2013-11-18 2016-02-02 Globalfoundries Inc. FinFET semiconductor device having local buried oxide
JP6444714B2 (ja) * 2013-12-20 2018-12-26 株式会社半導体エネルギー研究所 半導体装置の作製方法
US20150194433A1 (en) * 2014-01-08 2015-07-09 Broadcom Corporation Gate substantial contact based one-time programmable device
US9508830B2 (en) * 2014-01-23 2016-11-29 Taiwan Semiconductor Manufacturing Company Limited Method of forming FinFET
US11107808B1 (en) 2014-01-28 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure
US11031394B1 (en) 2014-01-28 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure
US10297586B2 (en) 2015-03-09 2019-05-21 Monolithic 3D Inc. Methods for processing a 3D semiconductor device
US9543407B2 (en) * 2014-02-27 2017-01-10 International Business Machines Corporation Low-K spacer for RMG finFET formation
US10553718B2 (en) * 2014-03-14 2020-02-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices with core-shell structures
US9947772B2 (en) 2014-03-31 2018-04-17 Stmicroelectronics, Inc. SOI FinFET transistor with strained channel
US9530659B2 (en) 2014-05-02 2016-12-27 International Business Machines Corporation Structure for preventing buried oxide gouging during planar and FinFET Processing on SOI
CN105097913B (zh) * 2014-05-05 2018-12-04 中芯国际集成电路制造(上海)有限公司 场效应晶体管及其制造方法
US9577100B2 (en) * 2014-06-16 2017-02-21 Globalfoundries Inc. FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions
US9502518B2 (en) 2014-06-23 2016-11-22 Stmicroelectronics, Inc. Multi-channel gate-all-around FET
US9659827B2 (en) * 2014-07-21 2017-05-23 Samsung Electronics Co., Ltd. Methods of manufacturing semiconductor devices by forming source/drain regions before gate electrode separation
TWI553869B (zh) * 2014-07-31 2016-10-11 瑞昱半導體股份有限公司 半導體元件及多閘極場效電晶體
US9306019B2 (en) * 2014-08-12 2016-04-05 GlobalFoundries, Inc. Integrated circuits with nanowires and methods of manufacturing the same
US9773865B2 (en) 2014-09-22 2017-09-26 International Business Machines Corporation Self-forming spacers using oxidation
US9064943B1 (en) 2014-09-30 2015-06-23 International Business Machines Corporation Gate-all-around field effect transistor structures and methods
US9735256B2 (en) 2014-10-17 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for FinFET comprising patterned oxide and dielectric layer under spacer features
US9281379B1 (en) 2014-11-19 2016-03-08 International Business Machines Corporation Gate-all-around fin device
KR102235612B1 (ko) 2015-01-29 2021-04-02 삼성전자주식회사 일-함수 금속을 갖는 반도체 소자 및 그 형성 방법
US9496338B2 (en) 2015-03-17 2016-11-15 International Business Machines Corporation Wire-last gate-all-around nanowire FET
TWI695513B (zh) * 2015-03-27 2020-06-01 日商半導體能源研究所股份有限公司 半導體裝置及電子裝置
US9496373B2 (en) * 2015-04-02 2016-11-15 International Business Machines Corporation Damage-resistant fin structures and FinFET CMOS
US11011507B1 (en) 2015-04-19 2021-05-18 Monolithic 3D Inc. 3D semiconductor device and structure
US10381328B2 (en) 2015-04-19 2019-08-13 Monolithic 3D Inc. Semiconductor device and structure
US11056468B1 (en) 2015-04-19 2021-07-06 Monolithic 3D Inc. 3D semiconductor device and structure
US10825779B2 (en) 2015-04-19 2020-11-03 Monolithic 3D Inc. 3D semiconductor device and structure
EP3295486A4 (en) 2015-05-08 2019-01-16 Cirrus Logic International Semiconductor Ltd. HIGH-DENSITY CAPACITORS FORMED FROM THIN VERTICAL SEMICONDUCTOR STRUCTURES SUCH AS FINFET
US9748394B2 (en) * 2015-05-20 2017-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET having a multi-portioned gate stack
US9455317B1 (en) 2015-06-24 2016-09-27 International Business Machines Corporation Nanowire semiconductor device including lateral-etch barrier region
US9941157B2 (en) * 2015-06-26 2018-04-10 Taiwan Semiconductor Manufacturing Company, Ltd. Porogen bonded gap filling material in semiconductor manufacturing
US9680020B2 (en) 2015-07-09 2017-06-13 Globalfoundries Inc. Increased contact area for FinFETs
US9647139B2 (en) 2015-09-04 2017-05-09 International Business Machines Corporation Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer
CN108401468A (zh) 2015-09-21 2018-08-14 莫诺利特斯3D有限公司 3d半导体器件和结构
US9608099B1 (en) 2015-09-22 2017-03-28 International Business Machines Corporation Nanowire semiconductor device
US10522225B1 (en) 2015-10-02 2019-12-31 Monolithic 3D Inc. Semiconductor device with non-volatile memory
US10847540B2 (en) 2015-10-24 2020-11-24 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11114464B2 (en) 2015-10-24 2021-09-07 Monolithic 3D Inc. 3D semiconductor device and structure
US10418369B2 (en) 2015-10-24 2019-09-17 Monolithic 3D Inc. Multi-level semiconductor memory device and structure
US11296115B1 (en) 2015-10-24 2022-04-05 Monolithic 3D Inc. 3D semiconductor device and structure
US11114427B2 (en) 2015-11-07 2021-09-07 Monolithic 3D Inc. 3D semiconductor processor and memory device and structure
US11937422B2 (en) 2015-11-07 2024-03-19 Monolithic 3D Inc. Semiconductor memory device and structure
US9882047B2 (en) * 2016-02-01 2018-01-30 International Business Machines Corporation Self-aligned replacement metal gate spacerless vertical field effect transistor
US9614040B1 (en) 2016-02-02 2017-04-04 International Business Machines Corporation Strained silicon germanium fin with block source/drain epitaxy and improved overlay capacitance
KR102413610B1 (ko) 2016-03-02 2022-06-24 삼성전자주식회사 레이아웃 디자인 시스템, 이를 이용한 반도체 장치 및 그 제조 방법
US9882000B2 (en) 2016-05-24 2018-01-30 Northrop Grumman Systems Corporation Wrap around gate field effect transistor (WAGFET)
US10236362B2 (en) 2016-06-30 2019-03-19 International Business Machines Corporation Nanowire FET including nanowire channel spacers
US10153367B2 (en) 2016-07-11 2018-12-11 International Business Machines Corporation Gate length controlled vertical FETs
US10332986B2 (en) 2016-08-22 2019-06-25 International Business Machines Corporation Formation of inner spacer on nanosheet MOSFET
US11088033B2 (en) * 2016-09-08 2021-08-10 International Business Machines Corporation Low resistance source-drain contacts using high temperature silicides
US11367789B2 (en) * 2016-09-26 2022-06-21 Intel Corporation Source/drain recess etch stop layers and bottom wide-gap cap for III-V MOSFETs
US11049773B2 (en) 2016-09-30 2021-06-29 Intel Corporation Art trench spacers to enable fin release for non-lattice matched channels
US11329059B1 (en) 2016-10-10 2022-05-10 Monolithic 3D Inc. 3D memory devices and structures with thinned single crystal substrates
US11869591B2 (en) 2016-10-10 2024-01-09 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11812620B2 (en) 2016-10-10 2023-11-07 Monolithic 3D Inc. 3D DRAM memory devices and structures with control circuits
US11251149B2 (en) 2016-10-10 2022-02-15 Monolithic 3D Inc. 3D memory device and structure
US11711928B2 (en) 2016-10-10 2023-07-25 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11930648B1 (en) 2016-10-10 2024-03-12 Monolithic 3D Inc. 3D memory devices and structures with metal layers
US10199503B2 (en) * 2017-04-24 2019-02-05 International Business Machines Corporation Under-channel gate transistors
US10276728B2 (en) 2017-07-07 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including non-volatile memory cells
US10672888B2 (en) 2017-08-21 2020-06-02 International Business Machines Corporation Vertical transistors having improved gate length control
US10535737B2 (en) 2017-10-27 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
WO2019199926A1 (en) * 2018-04-12 2019-10-17 Atomera Incorporated Device and method for making an inverted t channel field effect transistor (itfet) including a superlattice
US10749036B2 (en) * 2018-08-03 2020-08-18 Shenzhen China Star Optoelectronics Technology Co., Ltd. Oxide semiconductor thin film transistor having spaced channel and barrier strips and manufacturing method thereof
CN111463275B (zh) * 2019-01-18 2023-09-12 中芯国际集成电路制造(北京)有限公司 半导体结构及其形成方法
US11158652B1 (en) 2019-04-08 2021-10-26 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US10892016B1 (en) 2019-04-08 2021-01-12 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11296106B2 (en) 2019-04-08 2022-04-05 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11018156B2 (en) 2019-04-08 2021-05-25 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11763864B2 (en) 2019-04-08 2023-09-19 Monolithic 3D Inc. 3D memory semiconductor devices and structures with bit-line pillars
US11165032B2 (en) * 2019-09-05 2021-11-02 Taiwan Semiconductor Manufacturing Co., Ltd. Field effect transistor using carbon nanotubes
US11205593B2 (en) * 2020-05-20 2021-12-21 Applied Materials, Inc. Asymmetric fin trimming for fins of FinFET device
US11930696B2 (en) * 2021-03-18 2024-03-12 Taiwan Semiconductor Manufacturing Co., Ltd. Fabrication method of a double-gate carbon nanotube transistor

Family Cites Families (417)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4231149A (en) 1978-10-10 1980-11-04 Texas Instruments Incorporated Narrow band-gap semiconductor CCD imaging device and method of fabrication
GB2156149A (en) 1984-03-14 1985-10-02 Philips Electronic Associated Dielectrically-isolated integrated circuit manufacture
US4487652A (en) 1984-03-30 1984-12-11 Motorola, Inc. Slope etch of polyimide
US4711701A (en) 1986-09-16 1987-12-08 Texas Instruments Incorporated Self-aligned transistor method
US5514885A (en) * 1986-10-09 1996-05-07 Myrick; James J. SOI methods and apparatus
US4818715A (en) 1987-07-09 1989-04-04 Industrial Technology Research Institute Method of fabricating a LDDFET with self-aligned silicide
US4907048A (en) 1987-11-23 1990-03-06 Xerox Corporation Double implanted LDD transistor self-aligned with gate
US4905063A (en) 1988-06-21 1990-02-27 American Telephone And Telegraph Company, At&T Bell Laboratories Floating gate memories
JPH0214578A (ja) * 1988-07-01 1990-01-18 Fujitsu Ltd 半導体装置
KR910010043B1 (ko) 1988-07-28 1991-12-10 한국전기통신공사 스페이서를 이용한 미세선폭 형성방법
US4994873A (en) 1988-10-17 1991-02-19 Motorola, Inc. Local interconnect for stacked polysilicon device
US5346834A (en) 1988-11-21 1994-09-13 Hitachi, Ltd. Method for manufacturing a semiconductor device and a semiconductor memory device
US4906589A (en) * 1989-02-06 1990-03-06 Industrial Technology Research Institute Inverse-T LDDFET with self-aligned silicide
JPH02302044A (ja) * 1989-05-16 1990-12-14 Fujitsu Ltd 半導体装置の製造方法
US5328810A (en) 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
KR930003790B1 (ko) * 1990-07-02 1993-05-10 삼성전자 주식회사 반도체 장치의 캐패시터용 유전체
US5278102A (en) * 1990-08-18 1994-01-11 Fujitsu Limited SOI device and a fabrication process thereof
JP3061406B2 (ja) 1990-09-28 2000-07-10 株式会社東芝 半導体装置
JP3202223B2 (ja) * 1990-11-27 2001-08-27 日本電気株式会社 トランジスタの製造方法
US5521859A (en) * 1991-03-20 1996-05-28 Fujitsu Limited Semiconductor memory device having thin film transistor and method of producing the same
DE69213539T2 (de) 1991-04-26 1997-02-20 Canon Kk Halbleitervorrichtung mit verbessertem isoliertem Gate-Transistor
JPH05152293A (ja) 1991-04-30 1993-06-18 Sgs Thomson Microelectron Inc 段差付き壁相互接続体及びゲートの製造方法
US5346836A (en) 1991-06-06 1994-09-13 Micron Technology, Inc. Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnects
US5292670A (en) 1991-06-10 1994-03-08 Texas Instruments Incorporated Sidewall doping technique for SOI transistors
US5179037A (en) 1991-12-24 1993-01-12 Texas Instruments Incorporated Integration of lateral and vertical quantum well transistors in the same epitaxial stack
US5391506A (en) * 1992-01-31 1995-02-21 Kawasaki Steel Corporation Manufacturing method for semiconductor devices with source/drain formed in substrate projection.
JPH05243572A (ja) * 1992-02-27 1993-09-21 Fujitsu Ltd 半導体装置
US5405454A (en) * 1992-03-19 1995-04-11 Matsushita Electric Industrial Co., Ltd. Electrically insulated silicon structure and producing method therefor
JP2572003B2 (ja) * 1992-03-30 1997-01-16 三星電子株式会社 三次元マルチチャンネル構造を有する薄膜トランジスタの製造方法
JPH0793441B2 (ja) 1992-04-24 1995-10-09 ヒュンダイ エレクトロニクス インダストリーズ カンパニー リミテッド 薄膜トランジスタ及びその製造方法
KR960002088B1 (ko) * 1993-02-17 1996-02-10 삼성전자주식회사 에스오아이(SOI : silicon on insulator) 구조의 반도체 장치 제조방법
US5357119A (en) 1993-02-19 1994-10-18 Board Of Regents Of The University Of California Field effect devices having short period superlattice structures using Si and Ge
JPH06310547A (ja) 1993-02-25 1994-11-04 Mitsubishi Electric Corp 半導体装置及びその製造方法
EP0623963A1 (de) 1993-05-06 1994-11-09 Siemens Aktiengesellschaft MOSFET auf SOI-Substrat
US5739544A (en) * 1993-05-26 1998-04-14 Matsushita Electric Industrial Co., Ltd. Quantization functional device utilizing a resonance tunneling effect and method for producing the same
GB2282736B (en) 1993-05-28 1996-12-11 Nec Corp Radio base station for a mobile communications system
US6730549B1 (en) * 1993-06-25 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
JP3778581B2 (ja) 1993-07-05 2006-05-24 三菱電機株式会社 半導体装置およびその製造方法
US5398641A (en) 1993-07-27 1995-03-21 Texas Instruments Incorporated Method for p-type doping of semiconductor structures formed of group II and group VI elements
JP3460863B2 (ja) * 1993-09-17 2003-10-27 三菱電機株式会社 半導体装置の製造方法
US5554870A (en) * 1994-02-04 1996-09-10 Motorola, Inc. Integrated circuit having both vertical and horizontal devices and process for making the same
US5479033A (en) 1994-05-27 1995-12-26 Sandia Corporation Complementary junction heterostructure field-effect transistor
JP3317582B2 (ja) 1994-06-01 2002-08-26 菱電セミコンダクタシステムエンジニアリング株式会社 微細パターンの形成方法
JP3361922B2 (ja) 1994-09-13 2003-01-07 株式会社東芝 半導体装置
JP3378414B2 (ja) 1994-09-14 2003-02-17 株式会社東芝 半導体装置
JPH08153880A (ja) 1994-09-29 1996-06-11 Toshiba Corp 半導体装置及びその製造方法
US5602049A (en) 1994-10-04 1997-02-11 United Microelectronics Corporation Method of fabricating a buried structure SRAM cell
JPH08125152A (ja) 1994-10-28 1996-05-17 Canon Inc 半導体装置、それを用いた相関演算装置、ａｄ変換器、ｄａ変換器、信号処理システム
US5728594A (en) 1994-11-02 1998-03-17 Texas Instruments Incorporated Method of making a multiple transistor integrated circuit with thick copper interconnect
US5576227A (en) 1994-11-02 1996-11-19 United Microelectronics Corp. Process for fabricating a recessed gate MOS device
JP3078720B2 (ja) 1994-11-02 2000-08-21 三菱電機株式会社 半導体装置およびその製造方法
GB2295488B (en) 1994-11-24 1996-11-20 Toshiba Cambridge Res Center Semiconductor device
US5716879A (en) * 1994-12-15 1998-02-10 Goldstar Electron Company, Ltd. Method of making a thin film transistor
JPH08204191A (ja) 1995-01-20 1996-08-09 Sony Corp 電界効果トランジスタ及びその製造方法
US5665203A (en) 1995-04-28 1997-09-09 International Business Machines Corporation Silicon etching method
JP3303601B2 (ja) 1995-05-19 2002-07-22 日産自動車株式会社 溝型半導体装置
KR0165398B1 (ko) 1995-05-26 1998-12-15 윤종용 버티칼 트랜지스터의 제조방법
US5814545A (en) 1995-10-02 1998-09-29 Motorola, Inc. Semiconductor device having a phosphorus doped PECVD film and a method of manufacture
US5658806A (en) * 1995-10-26 1997-08-19 National Science Council Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration
US5814895A (en) 1995-12-22 1998-09-29 Sony Corporation Static random access memory having transistor elements formed on side walls of a trench in a semiconductor substrate
KR100205442B1 (ko) * 1995-12-26 1999-07-01 구본준 박막트랜지스터 및 그의 제조방법
US5595919A (en) 1996-02-20 1997-01-21 Chartered Semiconductor Manufacturing Pte Ltd. Method of making self-aligned halo process for reducing junction capacitance
DE19607209A1 (de) 1996-02-26 1997-08-28 Gregor Kohlruss Reinigungsvorrichtung zum Reinigen von flächigen Gegenständen
JPH09293793A (ja) * 1996-04-26 1997-11-11 Mitsubishi Electric Corp 薄膜トランジスタを有する半導体装置およびその製造方法
US5793088A (en) 1996-06-18 1998-08-11 Integrated Device Technology, Inc. Structure for controlling threshold voltage of MOSFET
JP3710880B2 (ja) 1996-06-28 2005-10-26 株式会社東芝 不揮発性半導体記憶装置
TW548686B (en) 1996-07-11 2003-08-21 Semiconductor Energy Lab CMOS semiconductor device and apparatus using the same
US5817560A (en) * 1996-09-12 1998-10-06 Advanced Micro Devices, Inc. Ultra short trench transistors and process for making same
US6399970B2 (en) 1996-09-17 2002-06-04 Matsushita Electric Industrial Co., Ltd. FET having a Si/SiGeC heterojunction channel
US6063677A (en) 1996-10-28 2000-05-16 Texas Instruments Incorporated Method of forming a MOSFET using a disposable gate and raised source and drain
US6063675A (en) 1996-10-28 2000-05-16 Texas Instruments Incorporated Method of forming a MOSFET using a disposable gate with a sidewall dielectric
US6163053A (en) 1996-11-06 2000-12-19 Ricoh Company, Ltd. Semiconductor device having opposite-polarity region under channel
US5827769A (en) 1996-11-20 1998-10-27 Intel Corporation Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode
JPH10150185A (ja) 1996-11-20 1998-06-02 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5773331A (en) 1996-12-17 1998-06-30 International Business Machines Corporation Method for making single and double gate field effect transistors with sidewall source-drain contacts
US5908313A (en) 1996-12-31 1999-06-01 Intel Corporation Method of forming a transistor
JP4086926B2 (ja) 1997-01-29 2008-05-14 富士通株式会社 半導体装置及びその製造方法
JPH118390A (ja) * 1997-06-18 1999-01-12 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6251763B1 (en) 1997-06-30 2001-06-26 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
US6054355A (en) 1997-06-30 2000-04-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device which includes forming a dummy gate
JPH1140811A (ja) * 1997-07-22 1999-02-12 Hitachi Ltd 半導体装置およびその製造方法
US5952701A (en) 1997-08-18 1999-09-14 National Semiconductor Corporation Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value
US5776821A (en) 1997-08-22 1998-07-07 Vlsi Technology, Inc. Method for forming a reduced width gate electrode
US6066869A (en) 1997-10-06 2000-05-23 Micron Technology, Inc. Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
US5976767A (en) 1997-10-09 1999-11-02 Micron Technology, Inc. Ammonium hydroxide etch of photoresist masked silicon
US5856225A (en) 1997-11-24 1999-01-05 Chartered Semiconductor Manufacturing Ltd Creation of a self-aligned, ion implanted channel region, after source and drain formation
US6120846A (en) 1997-12-23 2000-09-19 Advanced Technology Materials, Inc. Method for the selective deposition of bismuth based ferroelectric thin films by chemical vapor deposition
US5888309A (en) * 1997-12-29 1999-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluorine containing plasma followed by an oxygen containing plasma
US6117741A (en) 1998-01-09 2000-09-12 Texas Instruments Incorporated Method of forming a transistor having an improved sidewall gate structure
US6351040B1 (en) * 1998-01-22 2002-02-26 Micron Technology, Inc. Method and apparatus for implementing selected functionality on an integrated circuit device
US6294416B1 (en) 1998-01-23 2001-09-25 Texas Instruments-Acer Incorporated Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts
US6097065A (en) * 1998-03-30 2000-08-01 Micron Technology, Inc. Circuits and methods for dual-gated transistors
US6307235B1 (en) 1998-03-30 2001-10-23 Micron Technology, Inc. Another technique for gated lateral bipolar transistors
US6087208A (en) 1998-03-31 2000-07-11 Advanced Micro Devices, Inc. Method for increasing gate capacitance by using both high and low dielectric gate material
US6215190B1 (en) 1998-05-12 2001-04-10 International Business Machines Corporation Borderless contact to diffusion with respect to gate conductor and methods for fabricating
US6232641B1 (en) 1998-05-29 2001-05-15 Kabushiki Kaisha Toshiba Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor
US6114201A (en) 1998-06-01 2000-09-05 Texas Instruments-Acer Incorporated Method of manufacturing a multiple fin-shaped capacitor for high density DRAMs
US6317444B1 (en) 1998-06-12 2001-11-13 Agere System Optoelectronics Guardian Corp. Optical device including carbon-doped contact layers
US6165880A (en) 1998-06-15 2000-12-26 Taiwan Semiconductor Manufacturing Company Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits
US6130123A (en) 1998-06-30 2000-10-10 Intel Corporation Method for making a complementary metal gate electrode technology
JP2000037842A (ja) 1998-07-27 2000-02-08 Dainippon Printing Co Ltd 電磁波吸収化粧材
US6696366B1 (en) 1998-08-17 2004-02-24 Lam Research Corporation Technique for etching a low capacitance dielectric layer
JP2000156502A (ja) 1998-09-21 2000-06-06 Texas Instr Inc <Ti> 集積回路及び方法
US6262456B1 (en) 1998-11-06 2001-07-17 Advanced Micro Devices, Inc. Integrated circuit having transistors with different threshold voltages
US6114206A (en) 1998-11-06 2000-09-05 Advanced Micro Devices, Inc. Multiple threshold voltage transistor implemented by a damascene process
US5985726A (en) 1998-11-06 1999-11-16 Advanced Micro Devices, Inc. Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFET
US6153485A (en) 1998-11-09 2000-11-28 Chartered Semiconductor Manufacturing Ltd. Salicide formation on narrow poly lines by pulling back of spacer
US6200865B1 (en) 1998-12-04 2001-03-13 Advanced Micro Devices, Inc. Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate
US6362111B1 (en) 1998-12-09 2002-03-26 Texas Instruments Incorporated Tunable gate linewidth reduction process
TW406312B (en) 1998-12-18 2000-09-21 United Microelectronics Corp The method of etching doped poly-silicon
TW449919B (en) 1998-12-18 2001-08-11 Koninkl Philips Electronics Nv A method of manufacturing a semiconductor device
US6380558B1 (en) 1998-12-29 2002-04-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US6150222A (en) 1999-01-07 2000-11-21 Advanced Micro Devices, Inc. Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions
FR2788629B1 (fr) 1999-01-15 2003-06-20 Commissariat Energie Atomique Transistor mis et procede de fabrication d'un tel transistor sur un substrat semiconducteur
US6174820B1 (en) 1999-02-16 2001-01-16 Sandia Corporation Use of silicon oxynitride as a sacrificial material for microelectromechanical devices
JP2000243854A (ja) 1999-02-22 2000-09-08 Toshiba Corp 半導体装置及びその製造方法
US6093621A (en) 1999-04-05 2000-07-25 Vanguard International Semiconductor Corp. Method of forming shallow trench isolation
US7045468B2 (en) 1999-04-09 2006-05-16 Intel Corporation Isolated junction structure and method of manufacture
US6459123B1 (en) 1999-04-30 2002-10-01 Infineon Technologies Richmond, Lp Double gated transistor
DE60001601T2 (de) * 1999-06-18 2003-12-18 Lucent Technologies Inc Fertigungsverfahren zur Herstellung eines CMOS integrieten Schaltkreises mit vertikalen Transistoren
JP2001015704A (ja) 1999-06-29 2001-01-19 Hitachi Ltd 半導体集積回路
US6218309B1 (en) 1999-06-30 2001-04-17 Lam Research Corporation Method of achieving top rounding and uniform etch depths while etching shallow trench isolation features
US6501131B1 (en) 1999-07-22 2002-12-31 International Business Machines Corporation Transistors having independently adjustable parameters
TW432594B (en) 1999-07-31 2001-05-01 Taiwan Semiconductor Mfg Manufacturing method for shallow trench isolation
US6259135B1 (en) 1999-09-24 2001-07-10 International Business Machines Corporation MOS transistors structure for reducing the size of pitch limited circuits
FR2799305B1 (fr) * 1999-10-05 2004-06-18 St Microelectronics Sa Procede de fabrication d'un dispositif semi-conducteur a grille enveloppante et dispositif obtenu
EP1091413A3 (en) 1999-10-06 2005-01-12 Lsi Logic Corporation Fully-depleted, fully-inverted, short-length and vertical channel, dual-gate, cmos fet
US6541829B2 (en) 1999-12-03 2003-04-01 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6252284B1 (en) * 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
KR100311049B1 (ko) 1999-12-13 2001-10-12 윤종용 불휘발성 반도체 메모리장치 및 그의 제조방법
US6303479B1 (en) 1999-12-16 2001-10-16 Spinnaker Semiconductor, Inc. Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts
JP4923318B2 (ja) 1999-12-17 2012-04-25 ソニー株式会社 不揮発性半導体記憶装置およびその動作方法
JP4194237B2 (ja) 1999-12-28 2008-12-10 株式会社リコー 電界効果トランジスタを用いた電圧発生回路及び基準電圧源回路
US7391087B2 (en) 1999-12-30 2008-06-24 Intel Corporation MOS transistor structure and method of fabrication
JP3613113B2 (ja) 2000-01-21 2005-01-26 日本電気株式会社 半導体装置およびその製造方法
US6319807B1 (en) 2000-02-07 2001-11-20 United Microelectronics Corp. Method for forming a semiconductor device by using reverse-offset spacer process
JP3846706B2 (ja) * 2000-02-23 2006-11-15 信越半導体株式会社 ウエーハ外周面取部の研磨方法及び研磨装置
US6483156B1 (en) 2000-03-16 2002-11-19 International Business Machines Corporation Double planar gated SOI MOSFET structure
FR2806832B1 (fr) 2000-03-22 2002-10-25 Commissariat Energie Atomique Transistor mos a source et drain metalliques, et procede de fabrication d'un tel transistor
JP3906005B2 (ja) 2000-03-27 2007-04-18 株式会社東芝 半導体装置の製造方法
KR100332834B1 (ko) 2000-03-29 2002-04-15 윤덕용 비등방성 식각을 이용한 서브마이크론 게이트 제조 방법
TW466606B (en) 2000-04-20 2001-12-01 United Microelectronics Corp Manufacturing method for dual metal gate electrode
JP2001338987A (ja) 2000-05-26 2001-12-07 Nec Microsystems Ltd Ｍｏｓトランジスタのシャロートレンチ分離領域の形成方法
FR2810161B1 (fr) 2000-06-09 2005-03-11 Commissariat Energie Atomique Memoire electronique a architecture damascene et procede de realisation d'une telle memoire
US6526996B1 (en) 2000-06-12 2003-03-04 Promos Technologies, Inc. Dry clean method instead of traditional wet clean after metal etch
US6391782B1 (en) * 2000-06-20 2002-05-21 Advanced Micro Devices, Inc. Process for forming multiple active lines and gate-all-around MOSFET
KR100545706B1 (ko) 2000-06-28 2006-01-24 주식회사 하이닉스반도체 반도체 소자 제조방법
JP4112358B2 (ja) 2000-07-04 2008-07-02 インフィネオン テクノロジーズ アクチエンゲゼルシャフト 電界効果トランジスタ
US20020011612A1 (en) * 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2002047034A (ja) * 2000-07-31 2002-02-12 Shinetsu Quartz Prod Co Ltd プラズマを利用したプロセス装置用の石英ガラス治具
US6403981B1 (en) 2000-08-07 2002-06-11 Advanced Micro Devices, Inc. Double gate transistor having a silicon/germanium channel region
KR100338778B1 (ko) 2000-08-21 2002-05-31 윤종용 선택적 실리사이드 공정을 이용한 모스 트랜지스터의제조방법
US6358800B1 (en) 2000-09-18 2002-03-19 Vanguard International Semiconductor Corporation Method of forming a MOSFET with a recessed-gate having a channel length beyond photolithography limit
US6387820B1 (en) 2000-09-19 2002-05-14 Advanced Micro Devices, Inc. BC13/AR chemistry for metal overetching on a high density plasma etcher
JP2002100762A (ja) 2000-09-22 2002-04-05 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP4044276B2 (ja) * 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6562665B1 (en) * 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
US7163864B1 (en) 2000-10-18 2007-01-16 International Business Machines Corporation Method of fabricating semiconductor side wall fin
US6645840B2 (en) * 2000-10-19 2003-11-11 Texas Instruments Incorporated Multi-layered polysilicon process
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6396108B1 (en) * 2000-11-13 2002-05-28 Advanced Micro Devices, Inc. Self-aligned double gate silicon-on-insulator (SOI) device
US6716684B1 (en) * 2000-11-13 2004-04-06 Advanced Micro Devices, Inc. Method of making a self-aligned triple gate silicon-on-insulator device
US6472258B1 (en) 2000-11-13 2002-10-29 International Business Machines Corporation Double gate trench transistor
US6479866B1 (en) 2000-11-14 2002-11-12 Advanced Micro Devices, Inc. SOI device with self-aligned selective damage implant, and method
JP2002198441A (ja) 2000-11-16 2002-07-12 Hynix Semiconductor Inc 半導体素子のデュアル金属ゲート形成方法
US6552401B1 (en) 2000-11-27 2003-04-22 Micron Technology Use of gate electrode workfunction to improve DRAM refresh
US20020100942A1 (en) 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6921947B2 (en) * 2000-12-15 2005-07-26 Renesas Technology Corp. Semiconductor device having recessed isolation insulation film
US6413877B1 (en) * 2000-12-22 2002-07-02 Lam Research Corporation Method of preventing damage to organo-silicate-glass materials during resist stripping
JP2002198368A (ja) * 2000-12-26 2002-07-12 Nec Corp 半導体装置の製造方法
US6537901B2 (en) 2000-12-29 2003-03-25 Hynix Semiconductor Inc. Method of manufacturing a transistor in a semiconductor device
TW561530B (en) 2001-01-03 2003-11-11 Macronix Int Co Ltd Process for fabricating CMOS transistor of IC devices employing double spacers for preventing short-channel effect
US6975014B1 (en) 2001-01-09 2005-12-13 Advanced Micro Devices, Inc. Method for making an ultra thin FDSOI device with improved short-channel performance
US6359311B1 (en) * 2001-01-17 2002-03-19 Taiwan Semiconductor Manufacturing Co., Ltd. Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same
US6403434B1 (en) 2001-02-09 2002-06-11 Advanced Micro Devices, Inc. Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric
US6475890B1 (en) 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
JP2002246310A (ja) 2001-02-14 2002-08-30 Sony Corp 半導体薄膜の形成方法及び半導体装置の製造方法、これらの方法の実施に使用する装置、並びに電気光学装置
US6475869B1 (en) * 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6630388B2 (en) 2001-03-13 2003-10-07 National Institute Of Advanced Industrial Science And Technology Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
TW582071B (en) 2001-03-20 2004-04-01 Macronix Int Co Ltd Method for etching metal in a semiconductor
JP3940565B2 (ja) 2001-03-29 2007-07-04 株式会社東芝 半導体装置及びその製造方法
JP2002298051A (ja) 2001-03-30 2002-10-11 Mizuho Bank Ltd ポイント交換サービス・システム
US6458662B1 (en) 2001-04-04 2002-10-01 Advanced Micro Devices, Inc. Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed
KR100414217B1 (ko) * 2001-04-12 2004-01-07 삼성전자주식회사 게이트 올 어라운드형 트랜지스터를 가진 반도체 장치 및그 형성 방법
US6645861B2 (en) 2001-04-18 2003-11-11 International Business Machines Corporation Self-aligned silicide process for silicon sidewall source and drain contacts
US6787402B1 (en) 2001-04-27 2004-09-07 Advanced Micro Devices, Inc. Double-gate vertical MOSFET transistor and fabrication method
US6902947B2 (en) 2001-05-07 2005-06-07 Applied Materials, Inc. Integrated method for release and passivation of MEMS structures
SG112804A1 (en) 2001-05-10 2005-07-28 Inst Of Microelectronics Sloped trench etching process
KR100363332B1 (en) * 2001-05-23 2002-12-05 Samsung Electronics Co Ltd Method for forming semiconductor device having gate all-around type transistor
US6635923B2 (en) * 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US6506692B2 (en) 2001-05-30 2003-01-14 Intel Corporation Method of making a semiconductor device using a silicon carbide hard mask
US6737333B2 (en) 2001-07-03 2004-05-18 Texas Instruments Incorporated Semiconductor device isolation structure and method of forming
JP2003017508A (ja) 2001-07-05 2003-01-17 Nec Corp 電界効果トランジスタ
US6501141B1 (en) 2001-08-13 2002-12-31 Taiwan Semiconductor Manufacturing Company, Ltd Self-aligned contact with improved isolation and method for forming
US6534807B2 (en) 2001-08-13 2003-03-18 International Business Machines Corporation Local interconnect junction on insulator (JOI) structure
US6764965B2 (en) 2001-08-17 2004-07-20 United Microelectronics Corp. Method for improving the coating capability of low-k dielectric layer
JP2003100902A (ja) 2001-09-21 2003-04-04 Mitsubishi Electric Corp 半導体装置の製造方法
US6689650B2 (en) * 2001-09-27 2004-02-10 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US6492212B1 (en) * 2001-10-05 2002-12-10 International Business Machines Corporation Variable threshold voltage double gated transistors and method of fabrication
US20030085194A1 (en) * 2001-11-07 2003-05-08 Hopkins Dean A. Method for fabricating close spaced mirror arrays
US7385262B2 (en) * 2001-11-27 2008-06-10 The Board Of Trustees Of The Leland Stanford Junior University Band-structure modulation of nano-structures in an electric field
US6967351B2 (en) * 2001-12-04 2005-11-22 International Business Machines Corporation Finfet SRAM cell using low mobility plane for cell stability and method for forming
US6657259B2 (en) 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US6610576B2 (en) * 2001-12-13 2003-08-26 International Business Machines Corporation Method for forming asymmetric dual gate transistor
US6555879B1 (en) 2002-01-11 2003-04-29 Advanced Micro Devices, Inc. SOI device with metal source/drain and method of fabrication
US6722946B2 (en) 2002-01-17 2004-04-20 Nutool, Inc. Advanced chemical mechanical polishing system with smart endpoint detection
US6583469B1 (en) 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same
KR100442089B1 (ko) * 2002-01-29 2004-07-27 삼성전자주식회사 노치된 게이트 전극을 갖는 모스 트랜지스터의 제조방법
KR100458288B1 (ko) 2002-01-30 2004-11-26 한국과학기술원 이중-게이트 ＦｉｎＦＥＴ 소자 및 그 제조방법
DE10203998A1 (de) 2002-02-01 2003-08-21 Infineon Technologies Ag Verfahren zum Herstellen einer zackenförmigen Struktur, Verfahren zum Herstellen eines Transistors, Verfahren zum Herstellen eines Floating Gate-Transistors, Transistor, Floating Gate-Transistor und Speicher-Anordnung
US6784071B2 (en) 2003-01-31 2004-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement
US20030151077A1 (en) * 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
JP3782021B2 (ja) * 2002-02-22 2006-06-07 株式会社東芝 半導体装置、半導体装置の製造方法、半導体基板の製造方法
US6660598B2 (en) 2002-02-26 2003-12-09 International Business Machines Corporation Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region
JP4370104B2 (ja) 2002-03-05 2009-11-25 シャープ株式会社 半導体記憶装置
US6639827B2 (en) 2002-03-12 2003-10-28 Intel Corporation Low standby power using shadow storage
US6635909B2 (en) * 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
US6605498B1 (en) 2002-03-29 2003-08-12 Intel Corporation Semiconductor transistor having a backfilled channel material
US6784076B2 (en) 2002-04-08 2004-08-31 Micron Technology, Inc. Process for making a silicon-on-insulator ledge by implanting ions from silicon source
FR2838238B1 (fr) * 2002-04-08 2005-04-15 St Microelectronics Sa Dispositif semiconducteur a grille enveloppante encapsule dans un milieu isolant
US6762469B2 (en) 2002-04-19 2004-07-13 International Business Machines Corporation High performance CMOS device structure with mid-gap metal gate
US6713396B2 (en) * 2002-04-29 2004-03-30 Hewlett-Packard Development Company, L.P. Method of fabricating high density sub-lithographic features on a substrate
US6537885B1 (en) 2002-05-09 2003-03-25 Infineon Technologies Ag Transistor and method of manufacturing a transistor having a shallow junction formation using a two step EPI layer
US6642090B1 (en) 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US6680240B1 (en) * 2002-06-25 2004-01-20 Advanced Micro Devices, Inc. Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
US7105891B2 (en) 2002-07-15 2006-09-12 Texas Instruments Incorporated Gate structure and method
US6974729B2 (en) 2002-07-16 2005-12-13 Interuniversitair Microelektronica Centrum (Imec) Integrated semiconductor fin device and a method for manufacturing such device
KR100477543B1 (ko) 2002-07-26 2005-03-18 동부아남반도체 주식회사 단채널 트랜지스터 형성방법
US6919238B2 (en) * 2002-07-29 2005-07-19 Intel Corporation Silicon on insulator (SOI) transistor and methods of fabrication
US6921702B2 (en) 2002-07-30 2005-07-26 Micron Technology Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
EP1387395B1 (en) 2002-07-31 2016-11-23 Micron Technology, Inc. Method for manufacturing semiconductor integrated circuit structures
JP2004071996A (ja) 2002-08-09 2004-03-04 Hitachi Ltd 半導体集積回路装置の製造方法
US6984585B2 (en) 2002-08-12 2006-01-10 Applied Materials Inc Method for removal of residue from a magneto-resistive random access memory (MRAM) film stack using a sacrificial mask layer
US6833556B2 (en) 2002-08-12 2004-12-21 Acorn Technologies, Inc. Insulated gate field effect transistor having passivated schottky barriers to the channel
US6891234B1 (en) 2004-01-07 2005-05-10 Acorn Technologies, Inc. Transistor with workfunction-induced charge layer
JP3865233B2 (ja) 2002-08-19 2007-01-10 富士通株式会社 Ｃｍｏｓ集積回路装置
US7358121B2 (en) * 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US7163851B2 (en) * 2002-08-26 2007-01-16 International Business Machines Corporation Concurrent Fin-FET and thick-body device fabrication
JP5179692B2 (ja) 2002-08-30 2013-04-10 富士通セミコンダクター株式会社 半導体記憶装置及びその製造方法
US6770516B2 (en) 2002-09-05 2004-08-03 Taiwan Semiconductor Manufacturing Company Method of forming an N channel and P channel FINFET device on the same semiconductor substrate
JP3651802B2 (ja) 2002-09-12 2005-05-25 株式会社東芝 半導体装置の製造方法
US6794313B1 (en) 2002-09-20 2004-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Oxidation process to improve polysilicon sidewall roughness
JP3556651B2 (ja) * 2002-09-27 2004-08-18 沖電気工業株式会社 半導体装置の製造方法
US6800910B2 (en) 2002-09-30 2004-10-05 Advanced Micro Devices, Inc. FinFET device incorporating strained silicon in the channel region
KR100481209B1 (ko) 2002-10-01 2005-04-08 삼성전자주식회사 다중 채널을 갖는 모스 트랜지스터 및 그 제조방법
JP4294935B2 (ja) 2002-10-17 2009-07-15 株式会社ルネサステクノロジ 半導体装置
US6706571B1 (en) * 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US6833588B2 (en) 2002-10-22 2004-12-21 Advanced Micro Devices, Inc. Semiconductor device having a U-shaped gate structure
US6706581B1 (en) 2002-10-29 2004-03-16 Taiwan Semiconductor Manufacturing Company Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices
US6787439B2 (en) * 2002-11-08 2004-09-07 Advanced Micro Devices, Inc. Method using planarizing gate material to improve gate critical dimension in semiconductor devices
US6611029B1 (en) * 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6855990B2 (en) * 2002-11-26 2005-02-15 Taiwan Semiconductor Manufacturing Co., Ltd Strained-channel multiple-gate transistor
US6709982B1 (en) * 2002-11-26 2004-03-23 Advanced Micro Devices, Inc. Double spacer FinFET formation
US6825506B2 (en) 2002-11-27 2004-11-30 Intel Corporation Field effect transistor and method of fabrication
US6821834B2 (en) 2002-12-04 2004-11-23 Yoshiyuki Ando Ion implantation methods and transistor cell layout for fin type transistors
US6645797B1 (en) 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
US6686231B1 (en) 2002-12-06 2004-02-03 Advanced Micro Devices, Inc. Damascene gate process with sacrificial oxide in semiconductor devices
KR100487922B1 (ko) 2002-12-06 2005-05-06 주식회사 하이닉스반도체 반도체소자의 트랜지스터 및 그 형성방법
US7728360B2 (en) 2002-12-06 2010-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-gate transistor structure
US7214991B2 (en) 2002-12-06 2007-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS inverters configured using multiple-gate transistors
US6869868B2 (en) 2002-12-13 2005-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a MOSFET device with metal containing gate structures
US6867425B2 (en) 2002-12-13 2005-03-15 Intel Corporation Lateral phase change memory and method therefor
US6794718B2 (en) 2002-12-19 2004-09-21 International Business Machines Corporation High mobility crystalline planes in double-gate CMOS technology
US6780694B2 (en) 2003-01-08 2004-08-24 International Business Machines Corporation MOS transistor
US7259425B2 (en) 2003-01-23 2007-08-21 Advanced Micro Devices, Inc. Tri-gate and gate around MOSFET devices and methods for making same
US6762483B1 (en) 2003-01-23 2004-07-13 Advanced Micro Devices, Inc. Narrow fin FinFET
US6803631B2 (en) 2003-01-23 2004-10-12 Advanced Micro Devices, Inc. Strained channel finfet
US6885055B2 (en) * 2003-02-04 2005-04-26 Lee Jong-Ho Double-gate FinFET device and fabricating method thereof
KR100543472B1 (ko) 2004-02-11 2006-01-20 삼성전자주식회사 소오스/드레인 영역에 디플리션 방지막을 구비하는 반도체소자 및 그 형성 방법
WO2004073044A2 (en) 2003-02-13 2004-08-26 Massachusetts Institute Of Technology Finfet device and method to make same
US6855606B2 (en) * 2003-02-20 2005-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-rod devices
US7105894B2 (en) 2003-02-27 2006-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Contacts to semiconductor fin devices
KR100499159B1 (ko) 2003-02-28 2005-07-01 삼성전자주식회사 리세스 채널을 갖는 반도체장치 및 그 제조방법
US6800885B1 (en) 2003-03-12 2004-10-05 Advance Micro Devices, Inc. Asymmetrical double gate or all-around gate MOSFET devices and methods for making same
US6716690B1 (en) * 2003-03-12 2004-04-06 Advanced Micro Devices, Inc. Uniformly doped source/drain junction in a double-gate MOSFET
US6787854B1 (en) 2003-03-12 2004-09-07 Advanced Micro Devices, Inc. Method for forming a fin in a finFET device
TW582099B (en) 2003-03-13 2004-04-01 Ind Tech Res Inst Method of adhering material layer on transparent substrate and method of forming single crystal silicon on transparent substrate
JP4563652B2 (ja) * 2003-03-13 2010-10-13 シャープ株式会社 メモリ機能体および微粒子形成方法並びにメモリ素子、半導体装置および電子機器
US6844238B2 (en) * 2003-03-26 2005-01-18 Taiwan Semiconductor Manufacturing Co., Ltd Multiple-gate transistors with improved gate control
US20040191980A1 (en) 2003-03-27 2004-09-30 Rafael Rios Multi-corner FET for better immunity from short channel effects
US6790733B1 (en) 2003-03-28 2004-09-14 International Business Machines Corporation Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer
US6764884B1 (en) * 2003-04-03 2004-07-20 Advanced Micro Devices, Inc. Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
US6902962B2 (en) 2003-04-04 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon-on-insulator chip with multiple crystal orientations
TWI231994B (en) 2003-04-04 2005-05-01 Univ Nat Taiwan Strained Si FinFET
US7442415B2 (en) 2003-04-11 2008-10-28 Sharp Laboratories Of America, Inc. Modulated temperature method of atomic layer deposition (ALD) of high dielectric constant films
JP2004319704A (ja) 2003-04-15 2004-11-11 Seiko Instruments Inc 半導体装置
TW200506093A (en) 2003-04-21 2005-02-16 Aviza Tech Inc System and method for forming multi-component films
US20070108514A1 (en) 2003-04-28 2007-05-17 Akira Inoue Semiconductor device and method of fabricating the same
US7074656B2 (en) 2003-04-29 2006-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of semiconductor fin devices
US6867433B2 (en) * 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
JP3976703B2 (ja) 2003-04-30 2007-09-19 エルピーダメモリ株式会社 半導体装置の製造方法
US6838322B2 (en) * 2003-05-01 2005-01-04 Freescale Semiconductor, Inc. Method for forming a double-gated semiconductor device
US6909147B2 (en) 2003-05-05 2005-06-21 International Business Machines Corporation Multi-height FinFETS
US6765303B1 (en) 2003-05-06 2004-07-20 Advanced Micro Devices, Inc. FinFET-based SRAM cell
EP1643560A4 (en) 2003-05-30 2007-04-11 Matsushita Electric Ind Co Ltd SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF
US6830998B1 (en) 2003-06-17 2004-12-14 Advanced Micro Devices, Inc. Gate dielectric quality for replacement metal gate transistors
US7045401B2 (en) 2003-06-23 2006-05-16 Sharp Laboratories Of America, Inc. Strained silicon finFET device
US6911383B2 (en) 2003-06-26 2005-06-28 International Business Machines Corporation Hybrid planar and finFET CMOS devices
US20040262683A1 (en) 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US6960517B2 (en) 2003-06-30 2005-11-01 Intel Corporation N-gate transistor
US6716686B1 (en) 2003-07-08 2004-04-06 Advanced Micro Devices, Inc. Method for forming channels in a finfet device
US6921982B2 (en) * 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
US7013447B2 (en) 2003-07-22 2006-03-14 Freescale Semiconductor, Inc. Method for converting a planar transistor design to a vertical double gate transistor design
KR100487566B1 (ko) 2003-07-23 2005-05-03 삼성전자주식회사 핀 전계 효과 트랜지스터 및 그 형성 방법
KR100487567B1 (ko) 2003-07-24 2005-05-03 삼성전자주식회사 핀 전계효과 트랜지스터 형성 방법
EP1519420A2 (en) * 2003-09-25 2005-03-30 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Multiple gate semiconductor device and method for forming same
US7301206B2 (en) 2003-08-01 2007-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
US6835618B1 (en) 2003-08-05 2004-12-28 Advanced Micro Devices, Inc. Epitaxially grown fin for FinFET
US6787406B1 (en) 2003-08-12 2004-09-07 Advanced Micro Devices, Inc. Systems and methods for forming dense n-channel and p-channel fins using shadow implanting
US7172943B2 (en) * 2003-08-13 2007-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate transistors formed on bulk substrates
KR100496891B1 (ko) 2003-08-14 2005-06-23 삼성전자주식회사 핀 전계효과 트랜지스터를 위한 실리콘 핀 및 그 제조 방법
US7355253B2 (en) 2003-08-22 2008-04-08 International Business Machines Corporation Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates
WO2005022637A1 (ja) 2003-08-28 2005-03-10 Nec Corporation フィン型電界効果トランジスタを有する半導体装置
US6998301B1 (en) 2003-09-03 2006-02-14 Advanced Micro Devices, Inc. Method for forming a tri-gate MOSFET
US6877728B2 (en) 2003-09-04 2005-04-12 Lakin Manufacturing Corporation Suspension assembly having multiple torsion members which cooperatively provide suspension to a wheel
JP4439358B2 (ja) 2003-09-05 2010-03-24 株式会社東芝 電界効果トランジスタ及びその製造方法
US7170126B2 (en) 2003-09-16 2007-01-30 International Business Machines Corporation Structure of vertical strained silicon devices
US6970373B2 (en) 2003-10-02 2005-11-29 Intel Corporation Method and apparatus for improving stability of a 6T CMOS SRAM cell
US7612416B2 (en) 2003-10-09 2009-11-03 Nec Corporation Semiconductor device having a conductive portion below an interlayer insulating film and method for producing the same
US20050139860A1 (en) 2003-10-22 2005-06-30 Snyder John P. Dynamic schottky barrier MOSFET device and method of manufacture
US6946377B2 (en) 2003-10-29 2005-09-20 Texas Instruments Incorporated Multiple-gate MOSFET device with lithography independent silicon body thickness and methods for fabricating the same
US7138320B2 (en) 2003-10-31 2006-11-21 Advanced Micro Devices, Inc. Advanced technique for forming a transistor having raised drain and source regions
KR100515061B1 (ko) 2003-10-31 2005-09-14 삼성전자주식회사 핀 전계 효과 트랜지스터를 갖는 반도체 소자 및 그 형성방법
US6867460B1 (en) * 2003-11-05 2005-03-15 International Business Machines Corporation FinFET SRAM cell with chevron FinFET logic
US6831310B1 (en) 2003-11-10 2004-12-14 Freescale Semiconductor, Inc. Integrated circuit having multiple memory types and method of formation
US6885072B1 (en) 2003-11-18 2005-04-26 Applied Intellectual Properties Co., Ltd. Nonvolatile memory with undercut trapping structure
US7545001B2 (en) 2003-11-25 2009-06-09 Taiwan Semiconductor Manufacturing Company Semiconductor device having high drive current and method of manufacture therefor
US7183137B2 (en) * 2003-12-01 2007-02-27 Taiwan Semiconductor Manufacturing Company Method for dicing semiconductor wafers
US7075150B2 (en) 2003-12-02 2006-07-11 International Business Machines Corporation Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique
US7018551B2 (en) * 2003-12-09 2006-03-28 International Business Machines Corporation Pull-back method of forming fins in FinFets
US7388258B2 (en) * 2003-12-10 2008-06-17 International Business Machines Corporation Sectional field effect devices
JP2005183770A (ja) 2003-12-22 2005-07-07 Mitsubishi Electric Corp 高周波用半導体装置
US7569882B2 (en) 2003-12-23 2009-08-04 Interuniversitair Microelektronica Centrum (Imec) Non-volatile multibit memory cell and method of manufacturing thereof
US7662689B2 (en) 2003-12-23 2010-02-16 Intel Corporation Strained transistor integration for CMOS
US7223679B2 (en) 2003-12-24 2007-05-29 Intel Corporation Transistor gate electrode having conductor material layer
US7045407B2 (en) 2003-12-30 2006-05-16 Intel Corporation Amorphous etch stop for the anisotropic etching of substrates
US7247578B2 (en) 2003-12-30 2007-07-24 Intel Corporation Method of varying etch selectivities of a film
US7078282B2 (en) 2003-12-30 2006-07-18 Intel Corporation Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films
US7105390B2 (en) * 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US6997415B2 (en) * 2003-12-31 2006-02-14 Gulfstream Aerospace Corporation Method and arrangement for aircraft fuel dispersion
US7705345B2 (en) * 2004-01-07 2010-04-27 International Business Machines Corporation High performance strained silicon FinFETs device and method for forming same
US7056794B2 (en) 2004-01-09 2006-06-06 International Business Machines Corporation FET gate structure with metal gate electrode and silicide contact
US6974736B2 (en) 2004-01-09 2005-12-13 International Business Machines Corporation Method of forming FET silicide gate structures incorporating inner spacers
US7268058B2 (en) 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US7385247B2 (en) * 2004-01-17 2008-06-10 Samsung Electronics Co., Ltd. At least penta-sided-channel type of FinFET transistor
JP2005209782A (ja) 2004-01-21 2005-08-04 Toshiba Corp 半導体装置
US7250645B1 (en) * 2004-01-22 2007-07-31 Advanced Micro Devices, Inc. Reversed T-shaped FinFET
US7224029B2 (en) 2004-01-28 2007-05-29 International Business Machines Corporation Method and structure to create multiple device widths in FinFET technology in both bulk and SOI
KR100587672B1 (ko) 2004-02-02 2006-06-08 삼성전자주식회사 다마신 공법을 이용한 핀 트랜지스터 형성방법
EP1566844A3 (en) 2004-02-20 2006-04-05 Samsung Electronics Co., Ltd. Multi-gate transistor and method for manufacturing the same
US7060539B2 (en) * 2004-03-01 2006-06-13 International Business Machines Corporation Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
JP4852694B2 (ja) 2004-03-02 2012-01-11 独立行政法人産業技術総合研究所 半導体集積回路およびその製造方法
US6921691B1 (en) 2004-03-18 2005-07-26 Infineon Technologies Ag Transistor with dopant-bearing metal in source and drain
US7701018B2 (en) 2004-03-19 2010-04-20 Nec Corporation Semiconductor device and method for manufacturing same
KR100576361B1 (ko) 2004-03-23 2006-05-03 삼성전자주식회사 3차원 시모스 전계효과 트랜지스터 및 그것을 제조하는 방법
US7141480B2 (en) 2004-03-26 2006-11-28 Texas Instruments Incorporated Tri-gate low power device and method for manufacturing the same
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US8450806B2 (en) 2004-03-31 2013-05-28 International Business Machines Corporation Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby
US20050224797A1 (en) 2004-04-01 2005-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS fabricated on different crystallographic orientation substrates
US20050230763A1 (en) 2004-04-15 2005-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a microelectronic device with electrode perturbing sill
KR100642632B1 (ko) 2004-04-27 2006-11-10 삼성전자주식회사 반도체소자의 제조방법들 및 그에 의해 제조된 반도체소자들
US7084018B1 (en) 2004-05-05 2006-08-01 Advanced Micro Devices, Inc. Sacrificial oxide for minimizing box undercut in damascene FinFET
US20050255642A1 (en) 2004-05-11 2005-11-17 Chi-Wen Liu Method of fabricating inlaid structure
US6864540B1 (en) 2004-05-21 2005-03-08 International Business Machines Corp. High performance FET with elevated source/drain region
KR100625177B1 (ko) 2004-05-25 2006-09-20 삼성전자주식회사 멀티-브리지 채널형 모오스 트랜지스터의 제조 방법
US6955961B1 (en) 2004-05-27 2005-10-18 Macronix International Co., Ltd. Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution
KR100634372B1 (ko) 2004-06-04 2006-10-16 삼성전자주식회사 반도체 소자들 및 그 형성 방법들
WO2005122276A1 (ja) 2004-06-10 2005-12-22 Nec Corporation 半導体装置及びその製造方法
US7452778B2 (en) 2004-06-10 2008-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-wire devices and methods of fabrication
US7132360B2 (en) 2004-06-10 2006-11-07 Freescale Semiconductor, Inc. Method for treating a semiconductor surface to form a metal-containing layer
US7291886B2 (en) 2004-06-21 2007-11-06 International Business Machines Corporation Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs
KR100541657B1 (ko) 2004-06-29 2006-01-11 삼성전자주식회사 멀티 게이트 트랜지스터의 제조방법 및 이에 의해 제조된멀티 게이트 트랜지스터
US8669145B2 (en) * 2004-06-30 2014-03-11 International Business Machines Corporation Method and structure for strained FinFET devices
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US20060040054A1 (en) 2004-08-18 2006-02-23 Pearlstein Ronald M Passivating ALD reactor chamber internal surfaces to prevent residue buildup
US20060043500A1 (en) 2004-08-24 2006-03-02 Jian Chen Transistor structure with stress modification and capacitive reduction feature in a channel direction and method thereof
US7105934B2 (en) 2004-08-30 2006-09-12 International Business Machines Corporation FinFET with low gate capacitance and low extrinsic resistance
US7250367B2 (en) 2004-09-01 2007-07-31 Micron Technology, Inc. Deposition methods using heteroleptic precursors
US7071064B2 (en) * 2004-09-23 2006-07-04 Intel Corporation U-gate transistors and methods of fabrication
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7332439B2 (en) 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7247547B2 (en) 2005-01-05 2007-07-24 International Business Machines Corporation Method of fabricating a field effect transistor having improved junctions
US7875547B2 (en) 2005-01-12 2011-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Contact hole structures and contact structures and fabrication methods thereof
US7071047B1 (en) 2005-01-28 2006-07-04 International Business Machines Corporation Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions
US7470951B2 (en) 2005-01-31 2008-12-30 Freescale Semiconductor, Inc. Hybrid-FET and its application as SRAM
US20060172480A1 (en) 2005-02-03 2006-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Single metal gate CMOS device design
US20060180859A1 (en) 2005-02-16 2006-08-17 Marko Radosavljevic Metal gate carbon nanotube transistor
DE102005008478B3 (de) 2005-02-24 2006-10-26 Infineon Technologies Ag Verfahren zur Herstellung von sublithographischen Strukturen
US7238564B2 (en) 2005-03-10 2007-07-03 Taiwan Semiconductor Manufacturing Company Method of forming a shallow trench isolation structure
JP4825526B2 (ja) 2005-03-28 2011-11-30 株式会社東芝 Ｆｉｎ型チャネルトランジスタおよびその製造方法
US7177177B2 (en) 2005-04-07 2007-02-13 International Business Machines Corporation Back-gate controlled read SRAM cell
KR100699839B1 (ko) 2005-04-21 2007-03-27 삼성전자주식회사 다중채널을 갖는 반도체 장치 및 그의 제조방법.
US7429536B2 (en) 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7319074B2 (en) 2005-06-13 2008-01-15 United Microelectronics Corp. Method of defining polysilicon patterns
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US20070023795A1 (en) 2005-07-15 2007-02-01 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US7348642B2 (en) 2005-08-03 2008-03-25 International Business Machines Corporation Fin-type field effect transistor
US7352034B2 (en) 2005-08-25 2008-04-01 International Business Machines Corporation Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
US7339241B2 (en) 2005-08-31 2008-03-04 Freescale Semiconductor, Inc. FinFET structure with contacts
US7416943B2 (en) 2005-09-01 2008-08-26 Micron Technology, Inc. Peripheral gate stacks and recessed array gates
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US8513066B2 (en) 2005-10-25 2013-08-20 Freescale Semiconductor, Inc. Method of making an inverted-T channel transistor
US7638843B2 (en) 2006-05-05 2009-12-29 Texas Instruments Incorporated Integrating high performance and low power multi-gate devices
KR100718159B1 (ko) 2006-05-18 2007-05-14 삼성전자주식회사 와이어-타입 반도체 소자 및 그 제조 방법
US20080017890A1 (en) 2006-06-30 2008-01-24 Sandisk 3D Llc Highly dense monolithic three dimensional memory array and method for forming
US7456471B2 (en) 2006-09-15 2008-11-25 International Business Machines Corporation Field effect transistor with raised source/drain fin straps
US7646046B2 (en) 2006-11-14 2010-01-12 Infineon Technologies Ag Field effect transistor with a fin structure
CA2669704A1 (en) 2006-11-16 2008-05-22 Allergan, Inc. Sulfoximines as kinase inhibitors
US7678632B2 (en) 2006-11-17 2010-03-16 Infineon Technologies Ag MuGFET with increased thermal mass
US20080128797A1 (en) 2006-11-30 2008-06-05 International Business Machines Corporation Structure and method for multiple height finfet devices
US7655989B2 (en) 2006-11-30 2010-02-02 International Business Machines Corporation Triple gate and double gate finFETs with different vertical dimension fins
US20080212392A1 (en) 2007-03-02 2008-09-04 Infineon Technologies Multiple port mugfet sram
JP4406439B2 (ja) 2007-03-29 2010-01-27 株式会社東芝 半導体装置の製造方法

Cited By (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101228634B (zh) * 2005-07-27 2010-06-02 国际商业机器公司 虚拟体接触的三栅极及其制造方法
CN101673767B (zh) * 2006-03-31 2012-05-30 海力士半导体有限公司 具有增加的沟道面积的半导体器件及其制造方法
US7977749B2 (en) 2006-03-31 2011-07-12 Hynix Semiconductor Inc. Semiconductor device with increased channel area
US7977196B2 (en) 2006-03-31 2011-07-12 Hynix Semiconductor Inc. Semiconductor device with increased channel area and fabrication method thereof
CN101047206B (zh) * 2006-03-31 2010-04-07 海力士半导体有限公司 具有增加的沟道面积的半导体器件及其制造方法
US7638398B2 (en) 2006-03-31 2009-12-29 Hynix Semiconductor Inc. Semiconductor device with increased channel area and fabrication method thereof
CN101556922B (zh) * 2008-04-10 2010-07-28 北京大学 一种纳米环栅mosfet晶体管及其制备方法
CN102301482A (zh) * 2009-02-04 2011-12-28 国际商业机器公司 用于悬浮和细化纳米线的无掩模制程
CN102244102B (zh) * 2011-06-28 2013-06-12 复旦大学 一种基于电子隧穿的围栅型栅控金属-绝缘体器件
CN102244102A (zh) * 2011-06-28 2011-11-16 复旦大学 一种基于电子隧穿的围栅型栅控金属-绝缘体器件
CN103035708A (zh) * 2011-09-30 2013-04-10 中国科学院微电子研究所 一种半导体结构及其制造方法
CN103035708B (zh) * 2011-09-30 2015-11-25 中国科学院微电子研究所 一种半导体结构及其制造方法
CN102544010A (zh) * 2012-02-28 2012-07-04 上海华力微电子有限公司 双层隔离三维阵列式半导体纳米线mosfet
CN104246994A (zh) * 2012-04-17 2014-12-24 国际商业机器公司 具有鳍结构的半导体器件和形成具有鳍结构的半导体器件的方法
CN103811320B (zh) * 2012-11-09 2017-08-11 中国科学院微电子研究所 半导体器件及其制造方法
CN103811320A (zh) * 2012-11-09 2014-05-21 中国科学院微电子研究所 半导体器件及其制造方法
CN103855091B (zh) * 2012-12-03 2016-06-29 国际商业机器公司 半导体结构及其形成方法
CN103855091A (zh) * 2012-12-03 2014-06-11 国际商业机器公司 半导体结构及其形成方法
CN103022136A (zh) * 2012-12-26 2013-04-03 电子科技大学 一种t型栅结构的mos晶体管
CN103022136B (zh) * 2012-12-26 2015-09-30 电子科技大学 一种t型栅结构的mos晶体管
CN108109967A (zh) * 2013-04-04 2018-06-01 意法半导体公司 集成电路器件和制作技术
US11705458B2 (en) 2013-04-04 2023-07-18 Stmicroelectronics, Inc. Integrated circuit devices and fabrication techniques
CN105023846A (zh) * 2014-04-15 2015-11-04 台湾积体电路制造股份有限公司 在金属栅极线端中具有t形的器件和制造半导体器件的方法
US10115596B2 (en) 2014-04-15 2018-10-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating a semiconductor device having a T-shape in the metal gate line-end
CN110911275A (zh) * 2014-04-15 2020-03-24 台湾积体电路制造股份有限公司 在金属栅极线端中具有t形的器件和制造半导体器件的方法
US9780213B2 (en) 2014-04-15 2017-10-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a reversed T-shaped profile in the metal gate line-end
CN105390442A (zh) * 2014-08-28 2016-03-09 格罗方德半导体公司 于非平面输出晶体管的非平面静电放电装置及其共同制造
CN105405888A (zh) * 2014-09-11 2016-03-16 台湾积体电路制造股份有限公司 半导体结构及其制造方法
CN105405888B (zh) * 2014-09-11 2019-04-02 台湾积体电路制造股份有限公司 半导体结构及其制造方法
CN104465354A (zh) * 2014-12-24 2015-03-25 上海集成电路研发中心有限公司 全包围栅极结构及其制造方法
CN106158878A (zh) * 2014-12-31 2016-11-23 意法半导体公司 制作增强utbb fdsoi器件的方法和结构
CN106158878B (zh) * 2014-12-31 2019-07-16 意法半导体公司 制作增强utbb fdsoi器件的方法和结构
US11508825B2 (en) 2015-01-12 2022-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
CN105789306B (zh) * 2015-01-12 2020-12-08 台湾积体电路制造股份有限公司 半导体器件及其制造方法
US10714581B2 (en) 2015-01-12 2020-07-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
CN105789306A (zh) * 2015-01-12 2016-07-20 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN105845726A (zh) * 2015-01-14 2016-08-10 中国科学院微电子研究所 全包围栅场效应晶体管及其制造方法
US10553706B2 (en) 2015-02-13 2020-02-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing semiconductor fin structure with extending gate structure
US11217683B2 (en) 2015-02-13 2022-01-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with extending gate structure and method for forming the same
CN105895695A (zh) * 2015-02-13 2016-08-24 台湾积体电路制造股份有限公司 具有延伸的栅极结构的半导体结构及其形成方法
CN107068756B (zh) * 2015-11-30 2020-08-18 格罗方德半导体公司 通过栅极自对准结改进结分布的替代体finfet
CN107068756A (zh) * 2015-11-30 2017-08-18 格罗方德半导体公司 通过栅极自对准结改进结分布的替代体finfet
CN106711194B (zh) * 2016-12-28 2019-08-20 中国科学院微电子研究所 一种环栅场效应晶体管及其制备方法
CN106711194A (zh) * 2016-12-28 2017-05-24 中国科学院微电子研究所 一种环栅场效应晶体管及其制备方法
CN108074819A (zh) * 2017-12-18 2018-05-25 深圳市晶特智造科技有限公司 环栅型鳍式场效应晶体管及其制作方法
WO2021098546A1 (zh) * 2019-11-19 2021-05-27 北京元芯碳基集成电路研究院 一种碳纳米管器件及其制造方法

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WO2005010994A1 (en) 2005-02-03
US8273626B2 (en) 2012-09-25
TWI241718B (en) 2005-10-11
US20110020987A1 (en) 2011-01-27
US7820513B2 (en) 2010-10-26
AU2003301042A1 (en) 2005-02-14
EP1639649A1 (en) 2006-03-29
US20090061572A1 (en) 2009-03-05
EP2270868A1 (en) 2011-01-05
US7456476B2 (en) 2008-11-25
DE60335301D1 (de) 2011-01-20
US20060172497A1 (en) 2006-08-03
EP1639649B1 (en) 2010-12-08
EP2270868B1 (en) 2015-05-20

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