CN1527379A - 具有晶格不相称区的变形沟道晶体管结构及其制造方法 - Google Patents

具有晶格不相称区的变形沟道晶体管结构及其制造方法 Download PDF

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CN1527379A
CN1527379A CNA2003101038154A CN200310103815A CN1527379A CN 1527379 A CN1527379 A CN 1527379A CN A2003101038154 A CNA2003101038154 A CN A2003101038154A CN 200310103815 A CN200310103815 A CN 200310103815A CN 1527379 A CN1527379 A CN 1527379A
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unbecoming
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CN100345280C (zh
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杨育佳
林俊杰
李文钦
胡正明
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种具有晶格不相称区的变形沟道晶体管结构及其制造方法。此晶体管结构包括一具有变形沟道区的基底，该基底包含第一自然晶格常数的第一半导体材料，于一表面，一栅极介电层覆盖此变形沟道区，一栅极电极覆盖此栅极介电层，且一源极区与漏极区位于此变形沟道区的相对邻近处，此源极区与/或漏极区包含一晶格不相称区，该晶格不相称区包含第二自然晶格常数的第二半导体材料，此第二自然晶格常数与第一自然晶格常数相异。

Description

具有晶格不相称区的变形沟道晶体管结构及其制造方法
技术领域
本发明是有关于一种具有晶格不相称区的半导体组件及其制造方法，特别关于一种变形沟道晶体管结构及其制造方法。
背景技术
近十几年来，随着金氧半场效晶体管(metal-oxide-semiconductorfield effect transistor，MOSFET)尺寸的缩小，包括栅极长度与栅极氧化层厚度的缩小，已使得持续改善速度效能、密度与每单位IC(integrated circuits)成本成为可能。
为了更进一步提升晶体管的效能，可利用在晶体管沟道的应变(strain)来改善载子迁移率，以达到提升晶体管效能的目的，进而使组件比例缩小。以下介绍几个使沟道区应变的既有方法：
在一常见方法，如于1992年12月在加州旧金山InternationalElectron Devices Meeting所出版的J.Welser et al.中1000-1002页的“NMOS and PMOS transistors fabricated in strainedsilicon/relaxed silicon-germanium structures”所述，一松散硅锗(SiGe)缓冲层110用来做下方的沟道区126，如图1A所示；在图1B与图1C中，利用一相异晶格常数的简单区块来表示在缓冲层110里的松散硅锗层114与应变硅层130的横截面；在图1B中，区块135表示硅的自然晶格常数，该晶格常数比区块115硅锗的自然晶格常数小；在图1C中，当一磊晶硅薄膜(区块135)长在松散硅锗层114(区块115)上时，区块135中硅的单位晶格136会横向延伸，产生一二维拉伸应力，使该磊晶硅薄膜变成应变硅层130，如图1A所示。在图1A中，一晶体管长在该应变磊晶硅层130上，使沟道区126处于此二维拉伸应力中，此自然晶格常数为此半导体于常压室温下的晶格常数。此法中，松散硅锗层114是一位于沟道区126下的应力区(stressor)，该应力区使沟道区126产生应变，受一二维拉伸应力的硅沟道对整个晶体管中电子与电洞迁移率有很大提升。在上述方法中，磊晶硅层130在晶体管形成前就已应变，因此，之后CMOS的高温制程所可能产生的应变松散(strain relaxation)需特别注意；另外，由于硅锗缓冲层110的厚度是以微米的等级在成长，所以此法非常昂贵；此外，松散硅锗层114中存在许多脱格(dislocation)现象，有些还会增生到应变硅层130中，产生高缺陷密度，使晶体管效能受到负面影响。
在其它方法中，沟道区于晶体管形成后才应变。在此方法中，一高应力膜220形成于整个晶体管结构250上，如图2所示；作为应力区的高应力膜220对沟道区206产生重大影响，它使沟道区206晶格间隙(lattice spacing)改变且产生应变；在此例中，应力区位于整个晶体管结构250上方，详细的描述请参考A.Shimizu et al.，“Local mechanicalstress control(LMC)：a new technique for CMOS performanceenhancement”，pp.433-436 of the Digest of Technical Papers of the2001 International Electron Device Meeting；高应力膜220所产生的应变本质上被认为是与源极到漏极平行的一维方向，然而，在源极到漏极的一维拉伸应力应变减低了电洞迁移率，且一维压缩应力减低了电子迁移率；锗的离子植入被用来选择性地减轻该应变，使电洞或电子迁移率不会降低，但由于N与P沟道晶体管很靠近，所以此植入有困难。
发明内容
本发明的主要目的为提供一种具有变形沟道区的晶体管结构。
本发明的另一目的就是提供一种变形沟道晶体管结构，该结构靠近变形沟道区的部分源极区与/或漏极区为晶格不相称区，该晶格不相称区受沟道区影响。
本发明的另一目的就是提供一种变形沟道晶体管的制造方法。
为达上述目的，本发明提供一变形沟道晶体管极结构，包括一变形沟道区、一栅极介电层、一栅极电极与一源极区与漏极区；该基底包含一第一自然晶格常数的第一半导体材料、该栅极介电层位于变形沟道区上、栅极电极位于栅极介电层上、源极区与漏极区位于变形沟道区的相对邻近处，且源极区与/或漏极区包含一晶格不相称区，此区包含一第二自然晶格常数的第二半导体材料，此第二自然晶格常数与第一自然晶格常数相异。
本发明进一步提供一制造变形沟道晶体管的方法：首先一基底具有一沟道区，此基底包含一第一自然晶格常数的第一半导体材料；在一表面，栅极介电层位于此沟道区上，且一栅极电极位于此栅极介电层上，然后一第一源极区与漏极区形成于沟道区相对邻近处，接着一间隙壁形成于栅极电极侧壁，此间隙壁覆盖一部分基底表面，接着凹蚀掉未被间隙壁与栅极电极覆盖的基底表面，再将此凹蚀处以具有第二自然晶格常数的第二半导体材料填充，此第二自然晶格常数与第一自然晶格常数相异，形成一晶格不相称区，该区会使沟道区应变。最后，一第二源极区形成于第一源极区邻近处、一第二漏极区形成于第一漏极区邻近处，第二源极区与/或第二漏极区包含晶格不相称区。
本发明进一步提供另一种制造变形沟道晶体管的方法：首先一基底具有一沟道区，此基底包含一第一自然晶格常数的第一半导体材料；在一表面，栅极介电层位于此沟道区上、一栅极电极位于此栅极介电层上、一源极区与漏极区位于沟道区相对邻近处，且一间隙壁位于栅极电极侧壁，此间隙壁覆盖一部分基底表面，然后凹蚀源极区与/或漏极区，最后，以具第二自然晶格常数的第二半导体材料填充此凹蚀处，此第二自然晶格常数与第一自然晶格常数相异，形成一晶格不相称区，该区会使沟道区应变。
本发明进一步再提供另一种制造变形沟道晶体管的方法：首先一基底具有一沟道区，此基底包含一第一自然晶格常数的第一半导体材料；在一表面，栅极介电层位于此沟道区上、一栅极电极位于该栅极介电层上，且一间隙壁位于栅极电极侧壁，此间隙壁覆盖一部分基底表面，然后凹蚀未被间隙壁与栅极电极覆盖的基底表面，形成一凹蚀处，最后，一源极区与漏极区形成于沟道区相对邻近处，源极区与/或漏极区包含晶格不相称区。
本发明最后再进一步提供另一种制造变形沟道晶体管的方法：首先一基底具有一沟道区，此基底包含一半导体材料，在一表面，一栅极介电层位于该沟道区上、一栅极电极位于栅极介电层上、一源极区与漏极区位于沟道区相对邻近处，且一间隙壁位于栅极电极侧壁，该间隙壁覆盖一部分基底表面。最后，于源极区与/或漏极区植入一元素，该元素具有与此半导体材料相异的原子尺寸，形成一晶格不相称区，该区会使沟道应变。
本发明利用一种非常简单的结构与制造方法来增进在晶体管中沟道区的变形，进而增进晶体管中载子的迁移率；如此可增进晶体管的驱动电流，进而改进电路速度。
附图说明
图1A至图1C为一系列常见的应变硅晶体管剖面图，该晶体管具有一松弛硅锗层作为应力区，使磊晶硅层上方产生应变；
图2为另一常见的应变硅晶体管剖面图，用以说明利用一高应力膜的应力区使沟道应变；
图3A与图3B为一系列使用本发明实施例一的变形沟道晶体管结构的剖面图；
图4A至图4D为一系列使用本发明实施例二的变形沟道晶体管结构的剖面图；
图5为本发明变形沟道晶体管结构实施例三的详细流程图；
图6A至图6F为一系列使用本发明实施例三的变形沟道晶体管结构的制程步骤剖面图；
图7为本发明变形沟道晶体管结构实施例四的详细流程图；
图8A至图8D为一系列使用本发明实施例四的变形沟道晶体管结构的制程步骤剖面图；
图9为本发明变形沟道晶体管结构实施例五的详细流程图；
图10A至图10G为一系列使用本发明实施例五的变形沟道晶体管结构的制程步骤剖面图；
图11A至图11D为一系列使用本发明实施例六的变形沟道晶体管结构的制程步骤剖面图。
符号说明：
100、200、300a、300b、400、500、600、700、800：基底
110：硅化锗缓冲层
112：硅化锗缓冲层下方
114：硅化锗缓冲层上方
115：硅化锗区块
122、202：漏极
124、204：源极
126、206、506、606、706、806：沟道区
130：应变硅层
135：硅区块
136：硅的单位晶格
142、214、314a、314b、414、514、614、714、814：栅极电极
T：张力
212、312a、312b、412、512、612、712、812：栅极介电层
216、316a、316b、416、516、616、715、716、816：间隙壁
220：高应力膜
250：晶体管结构
3a、3b、4a、4b、4c、4d、5、6、7、8：变形沟道晶体管结构
301a、301b、401、501、601、701、801：漏极延伸区
302a、302b、402、502、602、702、802：深漏极区
303a、303b、403、503、603、703、803：源极延伸区
304a、304b、404、504、604、704、804：深源极区
305a、305b、405a、405b、405c、405d、505、605、705、805：晶格不相称区
306a、306b、406a、406b、406c、406d、506’、606’、706’、806’：变形沟道区
307a、307b、407、507、607、707、807：漏极区
308a、308b、408、508、608、708、808：源极区
C1：源极至漏极方向的压缩应力
T1：垂直方向的拉伸应力
C2：垂直方向的压缩应力
T2：源极至漏极方向的拉伸应力
420、520、620、720、820：传导层
509、609、709：凹蚀处
d：凹蚀处的深度
622、722：硅盖层
830：植入离子
具体实施方式
为让本发明的上述和其它目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合所附图式，作详细说明如下：
实施例一：
在本发明的实施例一中，将讨论运用于变形沟道区的两种应力型式。
在图3A中，一变形沟道晶体管结构3a剖面图表示本发明实施例一：基底300a表面有一变形沟道区306a，该基底包含一半导体材料；栅极介电层312a位于变形沟道区306a上，此层最好的厚度约为3至100埃；栅极电极314a位于栅极介电层312a上；间隙壁316a位于栅极电极314a侧壁，且覆盖一部分基底300a表面；漏极区307a包括漏极延伸区301a与深漏极区302a、源极区308a包括源极延伸区303a与深源极区304a，漏极区与源极区位于变形沟道区306a的相对邻近处；晶格不相称区305a包含另一种半导体材料，此半导体材料的自然晶格常数与基底300a的自然晶格常数相异，且位于深漏极区302a与/或深源极区304a，因此，变形沟道区306a会被不同晶格常数的变形沟道区306a与晶格不相称区305a所应变。
在本发明实施例一中，在变形沟道晶体管结构3a里，基底300a最好包含自然晶格常数约为5.431埃的硅，且晶格不相称区305a最好包含一自然晶格常数最好约在5.431至5.657埃间的合金半导体材料，如硅锗合金，此常数与锗在硅锗合金中的浓度相关，且大于基底300a的自然晶格常数；在本发明实施例一中，晶格不相称区的锗在硅锗合金中的莫耳比(mole fraction)最好约为0.1至0.9，使晶格不相称区305a成为一应力区，于变形沟道区3 06a中产生一源极至漏极方向的压缩应力C1与一垂直方向的拉伸应力T1，使变形沟道区306a处于一源极至漏极方向的压缩应力与垂直方向的拉伸应力中。当此变形沟道晶体管结构3a为P沟道时，变形沟道区306a的电洞迁移率显著增加，而使驱动电流(drive current)提升。
在图3B中，3b为本发明实施例一的变形沟道晶体管结构的剖面图。基底300b表面有一变形沟道区306b，此基底包含一半导体材料；栅极介电层312b位于变形沟道区306b上，该层厚度最好约为3至100埃；栅极电极314b位于栅极介电层312b上；间隙壁316b位于栅极电极314b侧壁，覆盖一部分基底300b表面；漏极区307b包含漏极延伸区301b与深漏极区302b、源极区308b包含源极延伸区303b与深源极区304b，该漏极区与源极区位于变形沟道区306b的相对邻近处；晶格不相称区305b位于深漏极区与/或深源极区，此区包括另一种半导体材料，其自然晶格常数与基底300b的相异，因此，变形沟道区306b会被不同晶格系数的变形沟道区306b与晶格不相称区305b所应变。
在本发明实施例一的变形沟道晶体管结构3b中，基底300b最好包含硅与晶格不相称区305b，该区最好包含一合金半导体材料，如一碳硅合金，且该半导体材料的自然晶格常数比基底300b小。在本发明实施例一中，晶格不相称区的碳在硅碳合金中的莫耳比(mole fraction)最好约为0.01至0.04，使晶格不相称区305b成为一应力区，于变形沟道区306b中产生一源极至漏极方向的拉伸应力C2与一垂直方向的压缩应力T2，使变形沟道区306b处于一源极至漏极方向的拉伸应力与垂直方向的压缩应力中。当此变形沟道晶体管结构3b为N沟道时，变形沟道区306b的电子迁移率显著增加，而使驱动电流提升，再者，晶格不相称区可能包含锗，成为一硅锗碳合金，其中碳的莫耳比要大于十倍的锗。
另外，在图3A的变形沟道区306a与图3B的变形沟道区306b中，其压缩应变与张力应变约为0.1％至4％，最好约为1％至4％；图3A的晶格不相称区305a与图3B的晶格不相称区305b的厚度约为10至1000埃；在图3A的变形沟道区306a与图3B的变形沟道区306b中，其压缩应变与张力应变是与晶格不相称区306a与306b的晶格常数、厚度及在漏极区307a与/或源极区308a中的位置，且晶格不相称区306b位于漏极区307b与/或源极区308b中。
实施例二：
在本发明实施例二中，将讨论位于漏极区与/或源极区不同位置的晶格不相称区。在图4A至图4D中，基底400上方有变形沟道晶体管结构4a至4d、漏极延伸区401、深漏极区402、漏极区407、源极延伸区403、深源极区404、源极区408、晶格不相称区405a/405b/405c/405d、变形沟道区406a/406b/406c/406d、栅极介电层412、栅极电极414与间隙壁416。若叙述与本发明实施例一相同者则省略。
在图4A中，晶格不相称区405a位于靠近漏极区407与/或源极区408表面，并未延伸到漏极延伸区401与/或源极延伸区403；在图4B中，晶格不相称区405b凸出漏极区407与/或源极区408表面，形成一凸起的漏极区407b与凸起的源极区408b；在图4C中，晶格不相称区405c位于靠近漏极区407与/或源极区408表面，且进一步延伸到漏极延伸区401与/或源极延伸区403；在图4D中，晶格不相称区405d位于漏极区407与/或源极区408表面更深处，且更延伸到变形沟道区406d、漏极延伸区401与/或源极延伸区403下方。另外，位于漏极区与/或源极区的晶格不相称区的位置与本发明实施例一相符，并非意谓对此限制，熟习此技艺者，可视需要根据本发明进一步调整晶格不相称区的位置。
在图4A至图4D中，一传导层420，如硅、金属、金属硅化物或前述的组合，在变形沟道晶体管结构4a、4c与4d的漏极区与/或源极区与变形沟道晶体管结构4b的凸出漏极区与/或凸出源极区表面随意地形成。
此外在图4C中，由于晶格不相称区405c更靠近变形沟道区406c，使晶格不相称区405c施加更多应变于变形沟道区406c，改善了变形沟道结构4c中的电子或电洞迁移率。
实施例三：
在本发明实施例三中，将描述一变形沟道晶体管结构的制造方法，图5为此实施例的流程图，之后本实施例的描述会依图5的顺序进行。
在图6A中，一半导体基底如一硅基底500被提供，硅基底500包括一事先形成的多重隔离区(未表示于图上)，以及事先定义的多重组件区(未表示于图上)。例如，此隔离区可能为浅沟隔离区(shallow trenchisolation)。图6A至图6F提供一系列单一组件区的剖面图，使描述更加容易。硅基底500于一主动区表面包含一沟道区506。当图6E中的变形沟道晶体管结构5为P沟道晶体管结构时，硅基底500即为N型掺杂；若变形沟道晶体管结构5为N沟道晶体管结构，硅基底500即为P型掺杂。
在图6B中，一栅极介电层512形成于沟道区506上，而后一栅极电极514形成于此栅极介电层512上，栅极介电层是由热氧化法、热氧化法再经氮化处理法、化学气相沉积法、物理气相沉积法如溅镀或其它已知技术所形成；栅极介电层512可以是二氧化硅、氮氧化硅(siliconoxynitride)或前述组合物，其厚度约在3至100埃间，最好约为10埃或更少；栅极介电层512可能为一高介电常数(high-k)物质，如氧化铝(Al2O3)、氧化铪(HfO2)、氧化锆(ZrO2)、氮氧化铪(HfON)、硅酸铪(HfSiO4)、硅酸锆(ZrSiO4)、氧化镧(La2O3)或前述的组合，此栅极介电层的厚度相当于约3埃至100埃的氧化物。栅极电极514为多晶硅、多晶硅锗、耐火金属如钼或钨、化合物如氮化钛、前述的组合物或其它传导性物质；植入被用以改变栅极电极514的功函数，被认为是种功函数的植入；栅极电极514是借沉积栅极电极材料层(未表示于图上)于基底500上，再沉积一栅极罩(gate mask)(未表示于图上)于栅极电极材料层上，而后按栅极罩来定义栅极电极514，并蚀刻此栅极电极材料层来形成栅极电极514且将栅极罩去除；在电性上，栅极电极514与沟道区506用栅极介电层512区隔；在本发明实施例三中，栅极介电层512最好为氮氧化硅、栅极电极514最好为多晶硅，则用氯与溴化学法蚀刻可得高蚀刻选择比。
在图6C中，于基底500的主动区表面，一漏极延伸区501与源极延伸区503形成于沟道区506相对邻近处，且间隙壁516形成于栅极电极514侧壁，此间隙壁覆盖一部分漏极延伸区501与源极延伸区503，此漏极延伸区501与源极延伸区503是借由离子植入、电浆浸入式离子植入(PIII)或其它已知的技术所形成；间隙壁516的形成，最好是借沉积一间隙壁材料层(未表示于图上)如氮化硅或氧化硅及选择性地蚀刻此间隙壁材料层来形成；在本发明实施例三中，间隙壁材料为氮化硅。
在图6D中，在一部分或全部未被栅极介电层512与间隙壁516覆盖的基底500的主动区表面上，借由氯与溴化学法电浆蚀刻凹蚀，使形成一深度至少为d的凹蚀处509，此深度d约为50埃至1000埃。为了一之后的磊晶制程，可利用一非必须的回火步骤来促进硅的迁移率，修补因蚀刻而造成凹蚀处509的缺陷，使此凹蚀处509平滑，此回火步骤所使用的气体包含氮、氩、氖、氦、氢、氧与上述的组合物。
在图6E中，凹蚀处509被填充一半导体材料，如硅锗合金或碳硅合金，形成一晶格不相称区505，而后一深漏极区502形成于漏极延伸区501的邻近处、一深源极区504形成于源极延伸区503的邻近处，深漏极区502与漏极延伸区501结合形成漏极区507、深源极区504与源极延伸区503结合形成源极区508，漏极区507与/或源极区508包含晶格不相称区505；当晶格不相称区505形成时，沟道区506被应变，形成一变形沟道区506’；至此，本发明实施例三的变形沟道晶体管结构5基本上已形成。晶格不相称区505是借磊晶制程所形成，如化学气相沉积、超高真空化学气相沉积或分子束磊晶。当变形沟道晶体管结构5为P沟道晶体管结构时，此晶格不相称区505为硅锗合金，其中锗在此合金所占的莫耳比约为0.1至0.9；当变形沟道晶体管结构5为N沟道晶体管结构时，此晶格不相称区505为碳硅合金，其中碳在此合金所占的莫耳比约为0.01至0.04，且可能更进一步包含锗，形成碳硅锗合金，此合金锗的莫耳比小于十倍的碳。利用磊晶制程，一硅盖层522可随意地于晶格不相称区505形成，如化学气相沉积、超高真空化学气相沉积或分子束磊晶；在此磊晶制程中，晶格不相称区505与非必须的硅盖层522可能同时掺杂或未掺杂，当未掺杂时，之后它们掺杂可利用快速热回火制程(rapidthermal annealing process)来掺杂活化的掺质(dopants)。深漏极区502与深源极区504借离子植入、电浆浸入式离子植入、气相或固相源扩散或其它已知技术形成。当形成晶格不相称区505、硅盖层522、深漏极区502与深源极区504时，一回火步骤可进一步使植入缺陷与非结晶化(amorphization)恢复，此回火步骤所使用的气体包含氮、氩、氖、氦、氢、氧与上述的组合物。
在图6F中，一传导层520随意地形成于晶格不相称区505与/或漏极区507/源极区508上，使漏极区507与源极区508的电阻值降低；传导层520是利用自行对准金属硅化物(self-aligned silicide)或其它金属沉积制程所形成。护层(passivation layers)和组件接触窗(contacts)随后形成，使本发明实施例三的变形沟道晶体管结构5的组件完成。
实施例四：
在本发明实施例四中，将描述一变形沟道晶体管结构的制造方法，此晶体管的晶格不相称区不会延伸到漏极延伸区与/或源极延伸区。图7为此实施例的流程图，之后的描述会依图7的顺序进行。
在图8A中，一半导体基底如一硅基底600被提供，硅基底600包括一事先形成的多重隔离区(未表示于图上)及事先定义的多重组件区(未表示于图上)，例如此隔离区可能为浅沟隔离区。图8A至图8D提供一系列单一组件区的剖面图，使描述更加容易。硅基底600包含一常见的晶体管结构，此结构于基底600的主动区表面包含一沟道区606、一位于沟道区606上的栅极介电层612、一位于栅极介电层612上的栅极电极614、一位于沟道区606相对邻近处的源极区608与漏极区607，且一位于栅极电极614侧壁的间隙壁616，且此间隙壁覆盖部分基底600的主动区表面。漏极区607包含一漏极延伸区601与一深漏极区602、源极区608包含一源极延伸区603与一深源极区604。在图8C中，当变形沟道晶体管结构6为P沟道晶体管结构时，硅基底600即为N型掺杂；当变形沟道晶体管结构6为N沟道晶体管结构时，则为P型掺杂。
在图8B中，在一部分或全部未被栅极介电层612与间隙壁616覆盖的基底600的主动区表面，借由氯与溴化学法电浆蚀刻凹蚀，使形成一深度至少为d的凹蚀处609，此深度d约为50埃至1000埃。为了一之后的磊晶制程，可利用一非必须的回火步骤来促进硅的迁移率，修补因蚀刻而造成凹蚀处609的缺陷，使此凹蚀处609平滑，此回火步骤所使用的气体包含氮、氩、氖、氦、氢、氧与上述的组合物。
在图8C中，凹蚀处609被填充一半导体材料，如硅锗合金或碳硅合金，形成一晶格不相称区605；漏极区607与/或源极区608包含晶格不相称区605；当晶格不相称区605形成时，沟道区606被应变，形成一变形沟道区606’；至此，本发明实施例四的变形沟道晶体管结构6基本上已形成。晶格不相称区605会凸出漏极区607与/或源极区608表面，形成一凸起的漏极区与凸起的源极区；晶格不相称区605是借磊晶制程所形成，如化学气相沉积、超高真空化学气相沉积或分子束磊晶。当变形沟道晶体管结构6为P沟道晶体管结构时，此晶格不相称区605为硅锗合金，其中锗在此合金所占的莫耳比约为0.1至0.9；当变形沟道晶体管结构6为N沟道晶体管结构时，此晶格不相称区605为碳硅合金，其中碳在此合金所占的莫耳比约为0.01至0.04，且可能更进一步包含锗，形成碳硅锗合金，此合金锗的莫耳比小于十倍的碳。利用磊晶制程，如化学气相沉积、超高真空化学气相沉积或分子束磊晶，一硅盖层622可随意地于晶格不相称区605形成。晶格不相称区605与非必须的硅盖层622在此磊晶制程中同时掺杂。
在图8D中，一传导层620随意地形成于晶格不相称区605与/或漏极区607/源极区608上，使漏极区607与源极区608的电阻值降低，传导层620是利用自行对准金属硅化物或其它金属沉积制程所形成。护层和组件接触窗随后形成，使本发明实施例四的变形沟道晶体管结构6的组件完成。
实施例五：
在本发明实施例五中，将描述一变形沟道晶体管结构的制造方法。此晶体管的晶格不相称区会延伸到漏极延伸区与/或源极延伸区。图9为此实施例的流程图，之后的描述会依图9的顺序进行。
在图10A中，一半导体基底如一硅基底700被提供，硅基底700包括一事先形成的多重隔离区(未表示于图上)及事先定义的多重组件区(未表示于图上)，例如此隔离区可能为浅沟隔离区。图10A至图10G提供一系列单一组件区的剖面图，使描述更加容易。硅基底700包含一于主动区表面的沟道区706。图10D中，当变形沟道晶体管结构7为P沟道晶体管结构时，硅基底700即为N型掺杂；当变形沟道晶体管结构7为N沟道晶体管结构时，则为P型掺杂。
在图10B中，首先一栅极介电层712形成于沟道区706上，且一栅极电极714形成于栅极介电层712上，最后间隙壁715形成于栅极电极714侧壁，且此间隙壁覆盖部分基底700的主动区表面。栅极介电层712是由热氧化法、热氧化法再经氮化处理法、化学气相沉积法、物理气相沉积法如溅镀或其它已知技术所形成；栅极介电层712可以是二氧化硅、氮氧化硅或前述组合物，其厚度约在3至100埃间，最好约为10埃或更少；栅极介电层712可能为一高介电常数物质，如氧化铝、氧化铪、氧化锆、氮氧化铪、硅酸铪、硅酸锆、氧化镧或前述的组合，此栅极介电层的厚度相当于约3埃至100埃的氧化物。栅极电极714为多晶硅、多晶硅锗、耐火金属如钼或钨、化合物如氮化钛、前述的组合物或其它传导性物质；植入被用以改变栅极电极714的功函数，被认为是种功函数的植入；栅极电极714是借沉积栅极电极材料层(未表示于图上)于基底700上，再沉积一栅极罩(未表示于图上)于栅极电极材料层上，而后按栅极罩来定义栅极电极714，并蚀刻此栅极电极材料层来形成栅极电极714且将栅极罩去除；在电性上，栅极电极714与沟道区706用栅极介电层712区隔；在本发明实施例五中，栅极介电层712最好为氮氧化硅、栅极电极714为多晶硅，则用氯与溴化学法蚀刻可得高蚀刻选择比。为了保护之后磊晶步骤栅极电极714的侧壁，间隙壁715是利用沉积与非等向性蚀刻技术形成。
在图10C中，在一部分或全部未被栅极介电层712与间隙壁715覆盖的基底700的主动区表面上，借由氯与溴化学法电浆蚀刻凹蚀，使形成一深度为d的凹蚀处，此深度d约为50埃至1000埃。为了一之后的磊晶制程，可利用一非必须的回火步骤来促进硅的迁移率，修补因蚀刻而造成凹蚀处709的缺陷，使此凹蚀处709平滑，此回火步骤所使用的气体包含氮、氩、氖、氦、氢、氧与上述的组合物。
在图10D中，凹蚀处709被填充一半导体材料，如硅锗合金或碳硅合金，形成一晶格不相称区705，之后一漏极延伸区701与源极延伸区703于变形沟道区706’相对邻近处形成，至此，本发明实施例五的变形沟道晶体管结构7基本上已形成。晶格不相称区705是借磊晶制程所形成，如化学气相沉积、超高真空化学气相沉积或分子束磊晶。当晶格不相称区705形成时，沟道区706被应变，形成一变形沟道区706’。当变形沟道晶体管结构7为P沟道晶体管结构时，此晶格不相称区705为硅锗合金，其中锗在此合金所占的莫耳比约为0.1至0.9；当变形沟道晶体管结构7为N沟道晶体管结构时，此晶格不相称区705为碳硅合金，其中碳在此合金所占的莫耳比约为0.01至0.04，且可能更进一步包含锗，形成碳硅锗合金，此合金锗的莫耳比小于十倍的碳。利用磊晶制程，如化学气相沉积、超高真空化学气相沉积或分子束磊晶，一硅盖层722可随意地于晶格不相称区705形成。当在磊晶制程中，晶格不相称区705与非必须的硅盖层722未掺杂，但之后的掺杂可用快速热回火制程活化掺质。漏极延伸区701与/或源极延伸区703包含晶格不相称区705与非必须的硅盖层722。
在图10E中，一间隙壁716覆盖形成于原间隙壁715上，间隙壁716是借沉积与选择性蚀刻一间隙壁材料(未表示于图上)所形成，此间隙壁材料为氮化硅或二氧化硅；在本发明实施例五中，间隙壁716为氮化硅。
在图10F中，一深漏极区702形成于漏极延伸区701的邻近处，且深源极区704形成于源极延伸区703的邻近处。当晶格不相称区705有效时，深漏极区702会与漏极延伸区701结合，且不必须的盖层722有效时，会形成漏极区707；当晶格不相称区705有效时，深源极区704会与源极延伸区703结合，且不必须的盖层722有效时，会形成源极区708。深漏极区702与深源极区704借离子植入、电浆浸入式离子植入、气相或固相源扩散或其它已知技术形成。
在图10G中，一传导层720随意地形成于漏极区707与源极区708上，使漏极区707与源极区708的电阻值降低；传导层720是利用自行对准金属硅化物或其它金属沉积制程所形成。护层和组件接触窗随后形成，使本发明实施例五的变形沟道晶体管结构7的组件完成。
实施例六：
在本发明实施例六中，将描述一利用离子植入制程来形成变形沟道晶体管结构中晶格不相称区的制造方法。
在图11A中，一半导体基底如一硅基底800被提供，硅基底800包括一事先形成的多重隔离区(未表示于图上)及事先定义的多重组件区(未表示于图上)，例如此隔离区可能为浅沟隔离区。图11A至图11D提供一系列单一组件区的剖面图，使描述更加容易。硅基底800包含一常见的晶体管结构，该晶体管结构包含一沟道区806，该区位于基底800的主动区表面；一栅极介电层812位于沟道区806上、一栅极电极814位于栅极介电层812上、一源极808与漏极807位于沟道区806相对邻近处，且一间隙壁816位于栅极电极814侧壁，且此间隙壁覆盖部分基底800的主动区表面。漏极区807包含一漏极延伸区801与深漏极区802、源极区808包含一源极延伸区803与深源极区804。在图11C中，当变形沟道晶体管结构8为P沟道晶体管结构时，硅基底700即为N型掺杂；当变形沟道晶体管结构8为N沟道晶体管结构时，则为P型掺杂。
在图11B中，一离子植入制程用来将离子830植入漏极区807与/或源极区808中，此被植入离子为一种或多种原子，此原子的半径与基底800不同；在此离子植入制程进行时，栅极电极814与间隙壁816可作为一植入罩(implantation mask)，间隙壁816的厚度可视晶格不相称区805是否延伸入漏极延伸区801与/或源极延伸区803来做调整。
在图11C中，对基底800做回火，使晶格不相称区形成于漏极区807与/或源极区808，故漏极区807与/或源极区808包括晶格不相称区。当晶格不相称区805形成时，沟道区806被应变，形成一变形沟道区806’。至此，本发明实施例六的变形沟道晶体管结构8基本上已形成。当变形沟道晶体管结构8为P沟道晶体管结构时，此晶格不相称区805为硅锗合金，其中锗在此合金所占的莫耳比约为0.1至0.9；当变形沟道晶体管结构8为N沟道晶体管结构时，此晶格不相称区805为碳硅合金，其中碳在此合金所占的莫耳比约为0.01至0.04，且可能更进一步包含锗，形成碳硅锗合金，此合金锗的莫耳比小于十倍的碳。
在图11D中，一传导层820随意地形成于漏极区807与源极区808上，使漏极区807与源极区808的电阻值降低；传导层820是利用自行对准金属硅化物或其它金属沉积制程所形成。护层和组件接触窗随后形成，使本发明实施例六的变形沟道晶体管结构8的组件完成。

Claims (51)

1.一种具有晶格不相称区的变形沟道晶体管结构，其特征在于所述变形沟道晶体管结构包括：
一变形沟道区，包括具有第一自然晶格常数的第一半导体材料；
一覆盖该变形沟道区的栅极介电质层；
一覆盖该栅极介电质层的栅极电极；以及
一源极区与漏极区位于该变形沟道区相对相邻处，该源极与/或漏极包含一晶格不相称区，该晶格不相称区包括具有第二自然晶格常数的第二半导体材料，该第二自然晶格常数与该第一自然晶格常数相异。
2.根据权利要求1所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：该晶格不相称区域的厚度为10至1000埃。
3.根据权利要求1所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：该第一半导体材料包括硅。
4.根据权利要求1所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：该第二半导体材料包括硅与锗。
5.根据权利要求1所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：该第二半导体材料包括硅与碳。
6.根据权利要求4所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：锗在该第二半导体材料中所占的莫耳比为0.1至0.9。
7.根据权利要求5所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：碳在该第二半导体材料中所占的莫耳比为0.01至0.04。
8.根据权利要求5所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：该第二半导体材料尚包括锗，且在该第二半导体中，锗的莫耳比小于十倍的碳。
9.根据权利要求1所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：该变形沟道区受一源极至漏极方向的拉伸应力与一垂直方向的压缩应力作用。
10.根据权利要求9所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：该拉伸应力为0.1％至4％且压缩应力为0.1％至4％。
11.根据权利要求1所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：该变形沟道区受源极至漏极方向的压缩应力与垂直方向的拉伸应力作用。
12.根据权利要求11所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：该压缩应力为0.1％至4％且拉伸应力为0.1％至4％。
13.根据权利要求1所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：尚包含一位于该晶格不相称区的覆盖层。
14.根据权利要求13所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：该覆盖层包含该第一半导体材料。
15.根据权利要求1所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：该源极区包含一源极延伸区与一深源极区，且漏极区包含一漏极延伸区与一深漏极区。
16.根据权利要求15所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：该晶格不相称区域横向延伸至源极延伸区与/或漏极延伸区。
17.根据权利要求1所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：该晶格不相称区域进一步延伸超过该源极延伸区与/或漏极延伸区。
18.根据权利要求1所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：该栅极介电质层的相对介电常数大于5。
19.根据权利要求1所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：该栅极介电质层的厚度为3至100埃。
20.根据权利要求1所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：该栅极电极包括多晶硅或多晶硅锗。
21.根据权利要求1所述的具有晶格不相称区的变形沟道晶体管结构，其特征在于：该源极区与漏极区表面尚包括一层导电物质。
22.一种具有晶格不相称区的变形沟道晶体管的制造方法，包括：
提供一基底，该基底具有第一自然晶格常数的第一半导体材料、一栅极介电层位于该基底上、一栅极电极位于该栅极介电层上、一源极区与漏极区位于该栅极介电层相对相邻处以及一间隙壁位于该栅极电极侧壁；
凹蚀该源极区与/或漏极区，形成一凹蚀处；以及
以一具有第二自然晶格常数的第二半导体材料填充该凹蚀处，形成一晶格不相称区，该第二自然晶格常数与该第一自然晶格常数相异。
23.根据权利要求22所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该源极区包括源极延伸区与/或深源极区。
24.根据权利要求22所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该漏极区包括漏极延伸区与/或深漏极区。
25.根据权利要求22所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该晶格不相称区位于深源极区与/或深漏极区。
26.根据权利要求22所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该间隙壁包括一间隙壁，或一第一间隙壁与一第二间隙壁。
27.根据权利要求22所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该第一半导体材料包括硅。
28.根据权利要求22所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该第二半导体材料包括硅与锗。
29.根据权利要求22所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该第二半导体材料包括硅与碳。
30.根据权利要求28所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中锗在该第二半导体材料中所占的莫耳比为0.1至0.9。
31.根据权利要求29所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中碳在该第二半导体材料中所占的莫耳比为0.01至0.4。
32.根据权利要求29所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该第二半导体材料尚包括锗；且在该第二半导体中，锗的莫耳比小于十倍的碳。
33.根据权利要求22所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该凹蚀处是由电浆蚀刻所形成。
34.根据权利要求22所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该凹蚀处的深度为50至1000埃。
35.根据权利要求22所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中更包括在凹蚀后对该基底做回火处理。
36.根据权利要求22所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中更包括形成覆盖层于该第二半导体材料。
37.根据权利要求36所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该覆盖层包括第一半导体材料。
38.根据权利要求22所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该栅极介电层的相对介电常数大于5。
39.根据权利要求22所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该栅极介电质层的厚度为3至100埃。
40.根据权利要求22所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该栅极电极包括多晶硅或多晶硅锗。
41.根据权利要求22所述的具有晶格不相称区的变形沟道晶体管的制造方法，尚包括在该源极区与漏极区表面形成一层导电物质。
42.一种具有晶格不相称区的变形沟道晶体管的制造方法，包括：
提供一基底，该基底包括一半导体材料、一栅极介电层位于该基底上、一栅极电极位于该栅极介电层上、且一源极区与漏极区位于该栅极介电层相对相邻处；以及
植入一元素于该源极区与/或漏极区，形成一晶格不相称区，该元素具有与该半导体材料相异的原子半径。
43.根据权利要求42所述的具有晶格不相称区的变形沟道晶体管的制造方法，该基底在植入该元素后尚包括回火步骤。
44.根据权利要求42所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该第一半导体材料包括硅。
45.根据权利要求42所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该元素为锗。
46.根据权利要求42所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该元素为碳。
47.根据权利要求42所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中锗在该晶格不相称区中所占的莫耳比为0.1至0.9。
48.根据权利要求46所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中碳在该晶格不相称区中所占的莫耳比为0.01至0.4。
49.根据权利要求42所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该栅极介电层的相对介电常数大于5。
50.根据权利要求42所述的具有晶格不相称区的变形沟道晶体管的制造方法，其中该栅极介电质层的厚度为3至100埃。
51.根据权利要求42所述的具有晶格不相称区的变形沟道晶体管的制造方法，尚包括在该源极区与漏极区表面形成一层导电物质。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7459382B2 (en) 2006-03-24 2008-12-02 International Business Machines Corporation Field effect device with reduced thickness gate
CN100477123C (zh) * 2005-04-18 2009-04-08 株式会社东芝 用于减小多晶硅高度的SOI底部预掺杂合并e-SiGe
CN100568467C (zh) * 2003-08-28 2009-12-09 国际商业机器公司 一种mosfet器件及其形成方法
CN101573795B (zh) * 2007-01-04 2011-05-11 国际商业机器公司 一种制造半导体结构的方法
CN103187447A (zh) * 2011-12-31 2013-07-03 中芯国际集成电路制造(上海)有限公司 Pmos晶体管结构及其制造方法

Families Citing this family (135)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6830976B2 (en) 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US7301180B2 (en) 2001-06-18 2007-11-27 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
US6916727B2 (en) * 2001-06-21 2005-07-12 Massachusetts Institute Of Technology Enhancement of P-type metal-oxide-semiconductor field effect transistors
US6730551B2 (en) * 2001-08-06 2004-05-04 Massachusetts Institute Of Technology Formation of planar strained layers
US7138649B2 (en) * 2001-08-09 2006-11-21 Amberwave Systems Corporation Dual-channel CMOS transistors with differentially strained channels
US6974735B2 (en) 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices
WO2003017336A2 (en) * 2001-08-13 2003-02-27 Amberwave Systems Corporation Dram trench capacitor and method of making the same
US6831292B2 (en) 2001-09-21 2004-12-14 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US6933518B2 (en) 2001-09-24 2005-08-23 Amberwave Systems Corporation RF circuits including transistors having strained material layers
WO2003105204A2 (en) * 2002-06-07 2003-12-18 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US6946371B2 (en) 2002-06-10 2005-09-20 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
US6982474B2 (en) 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
US6703648B1 (en) * 2002-10-29 2004-03-09 Advanced Micro Devices, Inc. Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication
US20040154083A1 (en) * 2002-12-23 2004-08-12 Mcvicker Henry J. Sports pad closure system with integrally molded hooks
EP1602125B1 (en) * 2003-03-07 2019-06-26 Taiwan Semiconductor Manufacturing Company, Ltd. Shallow trench isolation process
US6900502B2 (en) * 2003-04-03 2005-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel on insulator device
US6882025B2 (en) * 2003-04-25 2005-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Strained-channel transistor and methods of manufacture
US6867433B2 (en) 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US6927414B2 (en) * 2003-06-17 2005-08-09 International Business Machines Corporation High speed lateral heterojunction MISFETs realized by 2-dimensional bandgap engineering and methods thereof
US7208362B2 (en) * 2003-06-25 2007-04-24 Texas Instruments Incorporated Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US20050012087A1 (en) * 2003-07-15 2005-01-20 Yi-Ming Sheu Self-aligned MOSFET having an oxide region below the channel
US6936881B2 (en) * 2003-07-25 2005-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor that includes high permittivity capacitor dielectric
US7078742B2 (en) 2003-07-25 2006-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel semiconductor structure and method of fabricating the same
US6891192B2 (en) * 2003-08-04 2005-05-10 International Business Machines Corporation Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
US7101742B2 (en) * 2003-08-12 2006-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel complementary field-effect transistors and methods of manufacture
US20050035410A1 (en) * 2003-08-15 2005-02-17 Yee-Chia Yeo Semiconductor diode with reduced leakage
US7112495B2 (en) 2003-08-15 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
US20050035369A1 (en) * 2003-08-15 2005-02-17 Chun-Chieh Lin Structure and method of forming integrated circuits utilizing strained channel transistors
US7071052B2 (en) * 2003-08-18 2006-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Resistor with reduced leakage
US7303949B2 (en) * 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
US7138320B2 (en) * 2003-10-31 2006-11-21 Advanced Micro Devices, Inc. Advanced technique for forming a transistor having raised drain and source regions
US7888201B2 (en) 2003-11-04 2011-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
US6872626B1 (en) * 2003-11-21 2005-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a source/drain and a transistor employing the same
US7545001B2 (en) * 2003-11-25 2009-06-09 Taiwan Semiconductor Manufacturing Company Semiconductor device having high drive current and method of manufacture therefor
US7005333B2 (en) * 2003-12-30 2006-02-28 Infineon Technologies Ag Transistor with silicon and carbon layer in the channel region
US7244654B2 (en) * 2003-12-31 2007-07-17 Texas Instruments Incorporated Drive current improvement from recessed SiGe incorporation close to gate
US20050186722A1 (en) * 2004-02-25 2005-08-25 Kuan-Lun Cheng Method and structure for CMOS device with stress relaxed by ion implantation of carbon or oxygen containing ions
US7023018B2 (en) * 2004-04-06 2006-04-04 Texas Instruments Incorporated SiGe transistor with strained layers
US20050253205A1 (en) * 2004-05-17 2005-11-17 Fujitsu Limited Semiconductor device and method for fabricating the same
US20050266632A1 (en) * 2004-05-26 2005-12-01 Yun-Hsiu Chen Integrated circuit with strained and non-strained transistors, and method of forming thereof
TWI463526B (zh) * 2004-06-24 2014-12-01 Ibm 改良具應力矽之ｃｍｏｓ元件的方法及以該方法製備而成的元件
JP4837902B2 (ja) 2004-06-24 2011-12-14 富士通セミコンダクター株式会社 半導体装置
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US8669145B2 (en) * 2004-06-30 2014-03-11 International Business Machines Corporation Method and structure for strained FinFET devices
DE102004031743B4 (de) * 2004-06-30 2006-10-05 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Epitaxieschicht für erhöhte Drain-und Sourcegebiete durch Entfernen von Oberflächendefekten der anfänglichen Kristalloberfläche
US20060030093A1 (en) * 2004-08-06 2006-02-09 Da Zhang Strained semiconductor devices and method for forming at least a portion thereof
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US20060099765A1 (en) * 2004-11-11 2006-05-11 International Business Machines Corporation Method to enhance cmos transistor performance by inducing strain in the gate and channel
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US20060118878A1 (en) * 2004-12-02 2006-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS device with selectively formed and backfilled semiconductor substrate areas to improve device performance
US7479431B2 (en) * 2004-12-17 2009-01-20 Intel Corporation Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain
US7279406B2 (en) * 2004-12-22 2007-10-09 Texas Instruments Incorporated Tailoring channel strain profile by recessed material composition control
JP4369359B2 (ja) 2004-12-28 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置
US7314804B2 (en) * 2005-01-04 2008-01-01 Intel Corporation Plasma implantation of impurities in junction region recesses
US7193279B2 (en) 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US7348232B2 (en) * 2005-03-01 2008-03-25 Texas Instruments Incorporated Highly activated carbon selective epitaxial process for CMOS
US7282415B2 (en) 2005-03-29 2007-10-16 Freescale Semiconductor, Inc. Method for making a semiconductor device with strain enhancement
US20060234455A1 (en) * 2005-04-19 2006-10-19 Chien-Hao Chen Structures and methods for forming a locally strained transistor
WO2006111888A1 (en) * 2005-04-20 2006-10-26 Koninklijke Philips Electronics N.V. A strained integrated circuit and a method of manufacturing the same
JP4984665B2 (ja) * 2005-06-22 2012-07-25 富士通セミコンダクター株式会社 半導体装置およびその製造方法
US7579617B2 (en) * 2005-06-22 2009-08-25 Fujitsu Microelectronics Limited Semiconductor device and production method thereof
US7348248B2 (en) * 2005-07-12 2008-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS transistor with high drive current and low sheet resistance
US7892905B2 (en) * 2005-08-02 2011-02-22 Globalfoundries Singapore Pte. Ltd. Formation of strained Si channel and Si1-xGex source/drain structures using laser annealing
US7902008B2 (en) * 2005-08-03 2011-03-08 Globalfoundries Inc. Methods for fabricating a stressed MOS device
CN100577511C (zh) * 2005-08-12 2010-01-06 李晓阳 变体式空天飞艇
US7402875B2 (en) 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
KR101155097B1 (ko) * 2005-08-24 2012-06-11 삼성전자주식회사 반도체 장치의 제조 방법 및 그에 의해 제조된 반도체 장치
DE102005041225B3 (de) * 2005-08-31 2007-04-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung vertiefter verformter Drain/Source-Gebiete in NMOS- und PMOS-Transistoren
US8003470B2 (en) 2005-09-13 2011-08-23 Infineon Technologies Ag Strained semiconductor device and method of making the same
US7612389B2 (en) * 2005-09-15 2009-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded SiGe stressor with tensile strain for NMOS current enhancement
CN1937183A (zh) * 2005-09-19 2007-03-28 中芯国际集成电路制造(上海)有限公司 使用应变硅晶体管栅极图案化用硬掩模的方法和结构
US7947546B2 (en) * 2005-10-31 2011-05-24 Chartered Semiconductor Manufacturing, Ltd. Implant damage control by in-situ C doping during SiGe epitaxy for device applications
US7655511B2 (en) 2005-11-03 2010-02-02 International Business Machines Corporation Gate electrode stress control for finFET performance enhancement
US7635620B2 (en) 2006-01-10 2009-12-22 International Business Machines Corporation Semiconductor device structure having enhanced performance FET device
US7518193B2 (en) * 2006-01-10 2009-04-14 International Business Machines Corporation SRAM array and analog FET with dual-strain layers comprising relaxed regions
EP1808886A3 (fr) * 2006-01-17 2009-08-12 S.O.I.T.E.C. Silicon on Insulator Technologies Procédé d'ajustement de la contrainte d'un substrat en un matériau semi-conducteur
FR2896255B1 (fr) * 2006-01-17 2008-05-09 Soitec Silicon On Insulator Procede d'ajustement de la contrainte d'un substrat en un materiau semi-conducteur
US8900980B2 (en) * 2006-01-20 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Defect-free SiGe source/drain formation by epitaxy-free process
US7608515B2 (en) * 2006-02-14 2009-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Diffusion layer for stressed semiconductor devices
DE102006009225B4 (de) * 2006-02-28 2009-07-16 Advanced Micro Devices, Inc., Sunnyvale Herstellung von Silizidoberflächen für Silizium/Kohlenstoff-Source/Drain-Gebiete
US7696019B2 (en) * 2006-03-09 2010-04-13 Infineon Technologies Ag Semiconductor devices and methods of manufacturing thereof
US8017487B2 (en) 2006-04-05 2011-09-13 Globalfoundries Singapore Pte. Ltd. Method to control source/drain stressor profiles for stress engineering
US8076189B2 (en) 2006-04-11 2011-12-13 Freescale Semiconductor, Inc. Method of forming a semiconductor device and semiconductor device
TWI275488B (en) * 2006-04-14 2007-03-11 Int United Technology Co Ltd Ink jet printhead control circuit
DE102006019921B4 (de) * 2006-04-28 2010-10-28 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung des Transistors mit eingebetteter Schicht mit Zugverformung mit geringem Abstand zu der Gateelektrode
US20070278541A1 (en) * 2006-06-05 2007-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Spacer engineering on CMOS devices
US7629603B2 (en) * 2006-06-09 2009-12-08 Intel Corporation Strain-inducing semiconductor regions
US7618866B2 (en) * 2006-06-09 2009-11-17 International Business Machines Corporation Structure and method to form multilayer embedded stressors
DE102006030268B4 (de) * 2006-06-30 2008-12-18 Advanced Micro Devices Inc., Sunnyvale Verfahren zum Ausbilden einer Halbleiterstruktur, insbesondere eines FETs
US7790540B2 (en) 2006-08-25 2010-09-07 International Business Machines Corporation Structure and method to use low k stress liner to reduce parasitic capacitance
US7494884B2 (en) * 2006-10-05 2009-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. SiGe selective growth without a hard mask
US8008157B2 (en) 2006-10-27 2011-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS device with raised source and drain regions
JP5181466B2 (ja) * 2006-11-16 2013-04-10 ソニー株式会社 半導体装置の製造方法および半導体装置
US7897493B2 (en) * 2006-12-08 2011-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Inducement of strain in a semiconductor layer
JP2008171999A (ja) * 2007-01-11 2008-07-24 Toshiba Corp 半導体装置およびその製造方法
US8558278B2 (en) 2007-01-16 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Strained transistor with optimized drive current and method of forming
CN101281871B (zh) * 2007-04-05 2011-11-09 联华电子股份有限公司 复合硬掩模层、金属氧化物半导体晶体管及其制作方法
US8569837B2 (en) * 2007-05-07 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices having elevated source/drain regions
US8450165B2 (en) * 2007-05-14 2013-05-28 Intel Corporation Semiconductor device having tipless epitaxial source/drain regions
US20080293192A1 (en) * 2007-05-22 2008-11-27 Stefan Zollner Semiconductor device with stressors and methods thereof
US8115254B2 (en) 2007-09-25 2012-02-14 International Business Machines Corporation Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same
US7781799B2 (en) * 2007-10-24 2010-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain strained layers
US8492846B2 (en) 2007-11-15 2013-07-23 International Business Machines Corporation Stress-generating shallow trench isolation structure having dual composition
US8058123B2 (en) * 2007-11-29 2011-11-15 Globalfoundries Singapore Pte. Ltd. Integrated circuit and method of fabrication thereof
US20090140351A1 (en) * 2007-11-30 2009-06-04 Hong-Nien Lin MOS Devices Having Elevated Source/Drain Regions
CN101925986B (zh) * 2008-01-25 2012-09-05 富士通半导体股份有限公司 半导体器件及其制造方法
KR20090096885A (ko) * 2008-03-10 2009-09-15 삼성전자주식회사 국부적 매립 절연막을 구비하는 반도체 장치 및 그 제조방법
US7943961B2 (en) 2008-03-13 2011-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Strain bars in stressed layers of MOS devices
US7892932B2 (en) * 2008-03-25 2011-02-22 International Business Machines Corporation Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure
US20090242989A1 (en) * 2008-03-25 2009-10-01 Chan Kevin K Complementary metal-oxide-semiconductor device with embedded stressor
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US7808051B2 (en) 2008-09-29 2010-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell without OD space effect in Y-direction
US20100181626A1 (en) 2009-01-21 2010-07-22 Jing-Cheng Lin Methods for Forming NMOS and PMOS Devices on Germanium-Based Substrates
US8017469B2 (en) * 2009-01-21 2011-09-13 Freescale Semiconductor, Inc. Dual high-k oxides with sige channel
US20100279479A1 (en) * 2009-05-01 2010-11-04 Varian Semiconductor Equipment Associates, Inc. Formation Of Raised Source/Drain On A Strained Thin Film Implanted With Cold And/Or Molecular Carbon
JP5668277B2 (ja) 2009-06-12 2015-02-12 ソニー株式会社 半導体装置
US8211784B2 (en) * 2009-10-26 2012-07-03 Advanced Ion Beam Technology, Inc. Method for manufacturing a semiconductor device with less leakage current induced by carbon implant
US8178414B2 (en) * 2009-12-07 2012-05-15 Globalfoundries Inc. NMOS architecture involving epitaxially-grown in-situ N-type-doped embedded eSiGe:C source/drain targeting
US8598006B2 (en) * 2010-03-16 2013-12-03 International Business Machines Corporation Strain preserving ion implantation methods
JP5614184B2 (ja) * 2010-09-06 2014-10-29 富士通セミコンダクター株式会社 半導体装置の製造方法
US8709897B2 (en) * 2010-11-30 2014-04-29 Taiwan Semiconductor Manufacturing Company, Ltd. High performance strained source-drain structure and method of fabricating the same
CN103348238B (zh) * 2010-12-03 2016-12-28 加利福尼亚大学董事会 具有提高的灵敏度的纳米线场效应晶体管生物传感器
US8629426B2 (en) * 2010-12-03 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain stressor having enhanced carrier mobility manufacturing same
US20120153350A1 (en) * 2010-12-17 2012-06-21 Globalfoundries Inc. Semiconductor devices and methods for fabricating the same
US8361847B2 (en) 2011-01-19 2013-01-29 International Business Machines Corporation Stressed channel FET with source/drain buffers
US9691898B2 (en) 2013-12-19 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Germanium profile for channel strain
US9287398B2 (en) 2014-02-14 2016-03-15 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor strain-inducing scheme
US20190348511A1 (en) * 2017-03-31 2019-11-14 Intel Corporation Cap layer for metal contacts of a semiconductor device

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3361922B2 (ja) * 1994-09-13 2003-01-07 株式会社東芝 半導体装置
US5561302A (en) * 1994-09-26 1996-10-01 Motorola, Inc. Enhanced mobility MOSFET device and method
US5710450A (en) * 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
US6399970B2 (en) * 1996-09-17 2002-06-04 Matsushita Electric Industrial Co., Ltd. FET having a Si/SiGeC heterojunction channel
US5714777A (en) * 1997-02-19 1998-02-03 International Business Machines Corporation Si/SiGe vertical junction field effect transistor
US6127233A (en) * 1997-12-05 2000-10-03 Texas Instruments Incorporated Lateral MOSFET having a barrier between the source/drain regions and the channel region
US6071783A (en) * 1998-08-13 2000-06-06 Taiwan Semiconductor Manufacturing Company Pseudo silicon on insulator MOSFET device
US6887762B1 (en) * 1998-11-12 2005-05-03 Intel Corporation Method of fabricating a field effect transistor structure with abrupt source/drain junctions
IL143078A0 (en) * 1998-11-12 2002-04-21 Intel Corp Field effect transistor structure with abrupt source/drain junctions
JP2001024194A (ja) * 1999-05-06 2001-01-26 Toshiba Corp 半導体装置の製造方法及び半導体装置
KR100332108B1 (ko) * 1999-06-29 2002-04-10 박종섭 반도체 소자의 트랜지스터 및 그 제조 방법
US6274894B1 (en) * 1999-08-17 2001-08-14 Advanced Micro Devices, Inc. Low-bandgap source and drain formation for short-channel MOS transistors
US7391087B2 (en) * 1999-12-30 2008-06-24 Intel Corporation MOS transistor structure and method of fabrication
US6531347B1 (en) * 2000-02-08 2003-03-11 Advanced Micro Devices, Inc. Method of making recessed source drains to reduce fringing capacitance
US6509586B2 (en) * 2000-03-31 2003-01-21 Fujitsu Limited Semiconductor device, method for fabricating the semiconductor device and semiconductor integrated circuit
US6437375B1 (en) * 2000-06-05 2002-08-20 Micron Technology, Inc. PD-SOI substrate with suppressed floating body effect and method for its fabrication
US6509241B2 (en) * 2000-12-12 2003-01-21 International Business Machines Corporation Process for fabricating an MOS device having highly-localized halo regions
US6495402B1 (en) * 2001-02-06 2002-12-17 Advanced Micro Devices, Inc. Semiconductor-on-insulator (SOI) device having source/drain silicon-germanium regions and method of manufacture
US6900103B2 (en) * 2001-03-02 2005-05-31 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6831292B2 (en) * 2001-09-21 2004-12-14 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
KR100406537B1 (ko) * 2001-12-03 2003-11-20 주식회사 하이닉스반도체 반도체장치의 제조 방법
US6504214B1 (en) * 2002-01-11 2003-01-07 Advanced Micro Devices, Inc. MOSFET device having high-K dielectric layer
US6492216B1 (en) * 2002-02-07 2002-12-10 Taiwan Semiconductor Manufacturing Company Method of forming a transistor with a strained channel
US6812103B2 (en) * 2002-06-20 2004-11-02 Micron Technology, Inc. Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects
US6858505B2 (en) * 2002-10-08 2005-02-22 Samsung Electronics Co. Ltd. Methods of forming transistor structures including separate anti-punchthrough layers
US6743684B2 (en) * 2002-10-11 2004-06-01 Texas Instruments Incorporated Method to produce localized halo for MOS transistor
US6657223B1 (en) * 2002-10-29 2003-12-02 Advanced Micro Devices, Inc. Strained silicon MOSFET having silicon source/drain regions and method for its fabrication
US6703648B1 (en) * 2002-10-29 2004-03-09 Advanced Micro Devices, Inc. Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication
US7208362B2 (en) * 2003-06-25 2007-04-24 Texas Instruments Incorporated Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel
US20040262683A1 (en) * 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US7132338B2 (en) * 2003-10-10 2006-11-07 Applied Materials, Inc. Methods to fabricate MOSFET devices using selective deposition process
US7122435B2 (en) * 2004-08-02 2006-10-17 Texas Instruments Incorporated Methods, systems and structures for forming improved transistors
US7335929B2 (en) * 2004-10-18 2008-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor with a strained region and method of manufacture
US7358551B2 (en) * 2005-07-21 2008-04-15 International Business Machines Corporation Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions
US20070026599A1 (en) * 2005-07-27 2007-02-01 Advanced Micro Devices, Inc. Methods for fabricating a stressed MOS device
DE102005052054B4 (de) * 2005-10-31 2010-08-19 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauteil mit Transistoren mit verformten Kanalgebieten und Verfahren zu seiner Herstellung
CN1959959B (zh) * 2005-10-31 2010-04-21 中芯国际集成电路制造(上海)有限公司 使用应变硅用于集成pmos和nmos晶体管的单掩模设计方法和结构
JP5141029B2 (ja) * 2007-02-07 2013-02-13 富士通セミコンダクター株式会社 半導体装置とその製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100568467C (zh) * 2003-08-28 2009-12-09 国际商业机器公司 一种mosfet器件及其形成方法
CN100477123C (zh) * 2005-04-18 2009-04-08 株式会社东芝 用于减小多晶硅高度的SOI底部预掺杂合并e-SiGe
US7459382B2 (en) 2006-03-24 2008-12-02 International Business Machines Corporation Field effect device with reduced thickness gate
CN101573795B (zh) * 2007-01-04 2011-05-11 国际商业机器公司 一种制造半导体结构的方法
CN103187447A (zh) * 2011-12-31 2013-07-03 中芯国际集成电路制造(上海)有限公司 Pmos晶体管结构及其制造方法
CN103187447B (zh) * 2011-12-31 2016-05-11 中芯国际集成电路制造(上海)有限公司 Pmos晶体管结构及其制造方法

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