CN1368756A - 近环绕闸极及制造具有该闸极的矽半导体装置的方法 - Google Patents
近环绕闸极及制造具有该闸极的矽半导体装置的方法 Download PDFInfo
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Abstract
本发明揭示一种制造具有近环绕(quasi－surrounding)闸极的绝缘层上有矽(SOI)的半导体装置的方法;根据本发明的方法,可得到一种MOSFET半导体装置,其闸极电极几乎包围整个通道区域,而达到体积反转(Volume－inversion)的效果,可大幅增加该半导体装置的单位电流亦可控制短通道效应(SCE)的发生,而减少次临限漏电(sub－threshold leakage);此外,本发明的方法可以传统方式制造不同闸极长度的装置。
Description
技术领域
本发明是有关于一种绝缘层上有矽(SOI)半导体装置的结构以及其制造方法，特别有关于一种具有近环绕闸极的SOI半导体装置的结构以及其制造方法。
背景技术
绝缘层上有砂的技术是与在一层覆盖于一绝缘层上的半导体材料中形成电晶体有关，其在集成电路的领域越来越重要。在一薄的SOI层上制作集成电路元件，相对于在一较厚的砂结构中制作相同的IC元件，可得到较低的寄生电容与较大的通道电流，因而加快MOS整合电路的操作速度。再者，制作于SOI结构的砂膜中的场效电晶体，例如金氧半场效电晶体(MOSFET)，比制作于传统矽基材上的MOSFET具有更多优点，包括对短通道效应的电阻、较陡峭的次临限(subthreshold)斜率、增加的电流驱动、较高的风装密度、减小的寄生电容以及简单的制程步骤等。此外，由于SOI结构有效地减少寄生元件，同时增加结构对接面崩溃的容忍度，因此SOI技术适用于高效能及高密度的集成电路。
上述MOSMT的操作是经由在源极与汲极之间的通道区域通过电流。该通道区域的导电性是借由施加电压于位于通道表面上方的导电闸极而控制。为了增加MOSFET的性能，许多研究皆朝向改良SOI MOSFET的驱动电流速度发展，以谋求半导体装置的稳定性，同时减低电力消耗。
目前一般MOS电晶体的驱动电流是如图1所示的表面反转层(surface-inversion layer)14。其中，当一电压施加于闸极13时，形成于通道尾端的源极11与汲极12之间的表面反转层14是做为驱动电流的路径。然而，在该表面反转层仅能提供有限的电流的情形下，必须制造出能够预防短通道效应、汲极导致表面电位降低(drain-induced barrierlowering；DIBL)以及次门槛斜率的降低的SOI MOSFET。
发明内容
有鉴于此，本发明的目的在于提供一种近环绕闸极，以及制作具有该近环绕闸极结构的绝缘层上有矽的半导体装置的方法，其中该环绕闸极结构是体积反转(volume-inversion)，所谓体积反转是指不仅在半导体表面的表层通道(surface channel)有反转，在半导体层容积内以及半导体层两侧皆有反转。借由该环绕闸极结构，可大幅增加通道电流，进而提升半导体元件的操作速度，并能达到预防短通道效应、汲极感应阻障降低以及次门槛斜率的降低的效果。
此外，本发明的新颖的近环绕闸极结构SOI半导体装置可使用现有的晶片以及制程。而本发明的具有近环绕闸极结构的MOSFET可结合传统MOS制程与已广为接受的SOI技术而制造。因此本发明的具有近环绕闸极的半导体装置可以现有的整体(bulk)或SOI MOSFET技术，而不需额外或复杂的制程。
根据本发明的制造具有近环绕闸极结构的半导体结构的方法，其包括下列步骤：(a)在一半导体基底上经由第一绝缘层形成一半导体层；(b)在该半导体层上形成第一氧化层；(c)在该第一氧化层上形成第一牺牲氮化物层；(d)以微影技术将该第一牺牲氮化物层、第一氧化层、以及该半导体层图案化而形成岛状或长条状；(e)在该岛状或长条状的半导体层周围形成第二氧化层；(f)剥离该第一牺牲氮化物层；(g)沉积第二牺牲氮化物层；(h)以该第二牺牲氮化物层为罩幕，以一既定距离蚀刻至该第一绝缘层，并蚀刻该第二氧化层；(i)在该半导体层周围形成绝缘材料；(j)以该第二牺牲氮化物层为罩幕，而沉积多晶矽；(k)移除该第二牺牲氮化物层而形成一闸极；以及(l)以该闸极为罩幕在该半导体层植入与该半导体基底相反导电性的掺杂离子而形成源/汲极区。
根据本发明，该近环绕的闸极结构，如图2所示主要具有第一绝缘层21，位于该第一绝缘层21上的微米厚度的半导体层22，该半导体层22具有通常是内部的主体通道区域(bulk channel region)，闸极绝缘层23环绕该半导体层，以及闸极24几乎整个围绕该绝缘层21。
根据本发明的制造具有近环绕闸极结构的半导体结构的方法，该方法可以一个SOI结构或一个半导体基底开始，于该半导体基底上经由第一绝缘层形成半导体层，再依序形成第一氧化层以及第一牺牲氮化物层。接着，借由微影技术将上述半导体层、第一氧化层以及第一牺牲氮化物层形成岛状或长条状。
接着，在该半导体层周围形成第二氧化层而使该半导体层的角落圆滑，借此可改善闸极绝缘崩溃特性(gate insulator breakdowncharacteristics)，并可避免经由闸极绝缘的电场强化通道(field-enhanced tunneling through the gate dielectric)。上述形成氧化层的步骤可以一般方法进行，例如沉积或者热氧化。
然后，剥离该第一牺牲氮化层，再形成一第二牺牲氮化层并图案化成图7所示，以该第二牺牲氮化物层为罩幕以既定距离蚀刻第一绝缘层。该既定距离并无特别限制，亦可为零，也就是说如图3所示，蚀刻至第一绝缘层之上，较佳的范围为10-100nm。此时，上述用来圆滑半导体层角落的氧化层亦被蚀刻移除。同样的，本发明的剥离或蚀刻方法并无特别限制，可使用一般剥离/蚀刻方法。
接着，在该半导体周围形成绝缘材料层，该绝缘材料为选自二氧化矽、氮化矽、氧氮化矽以及高介电常数(dielectric constant；K)的绝缘材料等。然后沉积闸极材料，例如多晶矽，该闸极材料并不限于多晶矽，任何传统制程中所使用的闸极材料皆可。其次，可使用一平坦化技术，例如但不限于化学机械研磨(CMP)或有机材料沉积或是反应离子蚀刻(RIE)，来平坦化闸极材料表面。
此时，因为整个装置的微小尺寸，从该闸极的电场线将结束于该装置的后部，因而可做为一个实质上的后闸极(back gate)。接着再移除第二牺牲氮化层。
最后，以一般制作MOSFET的方法形成源/汲极区而成。
在本发明的近环绕闸极结构中，该半导体层的厚度较佳为＜200nm，该整体结构如图2所示。
本发明的近环绕闸极是形成于一SOI结构上，较佳是在一埋藏有氧化层的整体(bulk)半导体基底上。根据本发明所得的MOSFET可避免短通道效应并可提供比已知MOSFET更佳的驱动电流。
附图说明
以下，就图式说明本发明的具有近环绕闸极结构的SOI MOSFET装置的实施例。
图1显示传统的表面反转的SOI MOSFET；
图2显示本发明实施例的近环绕闸极的结构；
图3显示根据本发明实施例的另一近环绕闸极结构；
图4至图10显示本发明的实施例中，制作具有近环绕闸极结构的SOIMOSFET的剖面图。
图号说明：
45-半导体基底； 41-台缘层；
42-半导体层； 43-第一氧化层；
43a-第一氧化层； 44-第一牺牲氮化层；
71、72-第二牺牲氮化层； 73-既定距离；
81-绝缘材料； 91-多晶矽。
具体实施方式
请参阅图4至图10，其显示根据本发明制作具有近环绕闸极结构的SOI MOSFET半导体装置的方法制作N通道装置的实施例，不过只要在植入对应的离子时，适当地改变掺杂的极性或导电性，相同的原理也可用于制作P通道装置。
首先，如图4所示，在一P型半导体基底45上经由第一绝缘层41(SiO2)形成半导体层42，在该半导体层42上再依序形成第一氧化层43以及第一牺牲氮化层44(Si2N4)。之后以微影技术将该半导体层42、该第一氧化层43及该第一牺牲氮化层44，如图5所示，形成长条状。
接着，请参阅图6，在该半导体层42周围形成第二氧化层43a，使得该半导体层的角落圆滑。然后剥离该第一牺牲氮化层44并形成第二牺牲氮化层71、72，而如图7所示将其图案化。使用该第二牺牲氮化层为罩幕，以既定距离110nm蚀刻至该第一绝缘层41。此时，第二氧化层43a亦被蚀刻移除，而使该半导体层42的角落圆滑。
其次，请参阅图8，在该半导体周围以一绝缘材料氧化矽形成绝缘材料81之后，再沉积多晶矽91做为闸极材料，如图9所示，并以CMP将多晶矽91表面平坦化。
请参照图10，此时，使用适当的蚀刻技术将第二牺牲氮化层71、72移除，再以开极电极为罩幕，于半导体层形成源/汲极区后，使用例如但不限于离子植入的技术导入例如但不限定于砷的掺杂杂质原子而成。
图2所示的本发明的近环绕闸极结构，其中闸极电极23几乎整个围绕通道区域，而该通道区域明显地大于在半导体表面具有表面反转的已知电晶体，因此本发明的半导体装置可提供的驱动电流的确大幅增加许多。借由本发明的近环绕闸极结构，可避免从闸极电极发出的电场在通道区域下方终止，而能减少短通道效应。
虽然本发明已以一较佳实施例揭露如上，然其并非用以限定本发明，任何熟习此技艺者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当以专利要求范围所界定的为准。
Claims (5)
1、一种制造具有近环绕闸极的矽半导体装置的方法，该方法包括下列步骤：
(a)、在一半导体基底上经由第一绝缘层形成一半导体层；
(b)、在该半导体层上形成第一氧化层；
(c)、在该第一氧化层上形成第一牺牲氮化物层；
(d)、以微影技术将该第一牺牲氮化物层、第一氧化层以及该半导体层图案化而形成岛状或长条状；
(e)、在该岛状或长条状的半导体层周围形成第二氧化层；
(f)、剥离该第一牺牲氮化物层；
(g)、沉积第二牺牲氮化物层；
(h)、以该第二牺牲氮化物层为罩幕，以一既定距离蚀刻至该第一绝缘层，并蚀刻该第二氧化层；
(i)、在该半导体层周围形成绝缘材料；
(j)、以该第二牺牲氮化物层为罩幕，而沉积多晶矽；
(k)、移除该第二牺牲氮化物层而形成一闸极；以及
(l)、以该闸极为罩幕在该半导体层植入与该半导体基底相反导电性的掺杂离子而形成源/汲极区。
2、根据权利要求1所述的方法，其中该矽半导体装置为N通道MOSFET装置。
3、根据权利要求1所述的方法，其中该矽半导体装置为P通道MOSFET装置。
4、根据权利要求1所述的方法，其中步骤(1)还包括以离子植入法形成源/汲极延伸区。
5、一种近环绕的闸极结构，其包括：
第一绝缘层；
微米厚度的半导体层，位于该第一绝缘层上，且该半导体层图案化为一岛状或长条状；
闸极绝缘层，围绕该岛状或长条状的半导体层；以及
闸极，包围该闸极绝缘层并延伸至该第一绝缘层。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/761,889 US6359311B1 (en) | 2001-01-17 | 2001-01-17 | Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same |
| US09/761,889 | 2001-01-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1368756A true CN1368756A (zh) | 2002-09-11 |
| CN1172357C CN1172357C (zh) | 2004-10-20 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021017263A Expired - Lifetime CN1172357C (zh) | 2001-01-17 | 2002-01-14 | 近环绕栅极及制造具有该栅极的硅半导体器件的方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6359311B1 (zh) |
| CN (1) | CN1172357C (zh) |
| TW (1) | TW487977B (zh) |
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-
2001
- 2001-01-17 US US09/761,889 patent/US6359311B1/en not_active Expired - Lifetime
- 2001-06-05 TW TW090113569A patent/TW487977B/zh not_active IP Right Cessation
-
2002
- 2002-01-14 CN CNB021017263A patent/CN1172357C/zh not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011097802A1 (zh) * | 2010-02-11 | 2011-08-18 | 中国科学院上海微系统与信息技术研究所 | 全包围栅cmos场效应晶体管 |
| CN103928518A (zh) * | 2013-01-14 | 2014-07-16 | 台湾积体电路制造股份有限公司 | FinFET器件及其制造方法 |
| CN103928517A (zh) * | 2013-01-14 | 2014-07-16 | 台湾积体电路制造股份有限公司 | FinFET器件及其制造方法 |
| CN103928517B (zh) * | 2013-01-14 | 2017-08-08 | 台湾积体电路制造股份有限公司 | FinFET器件及其制造方法 |
| CN103928518B (zh) * | 2013-01-14 | 2017-08-25 | 台湾积体电路制造股份有限公司 | FinFET器件及其制造方法 |
| US10622480B2 (en) | 2013-01-14 | 2020-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming gate stacks of FinFETs through oxidation |
| CN105470301A (zh) * | 2014-09-10 | 2016-04-06 | 中国科学院微电子研究所 | 一种FinFET结构及其制造方法 |
| CN105470301B (zh) * | 2014-09-10 | 2018-10-02 | 中国科学院微电子研究所 | 一种FinFET结构及其制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1172357C (zh) | 2004-10-20 |
| US6359311B1 (en) | 2002-03-19 |
| TW487977B (en) | 2002-05-21 |
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