CN1333454C - 具有应变膜的绝缘体上硅装置及用于形成应变膜的方法 - Google Patents

具有应变膜的绝缘体上硅装置及用于形成应变膜的方法 Download PDF

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CN1333454C
CN1333454C CNB03813263XA CN03813263A CN1333454C CN 1333454 C CN1333454 C CN 1333454C CN B03813263X A CNB03813263X A CN B03813263XA CN 03813263 A CN03813263 A CN 03813263A CN 1333454 C CN1333454 C CN 1333454C
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W·P·毛斯萨拉
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Abstract

一种具有应变膜(14)的绝缘体上硅装置，包括基板(10)以及在该基板(10)上的埋藏氧化物层(12)。硅岛(18)系形成于该埋藏氧化物层(12)上，并且藉由沟槽(16)而将该硅岛(18)彼此隔开，该埋藏氧化物层(12)具有在该沟槽(16)正下方的凹处(22)，材料(24)填补该凹处(22)与该沟槽(16)，此材料(24)与形成于该埋藏氧化物层(12)材料不同，该材料(24)是导入净应变量于该硅岛(18)中，藉此修正在该应变膜(14)中的载流子的电性并且改善装置性能。

Description

具有应变膜的绝缘体上硅装置及用于形成应变膜的方法
技术领域
本发明有关半导体制造的领域，尤指用于绝缘体上硅(silicon-on-insulator，SOI)装置应变膜(strained device film)的形成者。
背景技术
用于互补性金属氧化物半导体(complementarymetal-oxide-semiconductor，CMOS)集成电路(integrated circuits，ICs)的绝缘体上硅(SOI)技术的优点已广见于文献中。通常，SOI技术降低在源极/漏极与基板之间不要的p-n接合面电容，与其它用于CMOS集成电路的现有技术相比，SOI技术可降低将近百分的25的p-n接合面电容。再者，在维持装置性能相等于形成于原硅(bulk-silicon)基板上的相似装置的性能的同时，由SOI技术所制造的CMOS集成电路具有较少的主动电流消耗量。其它SOI技术的优点包括抑制短沟道效应(short channel effect)、抑制体效应(body-effect)、高穿孔测试(highpunch-through immunity)、以及降低闩锁(latch-up)与数据读取错误(soft errors)。随着对以电池操作的装置的需要增加，因SOI装置的高速度仅需要低功率(low power requirements)之故，使得SOI技术渐渐地广受欢迎。
有许多不同的技术可形成SOI晶圆，这些技术中包括SIMOX，SIMOX系与植入氧技术不同。晶圆打线系用于在基板中形成隔绝层的另一种技术。透过一连串的蚀刻与氧化步骤所形成的硅岛可提供侧向隔绝结构。
在标准的金属氧化半导体场效应晶体管(MOSFET)技术中，系降低沟道长度以与门极介电厚度以改善电流驱动及转换性能。因MOSFET装置的载流子迁移率将直接影响输出电流以及转换性能之故，MOSFET装置的载流子迁移率为一重要的参数。因此，便以增加装置性能的其它方式来加强载流子迁移率。而此载流子迁移率的加强已藉由应变该硅薄膜而提供于某些装置中，藉由该硅薄膜的压缩应力或者硅薄膜的抗拉应力可提供净应变(net strain)。
因此本发明欲提供SOI技术及硅岛的隔绝优点，并且亦提供透过加强载流子迁移率所获得的改进的装置性能。
发明内容
本发明的目的在于提供一种应变膜在具有硅岛的绝缘体上硅装置中，以藉由加强在硅薄膜中的载流子迁移率而增加装置性能。
本发明的另一目的在于提供一种形成应变膜的方法，以满足本发明的实施例中提供一种具有应变膜的绝缘体上硅装置的目的及其它目的。该方法的步骤包括蚀刻在SOI结构的埋藏氧化物层中的凹处，而该SOI结构具有基板、在该基板上的埋藏氧化物层、以及在该埋藏氧化物层上的硅层。该硅层具有沟槽，而且在该埋藏氧化物层中的凹处的蚀刻包括蚀刻贯穿该硅层中的沟槽。在该埋藏氧化物层中的凹处与该沟槽系以导入在该硅层中的净应变量的材料所填补。
藉由以其它材料取代部份的埋藏氧化物层，可导入在该硅层中的净应变量以提供所欲的应力的量以及形式。举例来说，在某些实施例中，氮化物系沉积于该凹处中以及在该硅层的埋藏氧化物层与该沟槽中。改变该材料将改变应力的量以及形式(诸如抗拉应力或压缩应力的其中一者)，而将制造在该硅层中的净应变量。因此，本发明藉由加强在SOI装置中所创造的载流子迁移率而改善了装置性能。
本发明的另一目的在于提供一种具有应变膜的绝缘体上硅装置，以满足本发明的上述目的。该具有应变膜的绝缘体上硅装置包括基板以及在该基板上的埋藏氧化物层。在该埋藏氧化物层上系设有硅岛。该硅岛系以沟槽彼此隔开，该埋藏氧化物层则具有在该沟槽正下方的凹处。将材料填在该凹处以及该沟槽，此材料导入净应变量于该硅岛中。
本发明的前述及其它特征、态样以及优点将以所附图式配合本发明下列详细说明而更易于了解。
附图说明
第1图表示根据本发明实施例所架构的SOI装置原型的概要的横截面图。
第2图显示第1图于该硅层中已蚀刻沟槽以形成硅岛后的结构。
第3图显示根据本发明实施例的第2图于以侧蚀来蚀刻该埋藏氧化物层后的结构。
第4图显示根据本发明实施例的第3图于接着进行其它材料的沉积与平坦化后的结构。
第5图显示根据本发明实施例的第4图于硅岛上形成完整的装置后的结构。
第6及第7图显示藉由不同栅极介电厚度而降低栅极介电泄漏的方法。
具体实施方式
本发明致力于解决有关改善SOI装置的装置性能的问题，在某种程度上，本发明系藉由在硅岛正下方以及硅岛之间以不同的材料取代部份隔绝氧化物，以达成SOI装置的装置性能改善。在本发明的某些实施例中，系以底切方式透过在硅岛与硅层间的沟槽而进行侧蚀以蚀刻埋藏氧化物层。在蚀刻该埋藏氧化物层之后，接着沉积材料于沟槽以及形成于该埋藏氧化物层中的凹部之内。该材料系经选择而提供所欲应力(抗拉应力或压缩应力的其中一者)的量至该硅岛，以导入净应变量于硅薄膜中。该应变的硅已加强载流子迁移率，藉此改善形成于该应变的硅上的装置的装置性能。
第1图描述根据本发明实施例所架构的SOI装置原型(precursor)的概要的横截面图。该原型包括基板10，该基板10可例如为硅基板，于该基板10的上方系形成埋藏氧化物层12，而硅薄膜或硅层14则系形成于该埋藏氧化物层12上。该原型可以现有方式形成。
在第2图中，系于该硅层14中蚀刻出沟槽16，应用现有的蚀刻技术及化学作用来蚀刻该硅层14并且在该埋藏氧化物层12上停止蚀刻。该沟槽16系将该硅层14分隔出硅岛18，所进行的蚀刻例如为现有的非等向性蚀刻，该非等向性蚀刻在该硅岛18上制造出垂直侧壁。该非等向性蚀刻可为反应性离子蚀刻(Reactive Ion Etch，RIE)，反应性离子蚀刻指向性地蚀刻该硅层14。该硅岛18的宽度系根据现有技术而选定者。
在将该沟槽16蚀刻进入该硅层14中以创造该硅岛18后，以侧蚀工艺来蚀刻该埋藏氧化物层12。在第3图中，系描述侧蚀的结果。可进行现有的蚀刻技术以蚀刻该埋藏氧化物层12。可应用适当的非等向性蚀刻，以在该埋藏氧化物层12中展现出底切(如组件符号20所指示者)。因此，便可进行蚀刻以在该埋藏氧化物层12之内创造凹处22。在该硅层14中的凹处22包括在该沟槽16正下方的沟槽16的部份，并且包括在该硅岛18正下方的部份。以贯穿该沟槽16而蚀刻至该埋藏氧化物层12的方式进行蚀刻工艺，并且进行蚀刻直到在该埋藏氧化物层12中产生该底切20。亦可选择性应用等向蚀刻工艺或适当的非等向性蚀刻工艺其中一者。可控制底切量以影响在该硅岛18中的应变量，换言的，除了选择待沉积的材料外，在该埋藏氧化物层12中所产生的凹处22的大小将对导入于该硅岛18中的应变造成影响。
在该埋藏氧化物层12中形成该底切20，并且在该硅岛18间形成该沟槽16后，导入新材料24以取代已从该埋藏氧化物层12中蚀刻的氧化物。可应用诸如电浆辅助化学气相沉积(Plasma Enhanced ChemicalVapor Deposition，PECVD)的现有沉积技术，将该材料24沉积于该凹处22及该沟槽16中。该材料24系根据材料的本质特性(IntrinsicProperties)所选择，而该本质特性将对导入于该硅岛18中的应变的净量造成影响。以作为示范性材料而言，氮化物可用以填补该凹处22及藉由该沟槽16所形成的间隙。由于氮化物的本质特性之故，氮化物提供抗拉应力(Tensile Stress)于第4图所描述的结构中。亦可选择其它提供不同抗拉应力的量或不同形式的应力(诸如压缩应力)的材料。熟习该项技艺者可基于材料的本质特性来选择适当的材料，以制造出所欲的应力的量与所欲的的应力形式。
该材料24系藉由现有诸如化学机械研磨(Chemical MechanicalPolishing，CMP)的平坦化技术予以平坦化，以产生第4图的结构。在第4图的结构中，藉由该取代的材料24所产生的应力导入了于该硅岛18中的应变的净量。此应变的净量改变在该硅岛18的硅薄膜中的载流子(Carrier)电性(Electrical Properties)。因此，随后所形成的SOI装置的装置性能将提高。
第5图显示第4图在该硅岛18上形成半导体装置26后的结构。由于该硅岛18的应变系藉由该取代的材料24导入该埋藏氧化物层12中以及该硅岛18之间，因此改善在该装置26中的沟道迁移率，使得该装置26展现出性能增加。
这些材料仅为示范之用，在不背离本发明的精神及范畴下可使用其它的材料。
本发明的其它态样提供一种藉由不同栅极介电厚度以降低栅极介电泄漏的方法。栅极介电泄漏通常发生于漏极与源极区域附近，当栅极介电泄漏发生于沟道中央时，会造成四或五级(order)的电量损失(magnitude less)。由于隧穿(tunneling)系视介电厚度以指数方式传送数据，因此在该漏极/源极边缘的介电必须较厚，方可抑制栅极泄漏。在别处的介电则必须较薄，以增加沟道反转的栅极控制。
在退火延伸植入后，系在具有可控制蚀刻速率的缓冲用HF溶液中从栅极氧化物的侧边进行侧向蚀刻。随后则进行延伸接合面的边缘的蚀刻。接下来，将栅极及硅两者均以低温(例如，小于750℃)进行氧化，以避免延伸掺杂物扩散。所掺杂的多晶硅及n+硅将比轻微掺杂的p沟道更快地氧化。
在氧化作用之后，于该n+区域之上形成具25至30埃(Angstroms)厚的介电。该厚度可彻底地降低大量泄漏并且亦降低米勒电容(Millercapacitance)。接着进行间隔件形成、漏极/源极植入与硅化(silicidation)的工艺，此工艺系显示于第6及第7图中。
虽然本发明以详细地描述并用图说明，可清楚地了解的是，本发明仅以此作为阐明与范例者，而非用以限制本发明，本发明的范围由所附的权利要求书为限。

Claims (7)

1.一种用于形成应变膜的方法，包括下列步骤：
蚀刻在绝缘体上硅结构的埋藏氧化物层(12)中的凹处(22)，该绝缘体上硅结构具有基板(10)、在该基板(10)上的埋藏氧化物层(12)、以及在该埋藏氧化物层(12)上的硅层(14)，该硅层(14)具有沟槽(16)，而且在该埋藏氧化物层(12)中的凹处(22)的蚀刻包括蚀刻贯穿在该硅层(14)中的沟槽(16)及蚀刻硅层(14)下方的底切(20)；以及
以导入在该硅层(14)中的净应变量材料(24)填补在该埋藏氧化物层(12)中的凹处(22)与该沟槽(16)。
2.如权利要求1所述的方法，其中，蚀刻该凹处(22)的步骤包括等向性蚀刻该埋藏氧化物层(12)。
3.如权利要求1所述的方法，其中，该材料(24)为氮化物。
4.一种具有应变膜的绝缘体上硅装置，包括：
基板(10)；
在该基板(10)上的埋藏氧化物层(12)；以及
在该埋藏氧化物层(12)上的硅岛(18)，该硅岛(18)是通过沟槽(16)而彼此隔开，该埋藏氧化物层(12)具有在基板上且只在该沟槽(16)正下方的凹处(22)，该凹处(22)包括延伸到部分硅岛(18)下方的埋藏氧化物层(12)中的底切区(20)；以及
填补该凹处(22)与该沟槽(16)的材料(24)，该材料(24)导入在该硅岛(18)中的净应变量。
5.如权利要求4所述的绝缘体上硅装置，还包括在该硅岛(18)上的半导体装置(26)。
6.如权利要求4所述的绝缘体上硅装置，其中，该材料(24)为氮化物。
7.如权利要求4所述的绝缘体上硅装置，其中，该凹处(22)包括在该沟槽(16)正下方的第一部份以及在该硅岛(18)正下方的第二部份。
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