CN1332437C - 新型场效应晶体管和制造方法 - Google Patents

新型场效应晶体管和制造方法 Download PDF

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CN1332437C
CN1332437C CNB2003801042092A CN200380104209A CN1332437C CN 1332437 C CN1332437 C CN 1332437C CN B2003801042092 A CNB2003801042092 A CN B2003801042092A CN 200380104209 A CN200380104209 A CN 200380104209A CN 1332437 C CN1332437 C CN 1332437C
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transistor
semiconductor film
bandgap semiconductor
narrow bandgap
dielectric
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CN1717798A (zh
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罗伯特·乔
道格拉斯·巴雷吉
金本义
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Abstract

本发明是一种新型场效应晶体管,其具有由形成在绝缘衬底上的窄带隙半导体膜形成的沟道区。在窄带隙半导体膜上形成栅极电介质层。然后在栅极电介质上形成栅极电极。由宽带隙半导体膜或金属形成的一对源极区/漏极区形成在所述栅极电极的相对侧上并与窄带隙半导体膜相邻。

Description

新型场效应晶体管和制造方法
发明背景
1.技术领域
本发明涉及半导体集成电路领域,更具体地,涉及耗尽型衬底晶体管(DST)及其制造方法。
2.背景技术
今天的现代集成电路完全是由一起集成到功能电路中的差不多数亿的晶体管构成。为了进一步提高逻辑集成电路的计算能力,必须进一步提高晶体管的密度和性能,并进一步降低工作电压(Vcc)。为了提高器件性能并降低工作电压,绝缘硅(SOI)晶体管已被提出用于制造现代集成电路。全耗尽型SOI晶体管已被提出来作为晶体管结构,以利用优化的导通电流/截止电流比率的理想亚阈值梯度。即,SOI晶体管的优点在于它们经受较低的泄漏电流(leakage current),因而可以降低晶体管的工作电压。降低晶体管的工作电压可以制造出低功率、高性能的集成电路。图1示出了标准的全耗尽型绝缘硅(SOI)晶体管100。SOI晶体管100包括单晶硅衬底102,其具有绝缘层104,例如形成在所述衬底上的隐埋(buried)的氧化物层。单晶硅主体106形成在绝缘层104上。栅极电介质层108形成在单晶硅主体106上,栅极(gate)电极110形成在栅极电介质108上。源极(source)区112和漏极(drain)区114横向地沿着栅极电极110的相对侧形成在硅主体106中。不幸的是,可以利用今天的结构和工艺来可靠并一致地获得的栅极氧化物生成(gate oxidescaling)和栅极长度生成(gate length scaling)的量正变得有限。
因此,需要一种可以实现进一步的Vcc定标和改善的电学性能的新型晶体管结构。
附图说明
图1示出了绝缘硅(SOI)晶体管的截面图。
图2示出了根据本发明的场效应晶体管的截面图。
图3A-3G示出了一种根据本发明的实施方案形成场效应晶体管的方法。
具体实施方式
本发明是一种新型场效应晶体管及其制造方法。在下面的描述中,提供了大量具体细节以透彻地理解本发明。但是,本领域的普通技术人员将会认识到,没有这些具体细节也可以实施本发明。在其他情形下,没有以具体的细节来描述公知的半导体设备和工艺,以免不必要地模糊本发明。
本发明是一种新型场效应晶体管及其制造方法。本发明的晶体管具有由窄带隙半导体(例如InSb)形成的超高沟道(channel)移动性。由于沟道是由窄带隙材料(室温下小于0.7eV)形成的,因此它具有高沟道移动性和饱和速度,可以在较低的电压下获得更多的驱动电流。低电压的大驱动电流使得晶体管可以工作在低工作电压下,例如小于0.5伏特。晶体管可以形成在绝缘衬底上,以便可以形成耗尽型衬底晶体管(DST)。使用绝缘衬底防止了结电荷泄漏到衬底中。晶体管的源极区(source region)和漏极区(drain region)可以专门被构造为有助于防止或减少与窄带隙材料相关联的泄漏电流。在本发明的一个实施方案中,由诸如铂、铝和金等材料形成源极区/漏极区,所述材料可以与用来形成沟道区的窄带隙半导体膜形成“肖特基”势垒,以便形成改变注入的势垒。在本发明的另一个实施方案中,可以由宽带隙半导体材料例如InAlSb、GaP和GaSb形成源极区和漏极区。在窄带隙沟道区附近的源极区/漏极区中使用大带隙半导体(以及在源极/漏极半导体和沟道区半导体之间的专门的带边构造)减小了器件的泄漏电流。使用具有专门的带构造的源极区/漏极区和绝缘衬底有助于最小化与窄带隙材料相关联的大结泄漏电流。
在图2中示出了根据本发明实施方案的场效应晶体管200。场效应晶体管200形成在绝缘衬底202上。在本发明的实施方案中,绝缘衬底202包括生长在衬底206上的绝缘膜204上。在其他实施方案中,可以使用其他类型的绝缘衬底,例如但不局限于氧化铪(hafium oxide)、氧化锆和钛酸钡(BaTiO3)。
晶体管200包括由形成在衬底202上的窄带隙(小于0.5eV)半导体膜形成的沟道区208。在本发明的实施方案中,沟道区(channel region)是由InSb(带隙=0.17eV)化合物形成的。在其他实施方案中,沟道区是用PdTe(带隙=0.31eV)或InAs(带隙=0.36eV)化合物膜形成的。在本发明的实施方案中,InSb化合物掺杂以n型杂质,例如砷、锑和磷(phosphorous),掺杂级别在1×1017-1×1018原子数/cm2,以制造p型器件。在本发明的另一个实施方案中,沟道区208掺杂以p型杂质,例如硼,掺杂级别在1×1017-1×1018原子数/cm2,以制造n型器件。在本发明的另一个实施方案中,沟道区208未掺杂,或者是具有窄带隙的本征半导体膜。在本发明的实施方案中,沟道区被形成为厚度约为器件栅极长度(Lg)的1/3。利用小于10纳米的薄膜能够形成具有30nm的Lg的全耗尽型衬底晶体管(DST)。使用窄带隙沟道区使得超高移动性和饱和速度能够实现,从而能够为逻辑应用实现高性能和低Vcc。
晶体管200具有形成在薄膜沟道区208上的栅极电介质210。虽然栅极电介质210可以是生长出的电介质,例如SiO2或氧氮化硅(silicon oxynitride),但是栅极电介质优选沉积的电介质,以便它可以形成在较低温度(小于500℃)下,并且由此可与窄带隙沟道区膜(例如InSb)相容(compatible)。在本发明的实施方案中,栅极电介质210是或包括高介电常数膜。高介电常数膜具有大于9.0,并且理想地具有大于50的介电常数。高介电常数膜可以是金属氧化物电介质,例如但不局限于五氧化二钽(Ta2O5)、氧化钛、氧化铪、氧化锆和氧化铝。但是,栅极电介质层210可以是其他公知的高介电常数膜,例如锆酸钛酸铅(PZT)或钛酸钡锶(BST)。利用高介电常数膜使得栅极电介质能够形成得相对较厚,对于高介电常数(k>100)的材料,厚度在20-3000之间,理想地大约在200。厚的栅极电介质层有助于堵住器件的泄漏电流。任何公知的技术例如气相沉积或溅射都可以用于沉积栅极电介质膜210。在本发明的实施方案中,使用低温工艺(200-500℃之间)来沉积栅极电介质。
晶体管200包括形成在栅极电介质210上的栅极电极212。在本发明的实施方案中,栅极电极212是金属栅极电极,例如但不局限于钨(W)、钽(Ta)、钛(Ti)和它们的硅化物和氮化物。在本发明的实施方案中,由功函数在n型硅和p型硅之间(例如在4.1eV和5.2eV之间)的膜形成栅极电极。在本发明的实施方案中,栅极电极是由具有中间能隙功函数(midgap work function)的金属或膜形成。金属栅极电极在使用金属氧化物电介质时是所期望的,因为它们与金属氧化物电介质相容并可以直接形成在其上。栅极电极212具有一对侧面相对的侧壁214和216,二者沿着器件的栅极宽度延伸。侧面相对的侧壁之间的距离定义了器件的栅极长度(Lg)。在本发明的实施方案中,栅极电极212形成为具有300纳米或更小的栅极长度。晶体管的栅极宽度(Gw)是栅极电极以与栅极长度垂直的方向(即进出图2的页面)在沟道区上延伸的距离。栅极电极212不一定由单个膜形成,而是可以由多个膜来形成,以形成复合栅极电极,所述多个膜例如可包括金属膜、硅膜和硅化物。当使用金属氧化物电介质时,应在金属氧化物电介质上直接形成金属膜。在本发明的实施方案中,栅极电极212形成为厚度在500-1000之间。在本发明的实施方案中,栅极电极212是利用小于500℃,优选小于350℃的低温工艺例如溅射形成。
晶体管200包括源极区220和漏极区222。源极区220和漏极区222形成在绝缘衬底202上,如图2所示。源极区220和漏极区222沿着栅极电极212横向相对的侧壁214和216延伸进出图2的页面。栅极电介质210上的栅极电极212与源极区220和漏极区222稍微重叠,如图2所示。理想地,所述重叠在每侧小于栅极长度的约10%。源极区220通过沟道区208漏极区222分开,如图2所示。
在本发明的实施方案中,源极区220和漏极区222由这样的材料形成,即所述材料抑制由于沟道区的窄带隙而形成的寄生晶体管泄漏。在本发明的实施方案中,源极区220和漏极区222由宽或高带隙半导体材料形成。当由半导体材料形成源极区220和漏极区222时,源极区220和漏极区222的半导体膜的带隙应大于沟道区的带隙。在实施方案中,源极和漏极半导体材料的带隙比沟道区中的半导体膜208的带隙至少大0.2eV,理想地至少大0.5eV。源极/漏极半导体膜220以及222和沟道半导体膜208之间的带隙偏差防止了跨越势垒的载流子注入。在本发明的实施方案中,源极区220和漏极区222是由与沟道区半导体相比具有较大带隙的III-V族化合物半导体形成的,例如但不局限于InP(带隙=1.35eV)、GaSb(带隙=0.75eV)、GaP和GaAs(带隙=1.43)。但是,其他具有合适的大带隙的半导体材料例如锗(带隙=0.67eV)也可以使用。源极/漏极半导体膜可以是多晶膜或单晶膜。半导体膜220和222可用n型杂质例如砷、锑或磷掺杂到1×1020-1×1021原子数/cm3的浓度级别,以形成n型MOS器件(NMOS),而在形成p型器件(PMOS)时,可用p型杂质例如硼或镓掺杂到1×1020-1×1021原子数/cm2的浓度级别。通过利用宽或大带隙材料来形成源极220和漏极222,并将它们放置与窄或小带隙沟道区208相邻,以产生抑制通常发生在窄带隙沟道区的寄生晶体管泄漏的势垒。
在本发明的另一个实施方案中,源极区和漏极区是由金属膜形成的。在本发明的实施方案中,源极区和漏极区是由金属或膜(“肖特基金属”)形成的,例如但不局限于铂(Pt)、铝(Al)和金(Au),这些材料可以与沟道区208的半导体膜形成“肖特基”势垒。通过将金属源极区和漏极区放置与沟道区的半导体膜相接触而产生的“肖特基”势垒,形成了对从源极区和漏极区进入沟道区的电流的势垒。以这种方式,需要偏压来将载流子从源极220和漏极222注入沟道208。在本发明的实施方案中,源极区和漏极区是由金属膜形成的,例如但不局限于氮化钛(TiN)、氮化钽(TaN)和氮化铪(HfN)。
使用绝缘衬底和专门的带构造的源极区/漏极区抑制了由于沟道区材料(例如InSb)的窄带隙而形成的寄生晶体管泄漏。以这种方式,晶体管200可作为低功耗、高性能器件来工作。
晶体管200可以全耗尽方式工作,其中当晶体管200导通时,沟道区208完全耗尽,从而提供了全耗尽型衬底晶体管(DST)有利的电学特性和性能。即,当晶体管200导通时,在区域208的表面形成反型层(inversion layer),其具有与源极区和漏极区相同的导电类型,并在源极区和漏极区之间形成导电沟道,以允许电流在其间流动。在反型层下面形成耗尽了自由载流子的耗尽区。耗尽区延伸到沟道区208的底部,因此晶体管可以说是“全耗尽”晶体管。全耗尽型晶体管具有超越非全耗尽型或部分耗尽型晶体管的改善的电学性能特性。例如,晶体管200以全耗尽方式工作,赋予了晶体管200理想或非常陡峭的亚阈值斜率。另外,晶体管200通过以全耗尽方式工作,具有了改善的漏极感应势垒(dibble)削弱,这提供了更好的“截止”状态泄漏,获得了更低的泄漏,从而获得了更低的功耗。为了使晶体管200以全耗尽方式工作,沟道区208的厚度理想地为晶体管栅极长度(Lg)的1/3。
图3A-3G示出了根据本发明的实施方案形成场效应晶体管200的方法。根据本发明的场效应晶体管的制造开始于在绝缘衬底300上形成窄带隙半导体膜,例如InSb。在本发明的实施方案中,所述衬底是例如图3A所示的绝缘衬底300。在本发明的实施方案中,绝缘衬底300包括较低的单晶硅衬底302和顶部绝缘层304,例如二氧化硅膜、金属氧化物或氮化硅膜。绝缘层304将窄带隙半导体材料306与衬底302隔绝开来,并且在实施方案中形成为厚度在200-2000之间。隔绝或绝缘层304有时称为“隐埋的氧化物”层。衬底302可以是半导体衬底,例如但不局限于单晶硅衬底和其他半导体衬底。
窄带隙半导体膜306可以用任何合适的方法形成在绝缘衬底300上。例如,窄带隙半导体膜306可以利用转印工艺(transfer process)形成到绝缘衬底300上。在这一技术中,首先在硅晶片上生长出薄氧化物,其在后面将用作为势垒氧化物(barrier oxide)304。接着,向窄带隙半导体膜中注入高剂量的氢,以在窄带隙半导体衬底的表面下形成高应力区。然后将窄带隙半导体晶片翻转过来,并结合到形成在硅衬底302上的氧化物层304的表面。然后沿着由于氢注入而产生的高应力区分开窄带隙半导体衬底。这样就获得了一种结构,其中薄的窄带隙半导体膜306形成在隐埋的氧化物膜304的顶部上,而隐埋的氧化物膜304形成在或位于单晶硅衬底302的顶部上。可以使用公知的精加工(smoothing)技术例如HCI精加工或化学机械抛光来将窄带隙半导体膜306的顶表面精加工到所需的厚度。在本发明的实施方案中,半导体膜306是本征(即未掺杂的)窄带隙半导体膜。在其他实施方案中,窄带隙半导体膜306被掺杂成p型或n型导电性,浓度级别在1×106-1×1019原子数/cm3。半导体膜306可以是现场(in situ)掺杂(即在沉积期间掺杂),或者在形成在衬底300上后例如通过离子注入307而掺杂。在形成后掺杂使得在同一绝缘衬底300上能够容易地制造PMOS和NMOS器件二者。窄带隙半导体材料的掺杂级别确定了器件的沟道区的掺杂级别。
接着,如图3B所示,在窄带隙半导体材料306上形成光致抗蚀剂掩模308。光致抗蚀剂掩模(mask)308可以通过公知的技术来形成,例如通过掩模(masking)、曝光和显影均厚沉积(blanket deposited)的光致抗蚀剂膜来形成。光致抗蚀剂掩模308覆盖了窄带隙半导体材料306将成为晶体管的沟道区的部分。在形成光致抗蚀剂层308后,利用公知技术,与光致抗蚀剂掩模对齐各向异性地蚀刻窄带隙半导体膜306,以完全去除氧化物304上随后将形成源极区和漏极区的位置312和314处的窄带隙半导体材料306。在蚀刻窄带隙半导体材料后,窄带隙半导体材料剩余的部分提供了晶体管的沟道区。
接着,如图3C所示,利用公知技术去除光致抗蚀剂掩模308,并使用膜316来形成均厚沉积(blanket deposition)在衬底300上的源极区和漏极区。在本发明的实施方案中,膜316是大或宽带隙半导体材料,例如III-V族化合物半导体,例如但不局限于InAlSb、InP、GaSb、GaP和GaAs。在本发明的另一个实施方案中,源极/漏极材料316是由金属形成的,例如铂、铝和金,该金属与窄带隙材料306形成肖特基势垒。应意识到,源极/漏极材料316形成为与窄带隙半导体材料316的侧壁相接触,如图3C所示。源极/漏极膜316理想地通过低温(小于500℃)工艺例如溅射或分子束外延而均厚沉积。源极/漏极膜316典型地沉积为厚度至少与窄带隙半导体膜306一样厚。
接着,如图3D所示,源极/漏极膜316被平面化,以使它变得与窄带隙半导体材料306的顶表面基本平齐。源极/漏极膜316可利用公知技术来平面化,例如但不局限于化学机械抛光和等离子回蚀(etch back)。
接着,如图3E所示,在窄带隙半导体膜306上形成栅极电介质层318。栅极电介质层318理想地为沉积的电介质膜。在本发明的实施方案中,栅极电介质层318是高介电常数电介质膜,例如如上所述的金属氧化物电介质。沉积的电介质将均厚沉积在衬底300的所有表面上,包括窄带隙半导体膜306和用来形成源极区和漏极区的膜316。任何公知的技术例如气相沉积或溅射都可用来沉积栅极电介质318。在本发明的实施方案中,使用低温工艺(200-500℃之间)来沉积栅极电介质层318。栅极电介质层318可形成为厚度在20-3000之间,理想地在大约20-200之间。
接着如图3F所示,一个或多个栅极电极膜320均厚沉积在栅极电介质层318上。栅极电极膜320理想地为金属膜,例如钨、钛和钽以及它们的硅化物或氮化物,如上所述。然后利用公知技术来形成光致抗蚀剂掩模322,例如掩盖、曝光和显影,以界定将在其处形成器件的栅极电极的位置。光致抗蚀剂掩模322形成在用于形成器件的沟道区的已图形化的窄带隙半导体材料306上并完全覆盖它。可使得光致抗蚀剂掩模比窄带隙半导体沟道区306稍宽,以确保沟道区的完全栅极覆盖以及解决未对齐的问题。
接着,如图3G所示,采用与光致抗蚀剂掩模322对齐来蚀刻栅极电极膜320,以界定器件的栅极电极320。栅极电极完全覆盖用于形成器件沟道的已图形化的窄带隙半导体膜。另外,此时还可去除形成在源极区和漏极区316上的栅极氧化物层。接着,如果需要,例如当宽带隙半导体材料被用作为膜316以形成源极区漏极区时,可利用源极/漏极注入324来掺杂源极区和漏极区316至所需的导电性类型和浓度。这就完成了场效应晶体管的制造,该晶体管具有由窄带隙半导体膜形成的沟道区,并具有防止不需要的载流子注入到沟道中的专门构造的源极区和漏极区。
至此,已经描述了一种新型晶体管,其具有高沟道移动性和饱和速度,可以工作在低工作电压例如小于0.7Vcc下。

Claims (38)

1.一种晶体管,包括:
由形成在绝缘衬底上的窄带隙半导体膜形成的沟道区;
形成在所述窄带隙半导体膜上的栅极电介质;
形成在所述栅极电介质上的栅极电极;以及
由具有比所述窄带隙半导体膜更宽带隙的半导体膜形成的一对源极区/漏极区,所述半导体膜形成在所述栅极电极的相对侧上并与所述窄带隙半导体膜相邻,所述栅极电极与所述源极区和漏极区中的至少一个的一部分重叠。
2.如权利要求1所述的晶体管,其中所述窄带隙半导体膜具有小于或等于0.7eV的带隙。
3.如权利要求1所述的晶体管,其中所述窄带隙半导体膜包括InSb。
4.如权利要求2所述的晶体管,其中所述窄带隙半导体膜选自由InAs、PdTe和InSb所组成的组。
5.如权利要求1所述的晶体管,其中所述栅极电介质包括高介电常数膜。
6.如权利要求1所述的晶体管,其中所述源极区和漏极区是由III-V族半导体形成的。
7.如权利要求1所述的晶体管,其中所述栅极电极是金属栅极电极。
8.如权利要求1所述的晶体管,其中所述源极区/漏极区的所述半导体膜的带隙至少比所述沟道区的带隙大0.2eV。
9.如权利要求1所述的晶体管,其中所述源极区/漏极区的所述半导体膜选自由InAISb、InP、GaSb、GaP和GaAs所组成的组。
10.一种晶体管,包括:
由形成在绝缘衬底上的窄带隙半导体膜形成的沟道区;
形成在所述窄带隙半导体膜上的栅极电介质;
形成在所述栅极电介质上的栅极电极;以及
沿所述栅极电极的相对侧,并与所述窄带隙半导体膜相邻而形成的一对金属源极区/漏极区,所述栅极电极与所述源极区和漏极区中的至少一个的一部分重叠。
11.如权利要求10所述的晶体管,其中所述窄带隙半导体膜具有小于或等于0.7eV的带隙。
12.如权利要求10所述的晶体管,其中所述窄带隙半导体膜选自由InAs、PdTe和InSb所组成的组。
13.如权利要求10所述的晶体管,其中所述源极区/漏极区是由选自由氮化钛、氮化钽和氮化铪所组成的组的材料形成。
14.如权利要求10所述的晶体管,其中所述源极区/漏极区是由可与所述窄带隙半导体膜形成肖特基势垒的金属膜形成的。
15.如权利要求10所述的晶体管,其中所述金属膜选自由铂、铝和金所组成的组。
16.如权利要求10所述的晶体管,其中所述栅极电介质具有大于9.0的介电常数。
17.如权利要求10所述的晶体管,其中所述栅极电介质包括金属氧化物电介质。
18.如权利要求10所述的晶体管,其中所述栅极电介质层选自由PZT、BST、五氧化二钽、氧化铪、氧化锆和氧化铝所组成的组。
19.如权利要求10所述的晶体管,其中所述栅极电介质层具有的厚度在20-3000之间。
20.如权利要求10所述的晶体管,其中所述栅极电极包括金属膜。
21.如权利要求10所述的晶体管,其中所述栅极电极具有中间能隙功函数。
22.如权利要求10所述的晶体管,其中所述晶体管具有小于或等于30纳米的栅极长度。
23.如权利要求10所述的晶体管,其中所述窄带隙半导体膜的所述厚度大约是所述晶体管的栅极长度的1/3。
24.如权利要求10所述的晶体管,其中所述绝缘衬底包括形成在单晶硅衬底上的二氧化硅膜。
25.一种形成晶体管的方法,包括:
在绝缘衬底上形成窄带隙半导体膜;
在所述窄带隙半导体膜上形成栅极电介质层;
在所述栅极电介质上形成栅极电极;以及
形成一对源极区/漏极区与所述窄带隙半导体膜相邻,所述栅极电极与所述源极区和漏极区中的至少一个的一部分重叠。
26.如权利要求25所述的方法,其中所述窄带隙半导体膜具有小于或等于0.7eV的带隙。
27.如权利要求26所述的方法,其中所述窄带隙半导体膜选自由InAs、PdTe和InSb所组成的组。
28.如权利要求26所述的方法,其中所述源极区/漏极区是由具有比所述窄带隙半导体膜更宽的带隙的半导体膜形成的。
29.如权利要求25所述的方法,其中所述源极区/漏极区是由化合物半导体形成的。
30.如权利要求28所述的方法,其中所述源极区/漏极区的所述半导体膜选自由InAISb、InP、GaSb、GaP和GaAs所组成的组。
31.如权利要求25所述的方法,其中所述源极区/漏极区是由金属膜形成的。
32.如权利要求31所述的方法,其中所述金属膜与所述窄带隙半导体膜形成肖特基势垒。
33.如权利要求31所述的方法,其中所述金属膜选自由氮化钛、氮化钽和氮化铪所组成的组。
34.如权利要求25所述的方法,其中所述栅极电介质层包括沉积的高介电常数膜。
35.如权利要求25所述的方法,其中所述栅极电极包括金属膜。
36.一种晶体管,包括:
由形成在绝缘衬底上的窄带隙半导体膜形成的沟道区;
形成在所述窄带隙半导体膜上的栅极电介质;
形成在所述栅极电介质上的栅极电极;以及
形成在所述绝缘衬底上并与所述窄带隙半导体膜的相对侧相邻的一对源极区/漏极区,所述栅极电极与所述源极区和漏极区中的至少一个的一部分重叠。
37.如权利要求36所述的晶体管,其中所述源极区/漏极区是由金属膜形成的。
38.如权利要求36所述的晶体管,其中所述源极区/漏极区是由宽带隙半导体膜形成的。
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