CN1320606C - Gate dielectric layer, its electric performace improving method and Mos crytsal - Google Patents
Gate dielectric layer, its electric performace improving method and Mos crytsal Download PDFInfo
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- CN1320606C CN1320606C CNB031050654A CN03105065A CN1320606C CN 1320606 C CN1320606 C CN 1320606C CN B031050654 A CNB031050654 A CN B031050654A CN 03105065 A CN03105065 A CN 03105065A CN 1320606 C CN1320606 C CN 1320606C
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Abstract
The present invention provides a method for improving the electrical properties of a gate dielectric layer, which comprises the following steps: providing a semiconductor substrate; foring a gate dielectric layer on the surface of the semiconductor substrate, wherein the gate dielectric layer comprises hafnium oxide (HfO2); implementing hydrogen-bearing gas processing; implementing oxygen-containing gas processing. A metal oxide semiconductor crytsal of the gate dielectric layer with high dielectric constant comprises a semiconductor substrate, a gate dielectric layer with high dielectric constant, and is arranged on the surface of the semiconductor substrate. The main purpose of the present invention is to provide the gate dielectric layer of new materials and the method for improving the electrical properties of the gate dielectric layer. The present invention not only provides the favorable gate dielectric layer, but also can makes the gate dielectric layer accord with the requirement of designing semiconductor assemblies.
Description
Technical field
The invention relates to a kind of gate dielectric, and particularly relevant for a kind of electrical method and a kind of MOS (metal-oxide-semiconductor) transistor with gate dielectric of high-k of improving gate dielectric.
Background of invention
Under the trend of and size of components microminiaturization growing along with the technology of integrated circuit, (the metal-oxide-semiconductor of metal-oxide-semiconductor (MOS), MOS) grid oxic horizon in the assembly (gate oxide) is done thinner and thinner, for the also raising relatively of reliability requirement of grid oxic horizon.
In the present known gate dielectric technology, method commonly used is to add a spot of nitrogen promotes grid oxic horizon to form the nitrogen oxide layer reliability in grid oxic horizon.Because the nitrogen oxide layer can be possessed the good interface characteristic with silicon base and be had preferable anti-electric stress characteristic to reduce hot carrier (hot carrier) effect.Yet the nitrogen-atoms of too high amount can make carrier mobility (mobility) descend.
In addition, the mode that also can adopt ion to implant is implanted fluorine atom at grid (gate) and is driven in (drive-in) via high temperature again and make fluorine atom diffuse to the interface of gate dielectric and silicon base that is SiO
2Hot carrier effect to form the Si-F bond, also can effectively be resisted in/Si interface.Though the bond ability of Si-F can be resisted the stress of hot carrier by force, however excessive fluorine atom, and the oxygen atom that can cause a large amount of not bonds is toward SiO
2/ Si Interface Moving and form interface trap and produce more defectives and then cause semiconductor subassembly electrically to degenerate, for example start voltage (threshold voltage; V
Th) reduce, flat band voltage (flat band voltage; V
Fb) change etc.
In addition, annealing in process also is suggested and is applied to gate dielectric, to improve the electrical degeneration of semiconductor subassembly.
Yet along with the increase of semiconductor integrated level, size of components is constantly dwindled thereupon.Especially from generation to generation, known silica grid dielectric layer can not satisfy to stop fully wears the demand of satisfying effect (tunneling effect), needs badly and seeks the higher material of dielectric constant with as gate dielectric to 0.13 μ m, 0.09 μ m.Therefore, the gate dielectric of new material begins to be suggested.
September 18 calendar year 2001 people such as Wallace bulletin No. the 6th, 291,867, United States Patent (USP), disclosing a kind of material is the gate oxide of metallic silicon oxynitride (metal silicon oxynitridc), this metal can comprise hafnium (hafnium; Hf) or zirconium (zirconium), the dielectric constant of this metallic silicon oxynitride is far above known silicon dioxide or silicon nitride.
January 28 in 2003 people such as order Aronowitz bulletin United States Patent (USP) the 6th, 511, No. 925, disclose a kind of method that forms the gate dielectric of high-k, be the electricity slurry processing that contains metal ion at the silicon oxide dielectric layer, to form the material of high-k (about 4.5-6.0).Wherein, this metal ion comprises hafnium (hafnium) and zirconium (zirconium).
Yet, though the gate dielectric of these new materials all has the characteristic of high-k, be applied on the semiconductor subassembly, but can cause the electrical change of assembly, for example: start voltage (V
Th) reduce, flat band voltage (V
Fb), electron mobility ... or the like, will destroy the original effect of assembly (fuction), still be unfavorable for the practical application manufacturing.
In view of this, in order to address the above problem, main purpose of the present invention is to provide a kind of gate dielectric and a kind of electrical method of improving gate dielectric of new material, and good gate dielectric not only is provided, and more can make this gate dielectric meet the demand that semiconductor subassembly designs.
Summary of the invention
The invention provides a kind of electrical method of improving gate dielectric, comprising following steps:
The semiconductor substrate is provided;
The electricity layer comprises hafnium oxide (HfO
2);
Implementing a hydrogen-containing gas handles; And
Implementing an oxygen-containing gas handles.
The described electrical method of improving gate dielectric wherein forms above-mentioned gate dielectric and also comprises before: with the above-mentioned semiconductor-based end of chemical solution cleans, to form a thin silicon oxide layer between the above-mentioned semiconductor-based end and above-mentioned gate dielectric.
The described electrical method of improving gate dielectric, wherein the thickness of above-mentioned thin silicon oxide layer is roughly 5-15 .
The described electrical method of improving gate dielectric, wherein above-mentioned gate dielectric are to utilize atomic layer chemical vapor deposition method (atomic layer chemical vapor deposition; ALCVD) form.
The described electrical method of improving gate dielectric, wherein the thickness of above-mentioned gate dielectric is roughly 20-50 .
The described electrical method of improving gate dielectric, the atmosphere pressures that wherein above-mentioned oxygen-containing gas is handled is roughly 0.1-10torr.
The described electrical method of improving gate dielectric, it is to be roughly under 700-900 ℃ in temperature to anneal that wherein above-mentioned oxygen-containing gas is handled.
The described electrical method of improving gate dielectric, the time that wherein above-mentioned oxygen-containing gas is handled is about 1-300 second.
The described electrical method of improving gate dielectric, the atmosphere that wherein above-mentioned oxygen-containing gas is handled comprises oxygen (O
2), nitric oxide (NO) or nitrous oxide (N
2O).
The described electrical method of improving gate dielectric, the atmosphere pressures that wherein above-mentioned hydrogen-containing gas is handled is roughly 10-70torr.
The described electrical method of improving gate dielectric, the temperature that wherein said hydrogen-containing gas is handled is roughly 600-1000 ℃.
A kind of gate dielectric of high-k is applicable between a semiconductor substrate and the grid layer, comprising:
One thin silicon oxide layer is arranged at above-mentioned substrate surface; And
One metal oxide layer is arranged at above-mentioned thin silicon oxide laminar surface, and wherein above-mentioned metal oxide layer comprises hafnium oxide (HfO
2).
A kind of MOS (metal-oxide-semiconductor) transistor with gate dielectric of high-k, comprising:
The semiconductor substrate;
The gate dielectric of one high-k is arranged at above-mentioned semiconductor-based basal surface, comprising:
One thin silicon oxide layer is arranged at above-mentioned substrate surface; And
One metal oxide layer is arranged at above-mentioned thin silicon oxide laminar surface, and wherein above-mentioned metal oxide layer comprises hafnium oxide (HfO
2);
One grid layer is arranged at above-mentioned metal oxide laminar surface; And
An one source pole district and a drain region are formed at the semiconductor-based basal surface of above-mentioned grid layer both sides respectively.
From last we can to draw advantage of the present invention as follows:
1. gate dielectric according to the present invention has high-k, and can effectively avoiding wearing then, effect takes place.
2. handle according to hydrogen-containing gas of the present invention, can make interface trap density (interface trap density by the defective in the hydrogen preparing structure; Dit) reduce.
3. handle according to oxygen-containing gas of the present invention, under high temperature, carry out, can control the skew of falt band voltage, make the falt band voltage of gate dielectric of the present invention keep close with the falt band voltage of known gate dielectric, help using, need not change component design.
4. according to gate dielectric of the present invention, have and be known as big equivalent oxide thickness (EOT), so can increase the physical thickness of gate dielectric of the present invention, increase processing procedure permission (process window).
5. handle with oxygen-containing gas according to hydrogen-containing gas of the present invention and handle, can make gate dielectric of the present invention, have good electron mobility (mobility), help using, need not change component design.
Description of drawings
It shown in Figure 1A to Fig. 1 I section of structure according to a preferred embodiment of the electrical method of improving gate dielectric of the present invention;
Shown in Figure 2 is the reaction mechanism schematic diagram of handling according to oxygen-containing gas of the present invention;
Shown in Figure 3 is electron mobility analysis chart according to a preferred embodiment of the electrical method of improving gate dielectric of the present invention.
Symbol description
The semiconductor-based end of 100-; The 102-thin silicon oxide layer;
The 104-hafnium oxide layer; The S300-hydrogen-containing gas is handled;
The S400-oxygen-containing gas is handled; The 106-grid;
The thin silicon oxide layer of 102a-after oxygen-containing gas is handled;
102b-patterning thin silicon oxide layer;
104a-patterning hafnium oxide layer
106a-patterning grid; 108-patterning cover curtain layer;
The 112-sept; S500-ion for the first time implants;
S600-ion for the second time implants; The S-source electrode;
The D-drain electrode.
Embodiment
Below please cooperate the section of structure referring to figs. 1A to Fig. 1 I, the schematic diagram of Fig. 2 and the electron mobility analysis chart of Fig. 3, illustrate according to a preferred embodiment of the present invention.
At first, please refer to Figure 1A, semiconductor substrate 100 is provided, its material comprises silicon (Si).Then, earlier with chemical solution, clean the semiconductor-based end 100, know impurity to remove surface, the semiconductor-based ends 100, just can form a thin silicon oxide layer 102 in semiconductor-based 100 surfaces, wherein the thickness of thin silicon oxide layer 102 is about 5-15 .
Then, please refer to Figure 1B, for example utilize atomic layer chemical vapor deposition method (atomic layerchemical vapor deposition; ALCVD) form metal oxide layer 104 in thin silicon oxide layer 102 surfaces, wherein metal oxide layer 104 comprises hafnium oxide (HfO
2), its dielectric constant is about 25, and thickness is roughly 20-50 .Form HfO
2Predecessor comprise H
2O and HfCl
4
According to the gate dielectric with high-k of the present invention, be applicable between a semiconductor substrate 100 and the grid layer, comprise that a thin silicon oxide layer 102 and that is arranged at substrate 100 surfaces is arranged at the metal oxide layer 104 on thin silicon oxide layer 102 surfaces, wherein above-mentioned metal oxide layer comprises hafnium oxide (HfO
2).The thickness of whole gate dielectric 102,104 is roughly 25-65 .
(material is silica (SiO usually compared to known gate dielectric
2)), dielectric constant is about 4, the main material hafnium oxide (HfO of gate dielectric of the present invention
2) dielectric constant be about 25.Therefore, the dielectric constant of gate dielectric of the present invention can effectively suppress leakage current (leakage) much larger than the dielectric constant of known gate dielectric, helps dwindling of size of components.So can reduce the equivalent oxide thickness (EOT) of gate dielectric, increase physical thickness.
Then, please refer to Fig. 1 C, implement a hydrogen-containing gas handling procedure S300.The atmosphere pressures of hydrogen-containing gas treatment S 300 is approximately 10-70torr, and temperature is approximately 600-1000 ℃, and the processing time is about 1-300 second.Hydrogen-containing gas treatment S 300 can utilize micromolecular hydrogen with the defective in the repairing gate dielectric layer structure, can effectively make suspension key (dangling bond) passivation, the reduced activity that are present in interface between high-k (high-k) material and the silicon base.
Then, please refer to Fig. 1 D, implement an oxygen-containing gas handling procedure S400.This step can be by feeding minor amounts of oxygen to implement in known cycle of annealing.The atmosphere pressures of oxygen-containing gas treatment S 400 is roughly 0.1-10tor, and temperature is approximately 700-900 ℃.And the atmosphere of oxygen-containing gas treatment S 400 comprises oxygen (O
2), nitric oxide (NO) or nitrous oxide (N
2O).
Please refer to Fig. 2, with the reaction mechanism of explanation oxygen-containing gas handling procedure S400.In general, the interface between high-k (high-k) material and silicon base often has more defective and produces, in order to make HfO
2Layer 104 perfect crystalline can carry out an annealing in process usually, yet under the high temperature, have SiO gas and disengage (shown in solid line) by silicon oxide layer 102, and cause the damage (damage) of silicon oxide layer.Yet a spot of oxygen atmosphere can suppress disengaging of SiO gas down, avoids producing defective.
Then, please refer to Fig. 1 E, can form a material on gate dielectric 102,104 surfaces for example is the grid layer 106 of polysilicon (poly silicon).
Then, please refer to Fig. 1 F, form earlier a cover curtain 108 with predetermined pattern, for example utilize earlier and revolve the figure method and form a photoresistance (photoresistor) comprehensively, see through again a light shield via the exposure imaging program so that the photoresistance patterning.Again with patterning cover curtain 108 for covering, patterned gate 106, metal oxide layer 104 and thin silicon oxide layer 102 in regular turn are till exposed portions serve substrate 100 surfaces.
Then, please refer to Fig. 1 G, with patterning grid 106a, patterning metal oxide layer 104a and patterning thin silicon oxide layer 102b is the cover curtain, ion implantation first time S500 is carried out in semiconductor substrate 100, to form lightly doped drain (lightly doped drain; LDD) 110 in the semiconductor-based ends 100 surface of grid 106 with whole gate dielectric 104a, 102b both sides.
Then, please refer to Fig. 1 H, utilize suitably deposition, etching step, forming a material on the sidewall of grid 106 and whole gate dielectric 104a, 102b for example is parting 112 between the nitride.
Then, please refer to Fig. 1 I, with patterning grid 106a, patterning metal oxide layer 104a, patterning thin silicon oxide layer 102b and sept 112 is the cover curtain, ion implantation second time S600 is carried out in semiconductor substrate 100, to form an one source pole district D (drain) and a drain region S (source), be formed at the surface, the semiconductor-based ends 100 of grid layer 106a both sides respectively.
So, just obtain MOS (metal-oxide-semiconductor) transistor of the present invention, comprising: the semiconductor-based end 100; Be arranged at high dielectric constant gate dielectric layer 104a, the 102b on surface, the semiconductor-based ends 100, comprise: the metal oxide layer 104a that is arranged at the thin silicon oxide layer 102b on substrate 100 surfaces and is arranged at thin silicon oxide layer 102b surface, wherein above-mentioned metal oxide layer comprises hafnium oxide (HfO
2); Be arranged at the surperficial grid layer 106a of metal oxide layer 104a; And the source area D and the drain region S that are formed at the surface, the semiconductor-based ends 100 of grid layer 106a both sides respectively.
Below please refer to table 1, superior efficacy of the present invention is described with experimental data.
Table 1
| Treatment conditions | EOT() | V fb(V) | RMS(％) | |
| A | 700℃，O 2，1torr | 18.4 | -0.6 | 8.7 |
| B | 800℃，O 2，1torr | 22.2 | -0.694 | 7.9 |
| C | 850℃，O 2，1torr | 24.4 | -0.708 | 7.5 |
| D | 900℃，O 2，1torr | 26.7 | -0.75 | 7.5 |
| E | 850℃，O 2，0.1torr | 22 | -0.714 | 8.4 |
| F | 900℃，O 2，0.1torr | 23.4 | -0.745 | 8.1 |
| G | 850℃，N 2，40torr | 20.1 | -0.717 | 7.8 |
| H | 900℃，N 2，40torr | 21.3 | -0.705 | 8 |
Table 1 show gate dielectric 102,104 according to the present invention at follow-up formation grid layer 106 behind its surface, handle 1 minute S300 down prior to 700 ℃ of hydrogen atmospheres after, contain the result of oxygen annealing in process S400 again according to the different disposal condition.Wherein, each torr N of G, H
2Contain 10
-6The O of torr
2
By in the table 1 as can be known, temperature is high more, flat band voltage (V
Fb) more little, get over convergence-0.95V (V of known silicon dioxide gate dielectric layer
Fb).Hence one can see that, and The high temperature anneal helps suppressing flat band voltage (V
Fb) skew.
For example relatively D, F and H can find that oxygen pressure is high more, and equivalent oxide thickness (EOT) is big more.This is owing to carry out high-temperature process under the atmosphere of elevated oxygen level, can generate oxide and be caused to increase gate dielectric layer thickness.But as previously mentioned, a spot of oxygen atmosphere can suppress disengaging of SiO gas down, avoids producing defective.
For example relatively A, B, C and D can find that temperature is high more, and RMS is more little.RMS calculates the resulting result of its r.m.s. by the thruster of capacitance-voltage (C-V) amount.RMS is big more, expression interface trap density (interface trap density; Dit) big more.Hence one can see that, and high-temperature process can reduce Dit.
Can obtain a preferred embodiment of hydrogen-containing gas treatment S 300 and oxygen-containing gas treatment S 400 by experimental result.The atmosphere pressures of hydrogen-containing gas treatment S 300 is about 40torr, in about 800 ℃ following of temperature, carries out about 1 minute.The atmosphere pressures of oxygen-containing gas treatment S 400 is about 0.1torr, in about 850 ℃ following of temperature, carries out about 1 minute.
Fig. 3 shows that gate dielectric according to the present invention is in the electron mobility (mobility) through the different disposal front and back.Curve A shows silicon dioxide (SiO
2) electron mobility result.Curve B is presented at the electron mobility result who carries out hydrogen-containing gas treatment S 300 under the low temperature (about 700 ℃) and carry out oxygen-containing gas treatment S 400 under low temperature (about 700 ℃).Curve C is presented at the electron mobility result who carries out hydrogen-containing gas treatment S 300 under the low temperature (about 700 ℃) and carry out oxygen-containing gas treatment S 400 under high temperature (about 800 ℃).Curve D is presented at the electron mobility result who carries out hydrogen-containing gas treatment S 300 under the high temperature (about 800 ℃) and carry out oxygen-containing gas treatment S 400 under high temperature (about 800 ℃).Hence one can see that, after hydrogeneous body treatment S 300 and oxygen-containing gas treatment S 400, can effectively improve the electron mobility of gate dielectric inside.Wherein, be good with the effect of carrying out oxygen-containing gas treatment S 400 under the high temperature again.
In addition, hydrogen-containing gas treatment S 300 can be applied to gate dielectric respectively separately with oxygen-containing gas treatment S 400, and its given efficacy is respectively arranged, and also can merge to be applied to gate dielectric, and its effect is had concurrently.Do not limited at this.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit scope of the present invention; anyly be familiar with this art person; without departing from the spirit and scope of the present invention; when can doing various changes and retouching, so protection scope of the present invention is as the criterion when looking claims institute confining spectrum.
Claims (12)
1, a kind of electrical method of improving gate dielectric is characterized in that may further comprise the steps:
The semiconductor substrate is provided;
Form a gate dielectric in above-mentioned semiconductor-based basal surface, wherein above-mentioned gate dielectric comprises hafnium oxide;
Implementing a hydrogen-containing gas handles; Then
Implement the annealing under the oxygen-containing gas environment, to suppress disengaging of silica gas.
2, the electrical method of improving gate dielectric as claimed in claim 1, also comprise before it is characterized in that forming above-mentioned gate dielectric: with the above-mentioned semiconductor-based end of chemical solution cleans, to form a thin silicon oxide layer between the above-mentioned semiconductor-based end and above-mentioned gate dielectric.
3, the electrical method of improving gate dielectric as claimed in claim 2, the thickness that it is characterized in that above-mentioned thin silicon oxide layer is 5-15 .
4, the electrical method of improving gate dielectric as claimed in claim 1 is characterized in that above-mentioned gate dielectric is to utilize the atomic layer chemical vapor deposition method to form.
5, the electrical method of improving gate dielectric as claimed in claim 1, the thickness that it is characterized in that above-mentioned gate dielectric is 20-50 .
6, the electrical method of improving gate dielectric as claimed in claim 1, the pressure that it is characterized in that the annealing under the above-mentioned oxygen-containing gas environment is 0.1-10torr.
7, the electrical method of improving gate dielectric as claimed in claim 1, the temperature that it is characterized in that the annealing under the above-mentioned oxygen-containing gas environment is 700-900 ℃.
8, the electrical method of improving gate dielectric as claimed in claim 1, the time that it is characterized in that the annealing under the above-mentioned oxygen-containing gas environment is 1-300 second.
9, the electrical method of improving gate dielectric as claimed in claim 1 is characterized in that the atmosphere of the annealing under the above-mentioned oxygen-containing gas environment comprises oxygen, nitric oxide or nitrous oxide.
10, the electrical method of improving gate dielectric as claimed in claim 1 is characterized in that the atmosphere pressures that above-mentioned hydrogen-containing gas is handled is 10-70torr.
11, the electrical method of improving gate dielectric as claimed in claim 1 is characterized in that the temperature that described hydrogen-containing gas is handled is 600-1000 ℃.
12, the electrical method of improving gate dielectric as claimed in claim 1, it is characterized in that also comprising forming a grid layer on this gate dielectric, wherein the annealing steps under this hydrogen-containing gas treatment step and this oxygen-containing gas environment is to carry out before forming this grid layer.
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| CN1320606C true CN1320606C (en) | 2007-06-06 |
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| JP2010021295A (en) | 2008-07-09 | 2010-01-28 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
| CN103578947B (en) * | 2012-07-26 | 2015-12-16 | 中芯国际集成电路制造(上海)有限公司 | A kind of high dielectric metal gates manufacture method |
| CN108257915A (en) * | 2016-12-28 | 2018-07-06 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
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| US6511875B2 (en) * | 2000-06-28 | 2003-01-28 | Hyundai Electronics Industries Co., Ltd. | Method for making high K dielectric gate for semiconductor device |
| US6511925B1 (en) * | 2001-10-19 | 2003-01-28 | Lsi Logic Corporation | Process for forming high dielectric constant gate dielectric for integrated circuit structure |
| CN1396638A (en) * | 2001-06-28 | 2003-02-12 | 夏普公司 | Method for dipositing high-dielectric constant material on chip using atomic layer diposition method |
| WO2003012850A1 (en) * | 2001-07-26 | 2003-02-13 | Motorola, Inc. | Selective metal oxide removal |
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2003
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| US6107656A (en) * | 1997-06-06 | 2000-08-22 | Oki Electric Industry Co., Ltd. | Ferroelectric transistors, semiconductor storage devices, method of operating ferroelectric transistors and method of manufacturing ferromagnetic transistors |
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| US6511875B2 (en) * | 2000-06-28 | 2003-01-28 | Hyundai Electronics Industries Co., Ltd. | Method for making high K dielectric gate for semiconductor device |
| US6436777B1 (en) * | 2000-10-19 | 2002-08-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
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