CN1314133C - Dual channel accumulation type varactor and method for making same - Google Patents
Dual channel accumulation type varactor and method for making same Download PDFInfo
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- CN1314133C CN1314133C CNB031374360A CN03137436A CN1314133C CN 1314133 C CN1314133 C CN 1314133C CN B031374360 A CNB031374360 A CN B031374360A CN 03137436 A CN03137436 A CN 03137436A CN 1314133 C CN1314133 C CN 1314133C
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Abstract
The present invention discloses a double channel accumulation type variable capacitance tube and a making method thereof. The method comprises the following steps: according to a method of making a single channel variable capacitance tube, a bottom layer channel, a first grid oxide layer, a grid, a side wall, a source and a drain are made; after the injection of the source and the drain, a second grid oxide layer is deposited or oxidized along the source, the side wall, the grid and the upper part of the drain of the single channel variable capacitance tube; successively, an in situ doped polycrystalline silicon layer is deposited on the second grid oxide layer to be used as a top layer channel; the lead-out holes of the source and the drain are respectively arranged on two sides where the lead-out holes pass through the second grid oxide layer and the polycrystalline silicon layer, and metal lead wires are led out through the lead-out holes so as to connect the top layer channel with the bottom layer channel, and thus, a double channel structural variable capacitor is formed. The present invention uses a single grid to control two channels at the same time. On the premise of retaining the quality factor equivalent to the single channel variable capacitance tube, the present invention doubles the variable capacitance range of the traditional single channel variable capacitance tube and has wide application prospect.
Description
Technical field
The present invention relates to a kind of semiconductor device, relate to a kind of dual channel accumulation type MOS varactor and manufacture method thereof specifically, described dual channel accumulation type MOS varactor uses as variable capacitance in radio circuit usually.
Background technology
Along with the development of Modern wireless communication, radio circuit is more and more higher to the performance requirement of wherein passive device.Variable capacitance is one of most important passive device in the radio circuit system.Traditional anti-inclined to one side PN junction variable capacitor structure transfiguration scope is less, quality factor is lower, and the MOS technology of technology and extensive use is incompatible, so people have proposed some capacitance structures based on the MOS technology.These variable capacitor structures are greatly improved than the transfiguration scope of PN junction electric capacity, but because that quality factor and transfiguration scope reach optimum condition is conflicting, in order to reach the purpose that enlarges the transfiguration scope, need be cost to reduce quality factor usually, this have limited the extensive use of MOS transfiguration structure to a great extent.
Summary of the invention
At above-mentioned the deficiencies in the prior art, main purpose of the present invention is to have proposed a kind of dual channel accumulation type MOS varactor (with the two ditch varactors of hereafter), described pair of ditch varactor improves a lot than traditional accumulation type MOS variable capacitance (hereinafter to be referred as single ditch varactor) transfiguration scope, and can keep and the suitable quality factor of single ditch varactor.
Another object of the present invention is the manufacture method that has proposed a kind of dual channel accumulation type MOS varactor.
Technical scheme of the present invention is:
A kind of dual channel accumulation type varactor comprises by substrate, lower floor's raceway groove, first grid oxide layer, Duo Qiang, grid and the deposit of drain electrode top or oxidation one deck second gate oxide, and deposit one deck polysilicon again on the top of second gate oxide constitutes top-layer channel; The metal lead-out wire is drawn from source electrode and drain electrode respectively, and pass the polysilicon on second gate oxide and upper strata, source electrode, drain electrode and last lower channel are communicated with, thereby form the variable capacitance of double channel structure, control the state of two raceway grooves by a grid simultaneously.The polysilicon on upper strata is in-situ doped polysilicon, and its doping type is identical with the type of described lower floor raceway groove.
A kind of manufacture method of dual channel accumulation type varactor, comprise: according to the method for making single ditch varactor, make lower floor's raceway groove, polysilicon gate, side wall, inject source electrode, drain electrode, (for the short channel situation, here also may carry out autoregistration silication (being salicide) to reduce the contact resistance of source, leakage, grid), after source electrode, drain electrode are injected, along source electrode, side wall, grid and the deposit of drain electrode top or oxidation one deck second gate oxide of single ditch varactor; The then in-situ doped polysilicon of deposit one deck again on second gate oxide is as top-layer channel; Offer source electrode, drain electrode fairlead respectively in both sides, fairlead connects second gate oxide and upper strata polysilicon, the metal lead-out wire passes from fairlead and constitutes source electrode, drain electrode, and top-layer channel and lower floor's raceway groove are communicated with, thereby forms the variable capacitance of double channel structure.
One stack features structural parameters of described capacitance structure are: the horizontal long 0.25-2.5 μ of grid m, grid width is not limit (vertical paper direction), the thick 0.05-0.5 μ of polysilicon gate m, the thick 0.1-0.5 μ of upper strata polysilicon raceway groove m, first grid oxidated layer thickness 3-20nm, the second gate oxide thickness 3-20nm, SOI silicon film thickness 0.05-0.23 μ m, bury oxygen thickness 0.08-0.45 μ m, lower floor's channel doping concentration 2 * 10
16-2 * 10
18Cm
-3, the in-situ doped concentration 2 * 10 of upper strata polysilicon raceway groove
16-2 * 10
18Cm
-3, doping content 1 * 10 is leaked in the source
19-1 * 10
21Cm
-3
All these parameters can be regulated according to circuit requirement (as the capacitance size that requires) and process conditions etc.
The present invention on the polysilicon gate top of single ditch varactor structure again by deposit one deck gate oxide and the in-situ doped polysilicon of one deck, form another raceway groove, utilize the exit of source electrode and drain electrode that two raceway grooves are connected, can change two CHARGE DISTRIBUTION states in the raceway groove simultaneously by changing grid voltage like this, play the purpose that enlarges the transfiguration scope, keeping under its quality factor prerequisite suitable with single ditch varactor, the transfiguration scope is increased be the twice of traditional single ditch varactor, therefore have broad application prospects.
Description of drawings
Fig. 1 is the two ditch varactor structure schematic diagrames of N type that the present invention is based on the SOI substrate.
Fig. 2 is the two ditch varactor structure schematic diagrames of N type that the present invention is based on the body silicon substrate.
Fig. 3 is the two ditch varactor structure schematic diagrames of P type that the present invention is based on the SOI substrate.
Fig. 4 is the transfiguration characteristic comparison diagram of single ditch varactor of two ditch varactors (as shown in Figure 1) of N type SOI substrate and N type SOI substrate.
Fig. 5 is the characteristic comparison diagram that the quality factor of single ditch varactor of two ditch varactors (as shown in Figure 1) of N type SOI substrate and N type SOI substrate changes with gate voltage.
Fig. 6 is the transfiguration characteristic comparison diagram of single ditch varactor of two ditch varactors (as shown in Figure 2) of N type body silicon substrate and N type body silicon substrate.
Fig. 7 is the two ditch varactors of P type raceway groove, SOI substrate (as shown in Figure 3) and P type body silicon substrate and the transfiguration characteristic comparison diagram of P type list raceway groove varactor.
Fig. 8 is the transfiguration characteristic comparison diagram of two ditch varactors (as shown in Figure 3) of P type SOI substrate and P type SOI substrate list raceway groove varactor.
Embodiment
Innovation of the present invention is that polysilicon gate top at single ditch varactor structure is again by deposit one deck grid oxygen and the in-situ doped polysilicon of one deck, form a raceway groove, utilize the source, leak and draw two raceway grooves connections, by changing grid voltage, can change the CHARGE DISTRIBUTION state in two raceway grooves simultaneously like this.For the raceway groove of N type, along with grid voltage by negative to just increasing, the state of two raceway grooves all is to change to accumulation by exhausting, the electric capacity of correspondence changes from small to big.And two channel capacitances are relations in parallel, so the total capacitance of total is changed from small to big.Because be two raceway grooves, so the transfiguration scope has greatly increased than traditional accumulation type mos capacitance, this advantage all has embodiment on body silicon substrate, SOI substrate; And mix and the raceway groove of P type doping also all is suitable for for the N type.
The present invention will be described in detail below in conjunction with the analysis of accompanying drawing and Computer simulation results.
The of the present invention pair of ditch varactor structure schematic diagram such as Fig. 1, Fig. 2 and shown in Figure 3 are respectively the two ditch varactor structure schematic diagrames of N type SOI substrate, the two ditch varactor structure schematic diagrames of N type body silicon (bulk) substrate and the two ditch varactor schematic diagrames of P type SOI substrate.
For Fig. 1, contain the elementary cell of traditional N type list ditch varactor structure in the structure: substrate, raceway groove is with source electrode, drain electrode, the polysilicon gate of raceway groove with doping type.According to the manufacture method of traditional single ditch varactor, silicon chip is carried out raceway groove inject, form lower floor's raceway groove; Make first grid oxide layer 11, polysilicon gate 12; Make side wall 13, carry out source drain then and inject, (for the short channel situation, also may carry out autoregistration silication (being salicide) here to reduce the contact resistance of source, leakage, grid) also realized doping to polysilicon gate simultaneously.Characteristics of the present invention are: after traditional single ditch varactor has been made side wall, source drain injection; clean and inject protective layer; deposit or oxidation obtain second gate oxide 14 then, and the thickness of its thickness and first grid oxide layer 11 is suitable, if two-layer gate oxide thickness is respectively t
Ox1, t
Ox2, then the maximum of two ditch varactor total capacitances can be by C
Max=A* ε
0* ε
Sio2/ t
Ox1+ A* ε
0* ε
Sio2/ t
Ox2Estimation.Under the desirable process conditions, the thickness of second gate oxide can be identical with first grid oxide layer, then total capacitance maximum C
Max=2*C
Ox=2A* ε
0* ε
Sio2/ t
Ox(A is the capacitor plate area in the formula, ε
0Be permittivity of vacuum, ε
Sio2Be SiO
2Relative dielectric constant).
The polysilicon 16 of deposit one deck in-situ doped (its doping type is identical with the doping type of former lower floor raceway groove) again on second gate oxide 14 then, with this as second raceway groove; The fairlead of source drain connects second gate oxide 14, and last raceway groove couples together by metal lead wire 15 and lower floor's raceway groove, thereby has just formed the variable capacitance of double channel structure.On manufacture craft, this structure has only increased by two steps on traditional CMOS technology, and does not have special alignment requirements, thus with the traditional cmos process compatibility.
Need to prove: no matter whether carried out the autoregistration silication in the single ditch varactor of tradition manufacture method is salicide, can realize the variable capacitance of double channel structure on this basis.The doping type of described source electrode, drain electrode, polysilicon gate is the very high heavy doping of doping content, and concentration is 1 * 10
19Cm
-3More than.
One group of typical structural parameters of Fig. 1 is: the long 0.9 μ m of horizontal grid, grid width 3000 μ m (vertical paper direction), the thick 0.05 μ m of polysilicon gate, the thick 0.3 μ m of upper strata polysilicon raceway groove, first grid oxidated layer thickness 10.5nm, the second gate oxide thickness 10.5nm, SOI silicon film thickness 0.1 μ m, bury oxygen thickness 0.37 μ m, substrate doping 2 * 10
17Cm
-3, the in-situ doped concentration 2 * 10 of upper strata polysilicon raceway groove
17Cm
-3, doping content 1 * 10 is leaked in the source
20Cm
-3
Fig. 2 typical structure parameter is: junction depth 0.1 μ m, (scope of planting of getting of junction depth is 0.05-0.5 μ m), all the other are the same.
Fig. 3 is two ditch varactor structure schematic diagrames of P type doping SOI substrate.The difference of it and N type structure only is that doping type everywhere is all opposite, all is the doping of P type.Two ditch varactor structures of P type body silicon substrate are also similar, and structural parameters are with Fig. 1 structure.
Need to specify: all these structures, gate electrode all are to draw in the side, not on the main cross section, thus in Fig. 1 and Fig. 3, do not reflect, but this does not influence following analysis and conclusion.
With Fig. 1 structure is the working method and the principle of example explanation variable capacitor structure of the present invention: during electric capacity work, and source electrode (S), drain electrode (D), the substrate utmost point (B) all connects same current potential, and is voltage reference points with them.Change electric capacity by changing grid (G) voltage.When grid potential for more greatly on the occasion of the time, the power line that grid sends attracts electronics, two channel surface of variable capacitance all accumulate electronics (promptly being in accumulated state), the electric capacity of two raceway groove correspondences all is grid oxygen capacitor C ox, these two electric capacity are relations in parallel, therefore total capacitance should be 2Cox (and traditional single-channel MOS electric capacity, maximum capacitor only is Cox).Along with grid potential reduces, attract the ability of electronics to reduce, the surface of two raceway grooves all becomes spent condition by accumulation gradually, therefore is equivalent to the depletion-layer capacitance of having connected on grid oxygen electric capacity separately, so its total capacitance reduces.Grid potential is more little, and its depletion width is wide more, and electric capacity is more little.When two raceway grooves all reach when exhausting entirely, depletion width no longer changes with gate voltage, and then electric capacity keeps minimum no longer to change.
Characteristics of the present invention have been to form the double channel of single grid-control system, therefore can be on area identical, increase attainable maximum capacitor Cmax (as a result of, its minimum capacity Cmin also increases), thereby increased the transfiguration scope (Cmax-Cmin) of variable capacitance.
Analyze (transactional analysis) with the AC among the device simulation device ISE8.0 this double channel structure and traditional single channel structure are simulated, the extraction result to these simulations analyzes comparison below:
Fig. 4 is the SOI substrate, and the transfiguration scope characteristic of single ditch varactor of the two ditch varactors (as shown in Figure 1) of N type doping and its correspondence compares, and promptly gate capacitance compares with the characteristic of the variation of gate voltage.Wherein symbol sc (Single Channel) represents single channel structure, and dc (Double Channel) represents double channel structure (as follows).This result shows that single ditch varactor structure has the maximum capacitor value when gate voltage is maximum, and being about Cox (can be according to C
Ox=A* ε
0* ε
Sio2/ t
OxEstimation).The maximum capacitor of two ditch varactor structures then is slightly larger than 2Cox, and this is because of the thinner thickness of side wall in the simulation, and near gate oxide thickness, polysilicon gate has constituted parasitic capacitance by the deposit polysilicon of side wall and both sides, makes electric capacity increase.Adopt the transfiguration scope of Cmax-Cmin definition, the double channel structure has increased 108% than the transfiguration scope of single channel structure.
From the N type of Fig. 5 mix single raceway groove, double channel varactor quality factor comparison diagram, see that the double channel structure has still kept the quality factor characteristic roughly suitable with single channel structure when the transfiguration scope increases.Specifically, at voltage hour, the double channel quality factor is higher; When voltage was big, single channel structure quality factor was higher.If get the mean value in effective transfiguration scope, then the two is close.
Fig. 6 is the two ditch varactors (as shown in Figure 2) of body silicon substrate and the transfiguration characteristic comparison diagram of conventional single ditch varactor structure.As seen its result is similar with the comparison diagram of SOI substrate.Maximum capacitor Cmax, the Cmin of double channel structure is big than single channel structure, and total transfiguration scope has increased 114%.
SOI substrate, body silicon substrate that Fig. 7 mixes for the P type, single ditch varactor and two ditch varactor capacitance characteristic contrast.The mix operation principle of two ditch varactors of P type is identical with N type situation, and different is, when gate voltage than hour, two channel surface are in accumulated state, and electric capacity is bigger, increase with voltage, raceway groove exhausts, and total capacitance diminishes, its electric capacity with the variation tendency of voltage and N type mix opposite.Fig. 7 shows, the double channel structure is than the transfiguration scope of traditional single channel structure, and it is many all to have increased one times of summary.
Fig. 8 is the quality factor comparison diagram of the two ditch varactors of P type doping SOI substrate and single ditch varactor, and identical with N type comparing result, both quality factors also are in same level.Consider that side wall is much thicker than side wall value in the simulation in the actual process, so the maximum capacitor of two ditch varactors will be about 2Cox in the actual process, therefore the transfiguration scope of expection is the twice of traditional single ditch varactor.
To sum up, dual channel accumulation type MOS variable capacitance of the present invention can keep improving the transfiguration scope largely, and having good processing compatibility under the suitable situation of quality factor with the single ditch varactor of tradition.These advantages are all set up for N type doped channel and P type doped channel for SOI substrate, body silicon substrate.Each structural parameters also can be regulated with technological level according to actual needs, has very big flexibility.When being applied to radio circuit, the trend that replaces anti-PN junction diode capacitance partially and traditional single ditch mos capacitance is arranged, have boundless application prospect.
It should be noted last that: above embodiment is the unrestricted technical scheme of the present invention in order to explanation only, although the present invention is had been described in detail with reference to the foregoing description, those of ordinary skill in the art is to be understood that: still can make amendment or be equal to replacement the present invention, and not breaking away from any modification or partial replacement of the spirit and scope of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (9)
1, a kind of dual channel accumulation type varactor, comprise single ditch varactor of forming by substrate, lower floor's raceway groove, first grid oxide layer, polysilicon gate, side wall, source electrode, drain electrode, it is characterized in that, source electrode, side wall, grid and the deposit of drain electrode top or oxidation one deck second gate oxide along single ditch varactor, deposit one deck polysilicon again on the top of second gate oxide constitutes top-layer channel; The metal lead-out wire is drawn from source electrode and drain electrode respectively, and passes the polysilicon on second gate oxide and upper strata, source electrode, drain electrode and last lower channel are communicated with, thus the variable capacitance of formation double channel structure; The polysilicon on described upper strata is in-situ doped polysilicon, and its doping type is identical with the type of described lower floor raceway groove.
2, according to claim 1 or described dual channel accumulation type varactor, it is characterized in that: the doping content of the doping content of top-layer channel and described lower floor raceway groove is suitable, and the doping content scope is 2 * 10
16-2 * 10
18Cm
-3
3, according to claim 1 or described dual channel accumulation type varactor, it is characterized in that: the thickness of described upper strata second gate oxide is suitable with former first grid thickness of oxide layer, and thickness range is 0.003-0.02 μ m.
4, dual channel accumulation type varactor according to claim 1 is characterized in that: described substrate, its type are the SOI substrate, or the body silicon substrate.
5, dual channel accumulation type varactor according to claim 1 is characterized in that: the doping type of described raceway groove, the doping type that comprises source electrode, drain electrode, polysilicon gate are N type or P type.
6, dual channel accumulation type varactor according to claim 1, it is characterized in that: the doping type of described source electrode, drain electrode, polysilicon gate is heavy doping, and concentration is 1 * 10
19Cm
-3More than.
7, dual channel accumulation type varactor according to claim 4, it is characterized in that: described varactor based on the SOI substrate, one group typical structural parameters is: the horizontal long 0.25-2.5 μ of grid m, and grid width is not limit, the thick 0.05-0.5 μ of polysilicon gate m, the thick 0.1-0.5 μ of upper strata polysilicon raceway groove m, first grid oxidated layer thickness 3-20nm, the second gate oxide thickness 3-20nm, SOI silicon film thickness 0.05-0.23 μ m, bury oxygen thickness 0.08-0.45 μ m, lower floor's channel doping concentration 2 * 10
16-2 * 10
18Cm
-3, the in-situ doped concentration 2 * 10 of upper strata polysilicon raceway groove
16-2 * 10
18Cm
-3, doping content 1 * 10 is leaked in the source
19-1 * 10
21Cm
-3
8, dual channel accumulation type varactor according to claim 4, it is characterized in that: described varactor based on the body silicon substrate, one group typical structural parameters is: the horizontal long 0.25-2.5 μ of grid m, grid width is not limit, the thick 0.05-0.5 μ of polysilicon gate m, the thick 0.1-0.5 μ of upper strata polysilicon raceway groove m, first grid oxidated layer thickness 3-20nm, the second gate oxide thickness 3-20nm, lower floor's channel doping concentration 2 * 10
17Cm
-3, the in-situ doped concentration 2 * 10 of upper strata polysilicon raceway groove
17Cm
-3, doping content 1 * 10 is leaked in the source
19-1 * 10
21Cm
-3, junction depth 0.05-0.5 μ m.
9, a kind of manufacture method of dual channel accumulation type varactor, comprise: according to the method for making single ditch varactor, make lower floor's raceway groove, first grid oxide layer, polysilicon gate, side wall, inject source electrode, drain electrode, it is characterized in that: after source electrode, drain electrode are injected, along source electrode, side wall, grid and the deposit of drain electrode top or oxidation one deck second gate oxide of single ditch varactor; The then in-situ doped polysilicon of deposit one deck again on second gate oxide is as top-layer channel; Offer source electrode, drain electrode fairlead respectively in both sides, fairlead connects second gate oxide and upper strata polysilicon, the metal lead-out wire passes from fairlead and constitutes source electrode, drain electrode, and top-layer channel and lower floor's raceway groove are communicated with, thereby forms the variable capacitance of double channel structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031374360A CN1314133C (en) | 2003-06-20 | 2003-06-20 | Dual channel accumulation type varactor and method for making same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031374360A CN1314133C (en) | 2003-06-20 | 2003-06-20 | Dual channel accumulation type varactor and method for making same |
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| CN1314133C true CN1314133C (en) | 2007-05-02 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7941886B2 (en) | 2003-09-19 | 2011-05-17 | Braun Gmbh | Toothbrushes |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102122654B (en) * | 2010-01-08 | 2012-12-05 | 中芯国际集成电路制造(上海)有限公司 | Varactor and manufacturing method thereof |
| CN108574017B (en) * | 2017-03-07 | 2021-08-06 | 中芯国际集成电路制造(上海)有限公司 | Varactor and method of forming the same |
| CN111602254B (en) * | 2020-04-22 | 2021-03-23 | 长江存储科技有限责任公司 | Variable capacitor |
| CN116779664A (en) * | 2023-08-22 | 2023-09-19 | 深圳芯能半导体技术有限公司 | IGBT chip with interelectrode capacitance structure and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4251767A (en) * | 1978-08-25 | 1981-02-17 | Montana Donald M | Dual channel capacitance measurement device |
| CN1108817A (en) * | 1993-11-23 | 1995-09-20 | 摩托罗拉公司 | Varactor and method of forming |
| US5909615A (en) * | 1996-02-28 | 1999-06-01 | International Business Machines Corporation | Method for making a vertically redundant dual thin film transistor |
-
2003
- 2003-06-20 CN CNB031374360A patent/CN1314133C/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4251767A (en) * | 1978-08-25 | 1981-02-17 | Montana Donald M | Dual channel capacitance measurement device |
| CN1108817A (en) * | 1993-11-23 | 1995-09-20 | 摩托罗拉公司 | Varactor and method of forming |
| US5909615A (en) * | 1996-02-28 | 1999-06-01 | International Business Machines Corporation | Method for making a vertically redundant dual thin film transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7941886B2 (en) | 2003-09-19 | 2011-05-17 | Braun Gmbh | Toothbrushes |
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| CN1567596A (en) | 2005-01-19 |
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