CN1301556C - CMOS assembly and its manufacturing method - Google Patents
CMOS assembly and its manufacturing method Download PDFInfo
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- CN1301556C CN1301556C CNB2004100296914A CN200410029691A CN1301556C CN 1301556 C CN1301556 C CN 1301556C CN B2004100296914 A CNB2004100296914 A CN B2004100296914A CN 200410029691 A CN200410029691 A CN 200410029691A CN 1301556 C CN1301556 C CN 1301556C
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Abstract
The present invention provides a CMOS assembly and a manufacturing method thereof. The CMOS assembly comprises a structure that a grid electrode is arranged on a substrate, a source electrode/drain electrode is arranged in the substrate on both sides of the grid electrode, a stress buffering lining which is compliantly configured on both of the two sides of the grid electrode partially extends to a substrate surface, a stress layer which is arranged on the grid electrode, the stress buffering lining and the source electrode/drain electrode is in contact with the stress buffering lining, and the stress of a passage area in the substrate below the grid electrode is enhanced.
Description
Technical field
The present invention relates to a kind of cmos component and manufacture method thereof, particularly a kind of method and structure thereof of utilizing local mechanical Stress Control (local mechanical-stress control is called for short LMC) to increase the usefulness of cmos component.
Background technology
In present semiconductor subassembly, be to use silicon integral body (Sibulk) as substrate, and reach the purpose of high speed operation and low power consumption by dwindling size of components.Yet size of components dwindles near the limit of physics and the limit of cost at present.Therefore, other is different from the technology of the method for minification to need development, reaches the purpose of high speed operation and low power consumption.
Therefore, the someone proposes to utilize at transistorized channel region the mode of Stress Control, overcomes the limit of assembly downsizing.The method is to change the silicon crystal lattice spacing by applied stress, increases the mobility in electronics and hole.
Common method places Si-Ge layer (being in tensile stress) to go up the channel layer of the silicon layer (tensile-strained Si layer) of tensile stress as nmos pass transistor for using, and the germanium-silicon layer (compressive-strained Si-Ge layer) (being in compression stress) of use compressive tension is as the transistorized channel layer of PMOS.By the Si-Ge layer of silicon layer that uses tensile stress and compressive tension channel layer, can increase the mobility in surface electronic and hole, and reach the purpose of high speed operation and low-yield consume simultaneously as MOS transistor.
Yet, there are some problems in this technology, when the Si-Ge layer (p channel layer) of Si layer (n channel layer) that forms tensile stress simultaneously and compressive tension during as the channel layer of CMOS, it is very complicated that technology can become, and to want selectivity to form NMOS channel layer and PMOS channel layer be suitable difficulty.And, when forming the Si-Ge layer by high-temperature heat treatment, the separation (segregation) of dislocation (dislocation) or generation Ge can take place, and make the characteristic degradation of grid breakdown voltage.
In addition, have research and utilization to produce stress as the silicon nitride layer that contact hole etching stops layer recently, influence the transistor electric current of tending to act, this technology is called the local mechanical Stress Control.By the compression stress that increase adds, can improve the transistorized mobility of PMOS; By the compression stress that minimizing adds, can improve the mobility of nmos pass transistor.
Though the above-mentioned method of utilizing silicon nitride layer generation stress to improve performance of transistors uses the method for Si-Ge resilient coating simple, its effect that can improve is limited.
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of cmos component structure and manufacture method thereof, utilize the technology of local mechanical Stress Control, further improve transistorized usefulness.
According to a kind of cmos component that purpose of the present invention provided, its structure comprises to be located at gate electrode in the substrate, source/drain is located in the gate electrode substrate on two sides, with stress buffer lining compliance be disposed at the gate electrode both sides and part extends to substrate surface, and stressor layers is located on gate electrode, stress buffer lining and the source/drain, and contact with the stress buffer lining, use the stress that improves the channel region in the gate electrode below substrate.
Specifically, cmos component provided by the present invention, its structure comprises:
One substrate;
One gate electrode is located in this substrate;
Source is located in this substrate of these gate electrode both sides;
One stress buffer lining is configured in to compliance these gate electrode both sides and part extends to this substrate surface; And
One stressor layers is located on this gate electrode, this stress buffer lining and this source/drain, and contacts with this stress buffer lining, uses the stress that improves the channel region in this gate electrode this substrate of below.
Wherein, if above-mentioned stressor layers tool tensile stress, being covered in the gate electrode of stressor layers below and the transistor of source/drain formation is PMOS transistor and nmos pass transistor.If above-mentioned stressor layers tool compression stress, being covered in the gate electrode of stressor layers below and the transistor of source/drain formation is the PMOS transistor.
In addition, the present invention also provides another kind of cmos component, its structure comprises to be located at gate electrode in the substrate that is provided with at least one barrier assembly, comprise one first stressor layers in this shallow trench barrier assembly, be located at source/drain in the gate electrode substrate on two sides and contact above-mentioned barrier assembly, with stress buffer lining compliance be disposed at the gate electrode both sides and part extends to substrate surface, and second stressor layers is located at gate electrode, on stress buffer lining and the source/drain, and contact with the stress buffer lining, by above-mentioned first stressor layers and second stressor layers to improve the stress of the channel region in the gate electrode below substrate.
Wherein, if when the above-mentioned second stressor layers tool tensile stress and the first stressor layers tool tensile stress, being covered in the gate electrode of second stressor layers below and transistor that source/drain constitutes is PMOS transistor and nmos pass transistor.If when compression of the above-mentioned second stressor layers tool compression stress and the first stressor layers tool or tensile stress, being covered in the gate electrode of second stressor layers below and transistor that source/drain constitutes is the PMOS transistor.
The present invention also provides the manufacture method of described a kind of cmos component simultaneously, and its method is as described below.At first the active area in substrate forms gate electrode, and the active area in the gate electrode substrate on two sides forms a shallow doped region.Then, compliance ground forms the stress buffer lining and extends to substrate surface in the gate electrode both sides and partly, and forms a clearance wall on the stress buffer lining of gate electrode both sides.Then do not formed a heavily doped region by the active area in the substrate of gate electrode and clearance wall covering in the gate electrode both sides, wherein above-mentioned shallow doped region and heavily doped region constitute source.Behind the source/drain regions to be formed, then remove clearance wall, and on gate electrode, stress buffer lining and source/drain, cover a stressor layers, and contact, use the stress that improves the channel region in the gate electrode below substrate with the stress buffer lining.
Moreover the present invention also provides the manufacture method of described another kind of cmos component, and its method is as described below.At first the active area in substrate forms gate electrode, and wherein above-mentioned active area is defined by being formed at intrabasement at least one barrier assembly, and contains one first stressor layers in this barrier assembly.Then the active area in the gate electrode substrate on two sides forms a shallow doped region and contacts above-mentioned barrier assembly.Then, compliance ground forms the stress buffer lining and extends to substrate surface in the gate electrode both sides and partly, and forms a clearance wall on the stress buffer lining of gate electrode both sides.Then do not formed a heavily doped region by the active area in the substrate of gate electrode and clearance wall covering in the gate electrode both sides, wherein above-mentioned shallow doped region and heavily doped region constitute source.Behind the source/drain regions to be formed, then remove clearance wall, and on gate electrode, stress buffer lining and source/drain, cover one second stressor layers, and contact with the stress buffer lining, by above-mentioned first stressor layers and second stressor layers to improve the stress of the channel region in the gate electrode below substrate.
In above-mentioned technology, before removing clearance wall, can comprise that more carrying out one aims at silicide process automatically, forms a metal silicide with the surface in source/drain.
In addition, also can after remove this clearance wall, carry out one and aim at silicide process automatically, form a metal silicide with surface in source/drain.
The thickness of above-mentioned stress buffer lining is preferably less than 500 dusts, and material can be silica.
The material of above-mentioned stressor layers can be the laminated of silicon nitride (SiN), silicon oxynitride (SiON) or silicon nitride (SiN) and silicon oxynitride (SiON).Its formation method comprises plasma enhanced chemical vapor deposition method (PECVD), rapid hot technics chemical vapour deposition technique (RTCVD), atomic level chemical vapour deposition technique (ALCVD) or Low Pressure Chemical Vapor Deposition (LPCVD).
In the manufacture method of above-mentioned cmos component, more can may further comprise the steps: on the stressor layers or second stressor layers, form an inner layer dielectric layer; With the stressor layers or second stressor layers is etching stopping layer, etches a contact window in inner layer dielectric layer; And remove the stressor layers or second stressor layers in the contact window.
In sum, utilize structure provided by the present invention and method, can use the transistor that forms characteristic with mechanical stress concentration at channel region with high speed operation and low-yield consume.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
Figure 1A to Fig. 1 E is the schematic diagram that illustrates the manufacture method of a kind of cmos component of the present invention.
Fig. 2 A to Fig. 2 G is the schematic diagram that illustrates the manufacture method of the another kind of cmos component of the present invention.
Embodiment
Show according to result of study,, when compression stress that increases channel region or tensile stress, can increase the mobility of hole carrier P channel-style transistor.For N channel-style transistor, when reducing the compression stress of channel region, when also promptly increasing the tensile stress of channel region, can increase the mobility of electronics carrier.In order to increase the mobility of carrier, therefore the invention provides a kind of structure and manufacture method thereof of cmos component of the stress that can effectively increase channel region at channel region.
Structure:
The invention provides a kind of structure of cmos component, shown in Fig. 1 D.In this structure, gate electrode 104 is to be located in the substrate 100, and source/drain S/D is located in gate electrode 104 substrate on two sides 100.Wherein, the material of gate electrode 104 can be polysilicon, metal, SiGe or germanic polysilicon.
In addition, at gate electrode 104 and substrate 100 gate dielectric 102 is set, its material can be silica.
Then, stressor layers 118 is located on gate electrode 104, stress buffer lining 110 and the source/drain .S/D, and contacts with stress buffer lining 110, use the stress that improves the channel region 114 in the gate electrode 104 below substrates 100 with gate electrode 104.Wherein, the material of stressor layers 118 is the laminated of silicon nitride (SiN), silicon oxynitride (SiON) or silicon nitride (SiN) and silicon oxynitride (SiON).
If these stressor layers 118 tool tensile stresses cover the gate electrode 104 of stressor layers 118 belows and the transistor of source/drain S/D formation and then are PMOS transistor and nmos pass transistor.
If these stressor layers 118 tool compression stresses cover the gate electrode 104 of stressor layers 118 belows and the transistor of source/drain S/D formation and then are the PMOS transistor.
In addition, between stressor layers 118 and source/drain S/D, a metal silicide layer 116 is set, uses the sheet resistor that reduces source/drain S/D, it also shows suitable compression stress, can promote the PMOS performance of transistors.Usually, between stressor layers 118 and gate electrode 104, the metal silicide layer 116 of identical material can be set also.
In addition, also can adopt ion injecting program (not illustrating) to inject as argon (Ar) ion or oxygen (O) ion in stressor layers 118, its operation opportunity is after stressor layers 118 forms, and after injecting, then implements in ion one between 350 ℃～700 ℃ tempering program finishing, to increase the compression stress of stressor layers 118, by this and appropriateness is adjusted the integrated stress in the channel region 114.
Moreover the present invention also provides the structure of another kind of cmos component, shown in Fig. 2 F.In this structure, gate electrode 210 is arranged in the active area AA that defined by two shallow trench barrier assembly STI ' in the substrate 200, and source/drain S/D is located in gate electrode 210 substrate on two sides 200 and is attached at contiguous shallow trench barrier assembly STI '.Wherein, in shallow trench barrier assembly STI ', be provided with first stressor layers 205 of compliance.
In addition, the material of gate electrode 210 can be polysilicon, metal, SiGe or germanic polysilicon, and at gate electrode 210 and substrate 200 gate dielectric 208 is set, and its material can be silica.
Be disposed to stress buffer lining 214 compliances gate electrode 210 both sides and partly extend to substrate 200 surfaces.The THICKNESS CONTROL of stress buffer lining 214 is below 500 dusts, and its material can be silica.
Then, second stressor layers 224 is located on gate electrode 210, stress buffer lining 214 and the source/drain S/D, and contact with stress buffer lining 214 with gate electrode 210, by the influence of second stressor layers 224 that is arranged at first stressor layers 205 in the shallow trench barrier assembly STI ' and is arranged at the gate electrode surface to improve channel region 220 stress in the gate electrode 210 below substrates 200.Wherein, the material of first stressor layers 205 and second stressor layers 224 can be the laminated of silicon nitride (SiN), silicon oxynitride (SiON) or silicon nitride (SiN) and silicon oxynitride (SiON).
If when these second stressor layers, 224 tool tensile stresses and first stressor layers, 205 tool tensile stresses, be covered in the gate electrode 210 of second stressor layers, 224 belows and transistor that source/drain S/D constitutes and then be PMOS transistor or nmos pass transistor.
If these second stressor layers, 224 tool compression stresses and first stressor layers, 205 tools stretch or during compression stress, be covered in the gate electrode 210 of second stressor layers, 224 belows and transistor that source/drain S/D constitutes and then be the PMOS transistor.
In addition, between second stressor layers 224 and source/drain S/D, a metal silicide layer 222 can be set, use the sheet resistor that reduces source/drain S/D, it also can show suitable compression stress and promote the transistorized usefulness of PMOS.Usually, between second stressor layers 224 and gate electrode 210, the metal silicide layer 222 of identical material can be set also.
In addition, also can adopt ion injecting program (not illustrating) to inject as argon (Ar) ion or oxygen (O) ion in first stressor layers 205 and second stressor layers 224, its operation opportunity is after described stressor layers forms, and after injecting, then implements in ion one between 350 ℃～700 ℃ tempering program in finishing, to increase the compression stress of these stressor layers, by this and appropriateness is adjusted the integrated stress in the channel region 220.
Manufacture method:
First embodiment:
Figure 1A to Fig. 1 E is the schematic diagram that illustrates the manufacture method of a kind of cmos component of the present invention.
At first please refer to Figure 1A, a substrate 100 is provided, substrate 100 has active area AA.Wherein this active area AA is by forming the barrier assembly structure in substrate 100, shallow trench barrier assembly STI for example, and define.
Then, form transistor for active area, this transistor can be PMOS transistor and nmos pass transistor.As shown in the figure, form a gate dielectric 102 and gate electrode 104 in substrate 100, wherein the material of gate dielectric 102 can be silica, and the material of gate electrode 104 can be polysilicon, metal, SiGe or germanic polysilicon.The formation method of gate dielectric 102 and gate electrode 104 wherein, for example be in substrate 100, to deposit one dielectric layer and conductive layer in regular turn, and on conductive layer, form a patterning cover curtain layer (not illustrating), afterwards, with the patterning cover curtain layer is the cover curtain, in regular turn conductive layer and dielectric layer are carried out anisotropic etching,, again the patterning cover curtain layer is removed to form gate dielectric 102 and gate electrode 104 as shown in the figure.
Afterwards, the active area AA in gate electrode 104 substrate on two sides 100 forms shallow doped region 106, and its formation method is with ion implantation admixture to be injected not by the substrate 100 of gate electrode 104 and shallow trench barrier assembly STI covering.
Then please refer to Figure 1B, compliance ground form a stress buffer lining 110 in gate electrode 104 both sides and part extend to substrate 100 surfaces.The thickness of above-mentioned stress buffer lining 110 is less than 500 dusts, and its material can be silica.Stress buffer lining 110 is except in order to the effect as stress buffer, also can be in order to the sidewall of grill-protected utmost point electrode 104 and near the zone of channel region 114.Afterwards, on gate electrode 104 both sides stress buffer linings 110, form a clearance wall 108.The material of above-mentioned clearance wall 108 can be the laminated of silicon nitride or silica/silicon nitride.Wherein, the formation method of stress buffer lining 110 and clearance wall 108, for example be in regular turn on the surface that substrate 100, gate electrode 104 and gate dielectric 102 expose compliance form skim insulating barrier and another thicker insulating barrier; Then, utilize anisotropic etching, to form a clearance wall 108 and stress buffer lining 110.
Then, do not formed heavily doped region 112 by the active area AA in the substrate 100 of gate electrode 104 and clearance wall 108 coverings in gate electrode 104 both sides, its formation method is admixture to be injected the substrate 100 that is not covered by gate electrode 104, clearance wall 108 and shallow trench barrier assembly STI with ion implantation.Wherein shallow doped region 106 and heavily doped region 112 are source/drain regions S/D of transistor formed.
Then please refer to Fig. 1 C, utilize wet etching or dry ecthing to remove clearance wall 108, to expose stress buffer lining 110.
Wherein before removing clearance wall 108, comprise that more carrying out one aims at silicide process automatically, forms a metal silicide layer 116 with the surface at source/drain S/D; Or after removing clearance wall 108, carry out one and aim at silicide process automatically, form a metal silicide layer 116 with surface, shown in Fig. 1 C at source/drain S/D.In above-mentioned automatic aligning silicide process, if the material of gate electrode 104 is polysilicon, SiGe or germanic polysilicon, then its surface also can form metal silicide layer 116, as shown in the figure.
Then please refer to Fig. 1 D, after removing clearance wall 108 and finishing automatic aligning silicide process, on gate electrode 104, stress buffer lining 110 and source/drain S/D, cover a stressor layers 118, and contact with stress buffer lining 110 with gate electrode 104, use the stress that improves the channel region 114 in the gate electrode 104 below substrates 100.
Above-mentioned stressor layers 118 can be compressive stress layers or tension stress layer, its material can be the laminated of silicon nitride (SiN), silicon oxynitride (SiON) or silicon nitride (SiN) and silicon oxynitride (SiON), its thickness is about between 300～700 dusts (), and its formation method can be plasma enhanced chemical vapor deposition method (PECVD), rapid hot technics chemical vapour deposition technique (RTCVD), atomic level chemical vapour deposition technique (ALCVD), Low Pressure Chemical Vapor Deposition (LPCVD).
When stressor layers 118 when using the laminated tension stress layer of silicon nitride (SiN)/silicon oxynitride (SiON), the tensile stress that is positioned at the upper strata preferably is greater than lower floor.At this moment, the material that is positioned at laminated upper strata is preferably silicon oxynitride or the higher silicon nitride layer (silicon-rich nitride) of a silicon content, and the material that is positioned at laminated lower floor then is preferably silicon nitride or the higher silicon nitride layer (nitrogen-rich nitride) of nitrogen content.
Condition by control formation, can adjust the stress intensity of formed rete, according to research, the factor of may command stress has temperature, pressure or process gas ratio, if plasma-deposited method, then the factor of may command stress also comprises plasma electric power (plasma power).
To form material be silicon nitride and be that the stressor layers 118 of compression stress is an example with the plasma enhanced chemical vapor deposition method, and roughly between 300 ℃ and 500 ℃, required pressure is roughly between 1.33 * 10 for required temperature
2Pascal (Pa) (1.0 Bristols (torr)) and 2.0 * 10
2Between the Pa (1.5 Bristol), roughly between between 1000 watts (W) and 2000 watts, its process gas can be NH to required plasma electric power
3: SiH
4, ratio is roughly 4～10.
To form material be silicon nitride and be that the stressor layers 118 of tensile stress is an example with the rapid hot technics chemical vapour deposition technique, and roughly between 300 ℃ and 800 ℃, required pressure is roughly between 2.0 * 10 for required temperature
4Pa (150 Bristol) and 4.0 * 10
4Between the Pa (300 Bristol), its process gas can be NH
3: SiH
4, ratio is roughly 50～400; Perhaps its process gas can be dichlorosilane (dichlorosilane, SiH
2Cl
2, be called for short DCS): NH
3, ratio is roughly 0.1～1.
To form material be silicon nitride and be that the stressor layers 118 of compression stress is an example with Low Pressure Chemical Vapor Deposition, and roughly between 400 ℃ and 750 ℃, required pressure is roughly between 13.3Pa (0.1 Bristol (torr)) and 6.7 * 10 for required temperature
3Between the Pa (50 Bristol), its process gas can be dichlorosilane and NH
3, ratio is roughly 1～300.
If stressor layers 118 tool tensile stresses cover the gate electrode 104 of stressor layers 118 belows and the transistor of source/drain S/D formation and can be PMOS transistor and nmos pass transistor.In the case, the structure that does not remove clearance wall with tradition is compared, and the compression stress of the channel region 114 of cmos component of the present invention can reduce about 93～128MPa, improves electronics and the hole carrier mobility at channel region by this.
If stressor layers 118 tool compression stresses, covering the gate electrode 104 of stressor layers 118 belows and the transistor of source/drain S/D formation is the PMOS transistor.In the case, the structure that does not remove clearance wall with tradition is compared, and the compression stress of the channel region 114 of cmos component of the present invention can increase about 93～128MPa, improves the mobility of hole carrier at channel region by this.
In addition, also can adopt ion injecting program (not illustrating) to inject as argon (Ar) ion or oxygen (O) ion in stressor layers 118, its operation opportunity is after stressor layers 118 forms, and after injecting, then implements in ion one between 350 ℃～700 ℃ tempering program in finishing, to increase the compression stress of stressor layers 118, by this and appropriateness is adjusted the integrated stress in the channel region 114.
In addition, above-mentioned stressor layers 118 also can be as the etching stopping layer of follow-up contact hole technology.
Then carrying out follow-up technology, for example is interconnect technology.Shown in Fig. 1 E, on stressor layers 118, form inner layer dielectric layer 120, its material for example is silica, boron-phosphorosilicate glass (BPSG) or other similar this character, and at this inner layer dielectric layer 120 after planarization, by lithography technology, in inner layer dielectric layer 120 and stressor layers 118, form contact window 122.In the etching step of contact hole, above-mentioned stressor layers 118 is as etching stopping layer, wait to be etched to the stressor layers of exposing in the contact window 122 118 after, change etching condition again, remove the stressor layers 118 in the contact window 122, treat online assembly district until exposing.
Second embodiment:
Fig. 2 A to Fig. 2 G has illustrated the schematic diagram of manufacture method of the cmos component of another embodiment of the present invention.
At first please refer to Fig. 2 A, a substrate 200 is provided, this substrate 200 has active area AA, and this active area AA defines by form two grooves 202 in substrate 200.Then in groove 202, form the surface of a lining 204 respectively with smoothing groove 202.Lining 204 for example is by the formed silicon oxide layer of thermal oxidation method.Then groove 202 in, reach and conformably form first stressor layers 205 in the substrate 200 and be covered on the lining 204 in the groove 202.At this, first stressor layers 205 can be with reference to the manufacture method of the stressor layers 118 among aforementioned first embodiment and is formed.Deposit an insulating material 206 in substrate 200 and insert in the groove 202 then comprehensively.
Then please refer to Fig. 2 B, the insulating material 206 that will be higher than substrate 200 surfaces by the execution as the planarisation step (not shown) of cmp program removes, and then stays an insulating barrier 206a in groove 202.Then by part first stressor layers of execution to remove substrate surface in the active area AA of an etching step (not shown), at last in groove, stay one first stressor layers 205 that conforms to flute surfaces, and in groove 202, then formed and define the shallow trench barrier assembly STI ' that different active areas are used.
Please refer to Fig. 2 C, then form transistor in active area AA, this transistor can be PMOS transistor or nmos pass transistor.As shown in the figure, form a gate dielectric 208 and gate electrode 210 in substrate 200, wherein the material of gate dielectric 208 can be silica, and the material of gate electrode 210 can be polysilicon, metal, SiGe or germanic polysilicon.The formation method of gate dielectric 208 and gate electrode 210 wherein, for example can be in substrate 200, to deposit one dielectric layer and conductive layer in regular turn, and on conductive layer, form a patterning cover curtain layer (not illustrating), afterwards, with the patterning cover curtain layer is the cover curtain, in regular turn conductive layer and dielectric layer are carried out anisotropic etching,, again the patterning cover curtain layer is removed to form gate dielectric 208 and gate electrode 210 as shown in the figure.
Afterwards, the active area AA in gate electrode 210 substrate on two sides 200 forms shallow doped region 212, and its formation method is with ion implantation admixture to be injected not by the substrate 200 of gate electrode 210 and shallow trench barrier assembly STI ' covering.
Then please refer to Fig. 2 D, compliance ground form a stress buffer lining 214 in gate electrode 210 both sides and part extend to substrate 200 surfaces.The thickness of above-mentioned stress buffer lining 214 is less than 500 dusts, and its material can be silica.Stress buffer lining 214 is except in order to the effect as stress buffer, also can be in order to the sidewall of grill-protected utmost point electrode 210 and near the zone of channel region 220.Afterwards, on gate electrode 210 both sides stress buffer linings 214, form a clearance wall 216.The material of above-mentioned clearance wall 216 can be the laminated of silicon nitride or silica/silicon nitride.Wherein, the formation method of stress buffer lining 214 and clearance wall 216, for example can be in regular turn on the surface that substrate 200, gate electrode 210 and gate dielectric 208 expose compliance form skim insulating barrier and another thicker insulating barrier; Then, utilize anisotropic etching, to form a clearance wall 216 and stress buffer lining 214.
Then, do not formed heavily doped region 218 by the active area AA in the substrate 200 of gate electrode 210 and clearance wall 216 coverings in gate electrode 210 both sides, its formation method is admixture to be injected the substrate 200 that is not covered by gate electrode 210, clearance wall 216 and shallow trench barrier assembly STI ' with ion implantation.The source/drain regions S/D of wherein shallow doped region 212 and heavily doped region 218 transistor formeds.
Then please refer to Fig. 2 E, utilize wet etching or dry ecthing to remove clearance wall 216, to expose stress buffer lining 214.
Wherein before removing clearance wall 216, can comprise that more carrying out one aims at silicide process automatically, forms a metal silicide layer 222 with the surface in source/drain S/D; Or after removing clearance wall 216, carry out one and aim at silicide process automatically, form a metal silicide layer 222 with surface, shown in Fig. 2 E in source/drain S/D.In above-mentioned automatic aligning silicide process, if the material of gate electrode 210 is polysilicon, SiGe or germanic polysilicon, then its surface also can form metal silicide layer 222, as shown in the figure.At this, the metal silicide layer 222 that is formed at the surface of source/drain S/D also can show a compression stress for channel region 220.
Then please refer to Fig. 2 F, after removing clearance wall 216 and finishing automatic aligning silicide process, on gate electrode 210, stress buffer lining 214 and source/drain S/D, cover one second stressor layers 224, and contact with stress buffer lining 214 with gate electrode 210, use the stress that improves in the gate electrode 210 below substrates 200 channel region 220.
In addition, also can adopt ion injecting program (not illustrating) to inject as argon (Ar) ion or oxygen (O) ion in first stressor layers 205 and second stressor layers 224, its operation opportunity is after described stressor layers forms, and after injecting, then implements in ion one between 350 ℃～700 ℃ tempering program in finishing, to increase the compression stress of first and second stressor layers, by this and appropriateness is adjusted the integrated stress in the channel region 220.
In addition, the second above-mentioned stressor layers 224 also can be as the etching stopping layer of follow-up contact hole technology.
Then carrying out follow-up technology, for example is interconnect technology.Shown in Fig. 2 G, on second stressor layers 224, form inner layer dielectric layer 226, its material for example is the material of silica, boron-phosphorosilicate glass (BPSG) or other similar this character, and in this inner layer dielectric layer 226 after planarization, by lithography technology, in the inner layer dielectric layer 226 and second stressor layers 224, form contact window 228.In the etching step of contact hole, the second above-mentioned stressor layers 224 is as etching stopping layer, wait to be etched to second stressor layers of exposing in the contact window 228 224 after, change etching condition again, remove second stressor layers 224 in the contact window 228, treat online assembly district until exposing.
Above-mentioned first stressor layers 205 and second stressor layers 224 can be compressive stress layers or tension stress layer, its material can be silicon nitride (SiN), silicon oxynitride (SiON), or silicon nitride (SiN) and silicon oxynitride (SiON) is laminated, its thickness is about respectively between 20～300 dusts () and 300～700 dusts (), and its formation method can be plasma enhanced chemical vapor deposition method (PECVD), rapid hot technics chemical vapour deposition technique (RTCVD), rapid hot technics chemical vapour deposition technique (RTCVD), atomic level chemical vapour deposition technique (ALCVD), Low Pressure Chemical Vapor Deposition (LPCVD).When stressor layers (first stressor layers 205 or second stressor layers 224) when using the laminated tension stress layer of silicon nitride (SiN)/silicon oxynitride (SiON), the tensile stress that is positioned at the upper strata preferably is greater than lower floor.At this moment, the material that is positioned at laminated lower floor is preferably silicon oxynitride or the higher silicon nitride layer (silicon-rich nitride) of silicon content, and the material that is positioned at laminated upper strata then is preferably silicon nitride or the higher silicon nitride layer (nitrogen-rich nitride) of nitrogen content.
Condition by control formation, can adjust the stress intensity of formed rete, according to research, the factor of may command stress has temperature, pressure or process gas ratio, if plasma-deposited method, then the factor of may command stress also comprises plasma electric power (plasma power).
To form material be silicon nitride and be that second stressor layers 224 of compression stress is an example with the plasma enhanced chemical vapor deposition method, and roughly between 300 ℃ and 500 ℃, required pressure is roughly between 1.33 * 10 for required temperature
2Pa (1.0 Bristols (torr)) and 2.0 * 10
2Between the Pa (1.5 Bristol), roughly between between 1000 watts (W) and 2000 watts, its process gas can be NH to required plasma electric power
3: SiH
4, ratio is roughly 4～10.
To form material be silicon nitride and be that second stressor layers 224 of tensile stress is an example with the rapid hot technics chemical vapour deposition technique, and roughly between 300 ℃ and 800 ℃, required pressure is roughly between 2.0 * 10 for required temperature
4Pa (150 Bristol) and 4.0 * 10
4Between the Pa (300 Bristol), its process gas can be NH
3: SiH
4, ratio is roughly 50～400; Perhaps its process gas can be dichlorosilane (dichlorosilane, SiH2Cl2 are called for short DCS): NH
3, ratio is roughly 0.1～1.
To form material be silicon nitride and be that second stressor layers 224 of compression stress is an example with Low Pressure Chemical Vapor Deposition, and roughly between 400 ℃ and 750 ℃, required pressure is roughly between 13.3Pa (0.1 Bristol (torr)) and 6.7 * 10 for required temperature
3Between the Pa (50 Bristol), its process gas can be DCS: NH
3, ratio is roughly 1～300.
If when second stressor layers, 224 tool tensile stresses and first stressor layers, 205 tool tensile stresses, be covered in the gate electrode 210 of second stressor layers, 224 belows and transistor that source/drain S/D constitutes and can be PMOS transistor and nmos pass transistor.In the case, the structure that does not remove clearance wall with tradition is compared, and the compression stress of the channel region 220 of cmos component of the present invention can reduce about 100～900MPa, improves electronics and hole carrier by this in the mobility of channel region.
If second stressor layers, 224 tool compression stresses and the first stressor layers 206a tool stretch or during compression stress, being covered in the gate electrode 210 of second stressor layers, 224 belows and transistor that source/drain S/D constitutes is the PMOS transistor.In the case, the structure that does not remove clearance wall with tradition is compared, and the compression stress of the channel region 220 of cmos component of the present invention can increase about 100～900MPa, improves the mobility of hole carrier in channel region by this.
In sum, utilize structure provided by the present invention and method, can use the transistor that forms characteristic with mechanical stress concentration at channel region with high speed operation and low-yield consume.
In making transistorized process, before the deposition stressor layers,, can make the stress of the stressor layers of deposition concentrate on transistorized channel region effectively by increasing the process that removes clearance wall together.Therefore, this method is applicable to any technology that improves transistorized usefulness by the local mechanical Stress Control.In addition, with regard to the manufacturing of above-mentioned stressor layers, can make the stressor layers that meets its demand respectively according to the different demand of P raceway groove and N raceway groove with compression stress and tensile stress.
Therefore, the formation method of stressor layers is not limited to above-mentioned method, and other can improve the technology of transistorized usefulness all applicable to the present invention by the local mechanical Stress Control.
Though the present invention discloses as above with preferred embodiment; right its is not in order to restriction the present invention, any people who has the knack of this skill, without departing from the spirit and scope of the present invention; change and retouching when doing, so protection scope of the present invention is when being as the criterion with the scope that claim was defined.
Claims (47)
1. cmos component is characterized in that comprising:
One substrate;
One gate electrode is located in this substrate;
Source is located in this substrate of these gate electrode both sides;
One stress buffer lining is configured in to compliance these gate electrode both sides and part extends to this substrate surface, and wherein the thickness of this stress buffer lining is less than 500 dusts; And
One stressor layers is located on this gate electrode, this stress buffer lining and this source/drain, and contacts with this stress buffer lining, uses the stress that improves the channel region in this gate electrode this substrate of below.
2. cmos component as claimed in claim 1 is characterized in that wherein the material of this stress buffer lining is a silica.
3. cmos component as claimed in claim 1 is characterized in that wherein the material of this stressor layers is the laminated of silicon nitride, silicon oxynitride or silicon nitride and silicon oxynitride.
4. cmos component as claimed in claim 1 is characterized in that wherein this stressor layers tool tensile stress, and being covered in this gate electrode of this stressor layers below and the transistor of this source/drain formation is PMOS transistor and nmos pass transistor.
5. cmos component as claimed in claim 1 is characterized in that wherein this stressor layers tool compression stress, and being covered in this gate electrode of this stressor layers below and the transistor of this source/drain formation is the PMOS transistor.
6. cmos component as claimed in claim 1 is characterized in that wherein more comprising a metal silicide layer, is arranged between this stressor layers and this source/drain, and between this stressor layers and this gate electrode.
7. the manufacture method of a cmos component is characterized in that comprising:
One substrate is provided, and this substrate has an active area;
Form a gate electrode at this active area;
This active area in this substrate of these gate electrode both sides forms a shallow doped region;
Compliance ground form a stress buffer lining in these gate electrode both sides and part extend to this substrate surface;
On this stress buffer lining of these gate electrode both sides, form a clearance wall;
Do not formed a heavily doped region by this active area in this substrate of this gate electrode and the covering of this clearance wall in these gate electrode both sides, wherein this shallow doped region and this heavily doped region are to constitute source;
Remove this clearance wall; And
On this gate electrode, this stress buffer lining and this source/drain, cover a stressor layers, and contact, use the stress that improves the channel region in this gate electrode this substrate of below with this stress buffer lining.
8. the manufacture method of cmos component as claimed in claim 7, the thickness that it is characterized in that this stress buffer lining wherein is less than 500 dusts.
9. the manufacture method of cmos component as claimed in claim 7 is characterized in that wherein the material of this stress buffer lining is a silica.
10. the manufacture method of cmos component as claimed in claim 7 is characterized in that wherein the material of this stressor layers is to select in the laminated group of forming of free silicon nitride, silicon oxynitride and silicon nitride and silicon oxynitride.
11. the manufacture method of cmos component as claimed in claim 10 is characterized in that wherein the formation method of this stressor layers is plasma enhanced chemical vapor deposition method, rapid hot technics chemical vapour deposition technique, atomic level chemical vapour deposition technique or Low Pressure Chemical Vapor Deposition.
12. the manufacture method of cmos component as claimed in claim 7 is characterized in that wherein this stressor layers tool tensile stress, covering this gate electrode of this stressor layers below and the transistor of this source/drain formation is PMOS transistor and nmos pass transistor.
13. the manufacture method of cmos component as claimed in claim 7 is characterized in that wherein this stressor layers tool compression stress, covering this gate electrode of this stressor layers below and the transistor of this source/drain formation is the PMOS transistor.
14. the manufacture method of cmos component as claimed in claim 7 is characterized in that wherein the material of this clearance wall is a silicon nitride, and the method that removes this clearance wall is wet etching or dry ecthing.
15. the manufacture method of cmos component as claimed in claim 7 is characterized in that wherein more may further comprise the steps:
On this stressor layers, form an inner layer dielectric layer;
With this stressor layers is etching stopping layer, etches a contact window in this inner layer dielectric layer; And
Remove this stressor layers in this contact window.
16. a cmos component is characterized in that comprising:
One substrate is provided with at least one barrier assembly, and comprises one first stressor layers in this barrier assembly;
One gate electrode is located in this substrate;
Source is located in this substrates of this gate electrode both sides and contacts described barrier assembly;
One stress buffer lining is configured in to compliance these gate electrode both sides and part extends to this substrate surface; And
One second stressor layers is located on this gate electrode, this stress buffer lining and this source/drain, and contacts with this stress buffer lining, by second stressor layers and first stressor layers to improve the stress of the channel region in this gate electrode this substrate of below.
17. cmos component as claimed in claim 16, the thickness that it is characterized in that this stress buffer lining wherein is less than 500 dusts.
18. cmos component as claimed in claim 16 is characterized in that wherein the material of this stress buffer lining is a silica.
19. cmos component as claimed in claim 16 is characterized in that wherein the material of this first stressor layers is the laminated of silicon nitride, silicon oxynitride or silicon nitride and silicon oxynitride.
20. cmos component as claimed in claim 16 is characterized in that wherein the material of this second stressor layers is the laminated of silicon nitride, silicon oxynitride or silicon nitride and silicon oxynitride.
21. cmos component as claimed in claim 20 it is characterized in that wherein this silicon nitride and the laminated of silicon oxynitride are a tension stress layer, and this laminated upper strata has higher tensile stress than its lower floor.
22. cmos component as claimed in claim 20 is characterized in that silicon nitride or silicon oxynitride that this lower floor's material wherein is a Silicon-rich, and the silicon nitride that this upper strata material is silicon nitride or rich nitrogen.
23. cmos component as claimed in claim 16, it is characterized in that wherein this second stressor layers tool tensile stress and this first stressor layers tool tensile stress, being covered in this gate electrode of second stressor layers below and the transistor of this source/drain formation is PMOS transistor and nmos pass transistor.
24. cmos component as claimed in claim 16, it is characterized in that wherein this second stressor layers tool compression stress and stretching of this first stressor layers tool or compression stress, being covered in this gate electrode of this second stressor layers below and the transistor of this source/drain formation is the PMOS transistor.
25. cmos component as claimed in claim 16 is characterized in that wherein more comprising a metal silicide layer, is arranged between this second stressor layers and this source/drain, and between this second stressor layers and this gate electrode.
26. cmos component as claimed in claim 24, it is characterized in that wherein more comprising a metal silicide layer, be arranged between this second stressor layers and this source/drain, and between this second stressor layers and this gate electrode, provide this PMOS transistor one compression stress.
27. the manufacture method of a cmos component is characterized in that comprising:
One substrate is provided;
In this substrate, form at least one barrier assembly to define an active area, wherein contain one first stressor layers in this barrier assembly;
Form a gate electrode at this active area;
Form a shallow doped region in this gate electrode substrate on two sides in this active area and contact this barrier assembly;
Compliance ground form a stress buffer lining in these gate electrode both sides and part extend to this substrate surface;
On this stress buffer lining of these gate electrode both sides, form a clearance wall;
Do not formed a heavily doped region by this active area in this substrate of this gate electrode and the covering of this clearance wall in these gate electrode both sides, wherein this shallow doped region and this heavily doped region constitute source;
Remove this clearance wall; And
On this gate electrode, this stress buffer lining and this source/drain, cover one second stressor layers, and contact with this stress buffer lining, so by this second stressor layers and this first stressor layers to improve the stress of the channel region in this gate electrode this substrate of below.
28. the manufacture method of cmos component as claimed in claim 27 is characterized in that wherein this barrier assembly is the shallow trench barrier assembly, and this first stressor layers compliance be formed in this shallow trench barrier assembly.
29. the manufacture method of cmos component as claimed in claim 27, the thickness that it is characterized in that this stress buffer lining wherein is less than 500 dusts.
30. the manufacture method of cmos component as claimed in claim 27 is characterized in that wherein the material of this stress buffer lining is a silica.
31. the manufacture method of cmos component as claimed in claim 27 is characterized in that wherein the material of this first stressor layers is to select in the laminated group of forming of free silicon nitride, silicon oxynitride and silicon nitride and silicon oxynitride.
32. the manufacture method of cmos component as claimed in claim 27 is characterized in that wherein the material of this second stressor layers is to select in the laminated group of forming of free silicon nitride, silicon oxynitride and silicon nitride and silicon oxynitride.
33. the manufacture method of cmos component as claimed in claim 27 is characterized in that wherein the formation method of this first stressor layers is plasma enhanced chemical vapor deposition method, rapid hot technics chemical vapour deposition technique, atomic level chemical vapour deposition technique or Low Pressure Chemical Vapor Deposition.
34. the manufacture method of cmos component as claimed in claim 27 is characterized in that wherein the formation method of this second stressor layers is plasma enhanced chemical vapor deposition method, rapid hot technics chemical vapour deposition technique, atomic level chemical vapour deposition technique or Low Pressure Chemical Vapor Deposition.
35. the manufacture method of cmos component as claimed in claim 27, it is characterized in that wherein this second stressor layers tool tensile stress and this first stressor layers tool tensile stress, covering this gate electrode of this second stressor layers below and transistor that this source/drain constitutes is PMOS transistor and nmos pass transistor.
36. the manufacture method of the described cmos component of claim 27, it is characterized in that wherein this second stressor layers tool compression stress and this first stressor layers tool stretches or compression stress, covering this gate electrode of this second stressor layers below and transistor that this source/drain constitutes is the PMOS transistor.
37. the manufacture method of cmos component as claimed in claim 27 is characterized in that the material of this gate electrode wherein is to select in the group that free polysilicon, metal, SiGe and germanic polysilicon form.
38. the manufacture method of cmos component as claimed in claim 27 is characterized in that wherein the material of this clearance wall is a silicon nitride.
39. the manufacture method of cmos component as claimed in claim 27, the method that it is characterized in that wherein removing this clearance wall is a wet etching.
40. the manufacture method of cmos component as claimed in claim 27, the method that it is characterized in that wherein removing this clearance wall is dry ecthing.
41. the manufacture method of cmos component as claimed in claim 27 is characterized in that wherein before removing this clearance wall, comprised that more carrying out one aims at silicide process automatically, forms a metal silicide with the surface at this source/drain.
42. the manufacture method of cmos component as claimed in claim 27 is characterized in that wherein after removing this clearance wall, comprises that more carrying out one aims at silicide process automatically, forms a metal silicide with the surface at this source/drain.
43. the manufacture method of cmos component as claimed in claim 36, it is characterized in that wherein before removing this clearance wall, comprise that more carrying out one aims at silicide process automatically, form a metal silicide with the surface at this source/drain, wherein this metal silicide provides this PMOS transistor one compression stress.
44. the manufacture method of cmos component as claimed in claim 36, it is characterized in that wherein after removing this clearance wall, comprise that more carrying out one aims at silicide process automatically, form a metal silicide with the surface at this source/drain, wherein this metal silicide provides this PMOS transistor one compression stress.
45. the manufacture method of cmos component as claimed in claim 27 is characterized in that wherein more may further comprise the steps:
On this stressor layers, form an inner layer dielectric layer;
With this stressor layers is etching stopping layer, etches a contact window in this inner layer dielectric layer; And
Remove this stressor layers in this contact window.
46. the manufacture method of cmos component as claimed in claim 27 is characterized in that the ion injecting program that comprises more that wherein this second stressor layers is implemented, to adjust the integrated stress of this channel region.
47. the manufacture method of cmos component as claimed in claim 46 is characterized in that wherein the admixture of this ion injecting program employing is argon ion or oxonium ion.
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| US7195969B2 (en) * | 2004-12-31 | 2007-03-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained channel CMOS device with fully silicided gate electrode |
| CN100437973C (en) * | 2005-12-09 | 2008-11-26 | 联华电子股份有限公司 | Contact window forming method and semiconductor element |
| JP5092340B2 (en) * | 2006-10-12 | 2012-12-05 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
| US8536619B2 (en) | 2007-02-05 | 2013-09-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained MOS device and methods for forming the same |
| CN102122638B (en) * | 2010-01-08 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for forming stress film of CMOS (Complementary Metal-Oxide-Semiconductor Transistor) device |
| CN102446767B (en) * | 2010-10-12 | 2013-09-04 | 中芯国际集成电路制造(北京)有限公司 | Manufacturing method of NMOS (N-channel metal oxide semiconductor) transistor |
| CN103035524B (en) * | 2011-09-29 | 2015-08-05 | 中国科学院微电子研究所 | Semiconductor device and manufacture method thereof |
| US8652893B2 (en) | 2011-09-29 | 2014-02-18 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6310367B1 (en) * | 1999-02-22 | 2001-10-30 | Kabushiki Kaisha Toshiba | MOS transistor having a tensile-strained SI layer and a compressive-strained SI-GE layer |
| US20030040158A1 (en) * | 2001-08-21 | 2003-02-27 | Nec Corporation | Semiconductor device and method of fabricating the same |
| US6573172B1 (en) * | 2002-09-16 | 2003-06-03 | Advanced Micro Devices, Inc. | Methods for improving carrier mobility of PMOS and NMOS devices |
| CN2731717Y (en) * | 2003-03-31 | 2005-10-05 | 台湾积体电路制造股份有限公司 | CMOS assembly |
-
2004
- 2004-03-30 CN CNB2004100296914A patent/CN1301556C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6310367B1 (en) * | 1999-02-22 | 2001-10-30 | Kabushiki Kaisha Toshiba | MOS transistor having a tensile-strained SI layer and a compressive-strained SI-GE layer |
| US20030040158A1 (en) * | 2001-08-21 | 2003-02-27 | Nec Corporation | Semiconductor device and method of fabricating the same |
| US6573172B1 (en) * | 2002-09-16 | 2003-06-03 | Advanced Micro Devices, Inc. | Methods for improving carrier mobility of PMOS and NMOS devices |
| CN2731717Y (en) * | 2003-03-31 | 2005-10-05 | 台湾积体电路制造股份有限公司 | CMOS assembly |
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