CN1296991C - 体半导体的鳍状fet器件及其形成方法 - Google Patents

体半导体的鳍状fet器件及其形成方法 Download PDF

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CN1296991C
CN1296991C CNB038111691A CN03811169A CN1296991C CN 1296991 C CN1296991 C CN 1296991C CN B038111691 A CNB038111691 A CN B038111691A CN 03811169 A CN03811169 A CN 03811169A CN 1296991 C CN1296991 C CN 1296991C
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戴维·M.·弗雷德
爱德华·J.·诺瓦克
贝思·安·雷尼
德温得拉·K.·萨达纳
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GlobalFoundries Inc
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Abstract

本发明提供了一种从体半导体晶片(200)形成鳍(210)状场效应晶体管(FET)同时改善各晶片之间的器件一致性的器件结构和方法。具体地说，本发明提供了保证鳍高度一致的高度控制层(212)，诸如衬底(200)的一个受损部分或一个标志层。此外，本发明提供鳍(210)之间的隔离(214)，这还通过相对于鳍侧壁的氧化部分(216)选择性氧化衬底的一部分(212)，使鳍宽度得到优化和变窄。本发明的器件结构和方法因此具有可以用高效益的体晶片一致地制造鳍状场效应晶体管的优点。

Description

体半导体的鳍状FET器件及其形成方法
技术领域
本发明与半导体制造领域有关，具体地说，与制造鳍状场效应晶体管的方法有关。
背景技术
在生产半器件中降低成本和提高性能的竞争性需求驱使集成电路内的器件密度不断增大。为了增大器件密度，不断需要有新的技术来减小这些半导体器件的形体尺寸。
在诸如设计和制造场效应晶体管(FET)的CMOS技术中增大器件密度的要求特别强烈。FET包括CMOS的主要组件。缩放FET以在CMOS内达到较高器件密度会导致性能和/或可靠性的降低。
已经提出的有利于增大器件密度的一类FET是鳍状场效应晶体管(fin Field Effect Transistor)。在finFET内，晶体管主体形成自一个垂直结构，这种结构由于类似于鱼的背鳍，因此通常称为“鳍”状结构。在鳍的一个或多个侧面上形成finFET的栅极。FinFET具有若干优点，包括有较好的电流控制而不需要增大器件的尺寸。因此，FinFET有利于在保持可接受的性能的同时缩放CMOS的尺寸。
不幸的是，在设计和制造鳍状晶体管中出现一些困难。首先，在鳍状晶体管内一般需要对每个finFET器件进行电隔离。具体地说，不但各finFET器件之间需要相互隔离，还需要隔离各器件本身的源极与漏极，以保证源极与漏极去耦。因此，finFET通常用绝缘体上硅(SOI)晶片制造，以提供各个器件的鳍之间的隔离。具体地说，这些晶体管的鳍由在掩埋的绝缘层上的硅层形成，由于这些鳍下面是掩埋的绝缘层，因此每个鳍与其他鳍隔离。同样，各个finFET的源极与漏极由于掩埋的绝缘层而相互去耦。
虽然用SOI晶片可以提供所要求的finFET隔离，但并不是没有显著缺点的。用SOI晶片形成finFET的特别明显的缺点是SOI晶片比体硅片(bulk silicon wafer)成本高。例如，SOI晶片的成本通常可能是体硅片的2至3倍。这样高的SOI晶片成本，虽然对于有些应用是可以接受的，但在其他应用中是不可接受的。此外，使用SOI晶片不是与所有制造工艺兼容的，例如与通常所用的SiGe工艺就不兼容。
Hisamoto等人在“A fully Depleted Lean-channel Transistor(DELTA)-A novel vertical ultra thin SOI MOSFET”，InternationalElectron Devices Meeting 1989,Paper 34.5.1，pp.833-6中揭示了隔离体晶片上的器件的方法。这种方法要求在鳍上生成氮化物隔离层，使得鳍在下层衬底氧化以形成隔离区的过程中受到保护。因此，相对于鳍，有选择地使衬底氧化。这个工艺的缺点是氧化温度高达1100℃，而且不能在生成绝缘层的同时修整鳍的厚度。随着器件继续按比例缩小，它们的耐高温能力减小，这样，Hisamoto等人提出的工艺与FinFET要用的毫微级技术不可兼容。而且，不能修整鳍的厚度意味着这些器件的关键尺寸仅仅由光刻(lithography)决定。如下面要详细说明的那样，本发明的方法的特征是它提供了通过氧化修整鳍的能力，以使得能够以超过光刻所能达到的效果来优化鳍的厚度。
此外，Hisamoto的工艺没有提供控制鳍高度的方法。体晶片没有诸如由掩埋在SOI晶片内的氧化层提供的能终止蚀刻鳍的层。没有这个蚀刻终止层，蚀刻深度的不一致就会转化为鳍的高度的不一致。由于器件所传导的电流的量与鳍的高度成正比，因此尽量减小鳍高度的不一致是很重要的。
因此，有必要开发一种有利于用体硅形成finFET器件、同时又尽量减小器件的不一致和提供充分的器件隔离的改进的制造方法和结构。
发明内容
因此，本发明提供了一种可以克服现有技术的许多缺点的形成鳍状场效应晶体管(FET)的器件结构和方法。具体地说，这种器件结构和方法能用体半导体晶片形成finFET器件，同时改善了器件的一致性。
在第一方面，发明提供了一种在半导体衬底上形成一个finFET的方法，这种方法包括下列步骤：在半导体衬底上形成一个鳍；以及使衬底受到在隔离鳍的同时进一步限定鳍的宽度的工艺的处理。
本发明还提供了一种在半导体衬底(200)中形成一个鳍状场效应晶体管的方法，所述方法包括下列步骤：在半导体衬底(200)上形成(102，104，106，108)一个鳍(210)；损伤(110)与鳍(210)相邻的半导体衬底区域的至少一部分(212)；以及在半导体衬底上生长绝缘体，使得绝缘体在半导体衬底的受损部分(214)内形成得比在鳍侧壁(216)上厚。
在第二方面，本发明提供了一种在半导体衬底上形成finFET的方法，这种方法包括下列步骤：在半导体衬底上形成一个鳍，这个鳍包括一个鳍侧壁(fin sidewall)，鳍的形成暴露了与鳍相邻的半导体衬底区域；损伤与鳍相邻的半导体衬底区域的至少一部分；以及对半导体衬底进行氧化，使得氧化物在半导体衬底的受损部分内形成得比在鳍侧壁上厚。
从以下对如附图所例示的本发明的优选实施例的更为具体的说明中可以清楚地看到本发明的以上所述及其他的优点和特征。
附图说明
以下将结合附图说明本发明的一个优选的示范性实施例，在这些附图中同样的标记所标示的是同样的部分，其中：
图1为例示本发明所提出的制造方法的流程图；以及
图2-7分别为本发明的半导体结构的一个实施例在图1所示的制造方法期间的各个切剖侧视图。
具体实施方式
因此，本发明提供了一种可以克服现有技术的许多缺点的形成鳍状场效应晶体管(FET)的器件结构和方法。具体地说，这种器件结构和方法能从体半导体晶片形成finFET器件，同时改善了器件的一致性。这种方法有利于从体半导体晶片形成finFET器件，而且改善了对鳍高度的控制。此外，这种方法能从体半导体形成finFET，同时提供各个鳍之间和各个finFET的源区与漏区之间的隔离。最后，这种方法还可以提供对鳍宽度的优化。本发明的器件结构和方法因此具有可在体晶片上制造一致的finFET的优点。
本发明的一个实施例在形成鳍图案前使用了一种工艺，以提供改进的鳍高度。这种工艺可以包括将一种损伤衬底的重离子注入到所需深度，从而相对于未受损衬底的蚀刻率改变受损衬底的蚀刻率。这允许在形成鳍图案期间通过尽量减小蚀刻率不一致的影响来提供改进的高度控制。另一种工艺可以包括在所需深度注入或形成一个标志层。在鳍蚀刻期间，监视标志层的元素，以精确确定什么时候蚀刻到所希望的深度。这两种工艺控制技术因此改善了鳍高度的一致性，使得能够从体半导体晶片形成鳍，同时各晶片间鳍的不一致性最小。
本发明的第二方面是形成相邻鳍之间和各finFET的源区与漏区之间的隔离。此外，这种工艺优化了鳍本身的宽度。这种工艺首先有选择地损伤鳍之间的半导体晶片。这种有选择的损伤可以通过在各鳍之间注入适当的重离子或通过注入一种p型物质并经一个有选择的阳极反应来实现。这些方法损伤所暴露的接近鳍处的半导体晶片，但是通过鳍顶上有保护性的硬掩模层使对鳍本身的损伤最小化。然后，对晶片进行氧化。这导致在鳍的侧壁上和鳍之间的区域内形成氧化。晶片的受损区域氧化得比未受损区域快，因此导致鳍之间的氧化物比鳍本身上的厚。这种氧化率的差异使鳍之间得到充分的氧化物而没有使鳍过分变窄。
这种工艺在鳍之间产生充分的氧化，从而提供了鳍之间和鳍本身的源区与漏区之间的隔离。此外，在鳍上形成氧化物使鳍本身变窄。在从鳍的侧壁除去氧化物时，使鳍的宽度在原始宽度的基础上进一步得到优化，而在鳍之间剩下足以提供隔离的氧化物。因此，这种工艺隔离了鳍并同时优化了鳍的宽度。
因此，所提供的方法有利于从体硅形成finFET器件，同时增大了对鳍的高度和宽度的控制，也增大了对鳍的源区与漏区的隔离。
本发明可以很容易适应各种迄今为止主要是在SOI衬底上制造的finFET及其有关器件。例如，这些方法可用来形成如在美国专利No.6,252,284中所揭示的双栅极finFET。因此，本技术领域的人员可以理解，本发明并不局限于附图中所例示的具体结构或在这里所详细说明的具体步骤。还可以理解，本发明不局限于使用任何具体的掺杂物类型，只要为各个组成部分选择的掺杂物类型与器件的预定电作用一致。
现在来看图1，图中例示了按照本发明设计的形成finFET的典型方法100。这种制造方法100允许从体半导体晶片形成finFEET，同时具有改进的晶片间一致性和充分的器件隔离。因此，方法100具有可以用效益较高的制造工艺生产finFET的优点。下面将结合图2-7所示的一个晶片部分在加工期间的各个情况对方法100进行详细说明。
图1的第一个步骤101是提供一个适当的体半导体晶片。方法100的下一个步骤102是淀积一个适当的硬掩模阻挡层(hardmaskblocking layer)，然后再淀积一个适当的硬掩模盖顶层(hardmask caplayer)。硬掩模阻挡层和硬掩模盖顶层都可以含有任何适当的材料，具有任何适当的厚度。例如，硬掩模阻挡层可以包括40-100nm厚的二氧化硅，而硬掩模盖顶层可以包括5-50nm厚的氮化硅。如以下可看到的那样，硬掩模盖顶层和硬掩模阻挡层被用来使在下面的半导体衬底形成图案和在形成隔离期间保护鳍。
现在来看图2，图中例示了一个示范性的晶片部分200，它包括一个硬掩模阻挡层204和一个硬掩模盖顶层202。同样，晶片部分200可以包括任何适当的体半导体晶片，诸如硅<100>晶片之类。硬掩模阻挡层204和硬掩模盖顶层202也可以包括任何适当的硬掩模材料，诸如分别为二氧化硅和氮化硅之类。
再来看图1，下一个步骤104是加工硬掩模阻挡层和硬掩模盖顶层，以形成鳍的图案。这可以用任何适当的工艺进行，通常包括淀积适当的光刻胶(photoresist)和并对其形成图案。于是可以有选择地对经显像的光刻胶用反应离子蚀刻(RIE)使硬掩模阻挡层和硬掩模盖顶层形成图案。形成图案的硬掩模层于是用来在硅RIE期间使在下面的半导体衬底形成图案，限定将用来形成finFET器件的鳍。因而，形成图案的长度和宽度由对于具体应用所需的鳍的尺寸确定。
现在来看图3，图中例示了晶片部分200在硬掩模阻挡层204和硬掩模盖顶层202已经形成图案后的情况。
再回到图1，下一个步骤106是在半导体晶片内形成一个高度控制层。然后，下一个步骤108是利用高度控制层控制鳍高度来使半导体晶片形成鳍的图案。有若干不同类型的高度控制层可以采用。例如，这层可以包括将一种损伤衬底的重离子注入到所需深度，从而相对于未受损衬底的蚀刻率改变受损衬底的蚀刻率。这允许在形成鳍图案期间通过尽量减小蚀刻率不一致的影响来改善高度控制。在另一个备选方案中，高度控制层可以包括在所需深度形成一个标志层(markerlayer)。在形成鳍图案期间，对标志层的元素进行监视，以精确地检测什么时候达到了所希望的鳍高度。这两种技术因此提供了得到改善的鳍高度控制，使得可以从体半导体晶片可靠地形成鳍。
在高度控制层包括损伤衬底的离子注入时，可以用任何适当的充分损伤半导体衬底的暴露部分以相对于未受损衬底的蚀刻率改变受损衬底的蚀刻率的离子。例如，可用As离子注入来损伤半导体晶片。其他适当的离子包括锗、铯、锑或其他重离子。选择注入的能量，以使损伤能够达到所希望的鳍的深度。例如，为了形成800埃左右的鳍高度，可以用140keV、剂量为1×1016/cm2的As注入。利用适当的蚀刻，可以使受损部分蚀刻得比未受损部分快，并且采用定时的蚀刻更可能产生一致的蚀刻深度。也就是说，未受损部分蚀刻得比受损部分慢，而用定时蚀刻可以大大减少未受损区的过蚀刻。因此，这种离子注入改善了对所得到的鳍的高度的控制。
在高度控制层包括一个标志层时，在蚀刻加工期间检测到标志离子表明已经蚀刻到所希望的深度。标志层可以包括任何适当的物质，诸如氧、氢或锗。标志层可以通过将标志物质(诸如Ge)注入衬底形成。或者，可以通过在衬底上淀积上标志物质，并在所淀积的标志层上形成一个附加的半导体衬底层来形成所述标志层。于是可以从标志层顶上的层蚀刻出鳍。在蚀刻半导体衬底层的同时对标志物质进行监视，以限定鳍的高度。在检测到标志物质时停止蚀刻，因为存在标志物质表明已经蚀刻到所希望的深度。出现标志层物质有助于确定什么时候应该停止蚀刻加工，因此可以产生一致的蚀刻深度。例如，标志层可以是一个厚为800至1000埃、锗浓度为25％至50％的SiGe层。
这两种技术因此提供了改进的鳍高度控制，从而可以从体半导体晶片可靠地形成高度一致的鳍。在所有这些实施例中，将蚀刻的化学作用选择成与高度控制层的类型兼容并且对用来限定鳍图案的硬掩模盖顶层是有选择的。
现在来看图4，图中例示了晶片部分200在形成高度控制层和使半导体衬底形成鳍210的图案后的情况。同样，由于有了高度控制层，因此各晶片间的鳍高度的一致性得到了改善。
有时候希望此时除去盖顶层202。这可以用任何适当技术来实现，诸如对下层硬掩模和暴露的硅是可以选择的湿蚀刻或干蚀刻。因此，留下了在下面的硬掩模阻挡层204，用来在以后的加工中保护鳍。在其他情况下，盖顶层202可以留在原处，以在以后的加工期间进一步保护鳍。
下一个步骤110是损伤鳍之间的衬底。如可以看到的那样，损伤衬底意味着相对于鳍本身的氧化率提高鳍之间的衬底的氧化率。损伤衬底的一种方法是将适当的元素注入鳍之间的衬底。这种注入适当地与衬底表面垂直进行，因此阻挡的硬掩模层防止注入直接损伤鳍，但这可能会产生一些蔓延。可用任何适当的注入来损伤衬底，虽然通常是优先选择能很好损伤衬底从而提高衬底氧化率的重离子。因此，注入As(剂量大约在1×1016/cm2到1×1017/cm2之间，能量大约为40-60keV)是一种适当的选择。其他适当的注入物质包括铯、氧和锗。
有选择地损伤半导体衬底的另一种方法是通过对p型注入物有选择的阳极反应。在这种工艺中，将p型离子注入鳍之间的半导体衬底。p型注入物可以包括任何适当的物质，诸如硼之类。同样，硬掩模阻挡层防止p型注入直接损伤鳍。在p型注入后，将衬底退火。然后，使注入区受到诸如HF/酒精之类的的化学蚀刻剂的作用，出现阳极反应。这就损伤了注入区。具体地说，阳极反应使注入区成为多孔的。损伤量可以由p型注入的密度和能量、HF浓度和HF/酒精混合物及反应电流密度和时间控制。受损区同样具有提高了的氧化率，因此导致衬底与鳍之间氧化物厚度的差异。
现在来看图5，图中例示了晶片部分200在硬掩模盖顶层202除去后执行了损伤加工从而形成衬底的受损部分212的情况。由于鳍受到剩下的硬掩模阻挡层204的保护，而且注入基本上是垂直的，因此半导体衬底的受损部分212将集中在鳍之间的区域。
再来看图1，下一个步骤112是对晶片的受损区进行氧化。这可以用任何适当的氧化工艺来实现。如上所述，晶片的受损区以比未受损区高许多的速率氧化。因此，在鳍之间的区域内比在鳍本身上将更迅速和更深入地形成氧化物。在优选的以800℃氧化40分钟的状况下，两种氧化率之比大约为5∶1。这在鳍之间产生厚度足以使鳍相互隔离、但不会将鳍完全氧化掉的氧化物。此外，氧化层生长到鳍下可以进一步地使鳍隔离。具体地说，氧化层生长到鳍下将导致改善晶体管本身的源极与漏极之间的隔离。没有这种隔离，电流可能会在源极和漏极之间的鳍下流动，因为这个区域不是完全可以由晶体管的栅极控制的。应指出的是，在鳍下生长的氧化物不一定要完全延伸到鳍下，来提供晶体管的源极与漏极之间的足够隔离，虽然有时候这是所希望的。
这个步骤的另一方面是，在鳍的侧壁上生长氧化物可以使鳍内剩下的半导体材料的宽度变窄。鳍变窄由于改善了栅极提供的电流控制从而改善了晶体管的性能。应指出的是，在很多情况下希望鳍可以比用传统的光刻技术能准确形成图案的情况还要窄。因此，在很多情况下所希望的是用诸如侧壁图像传送之类的图像增强技术来限定鳍的宽度。因此，本发明的这些实施例具有在形成鳍之间的隔离期间进一步使鳍的宽度变窄而不会完全氧化掉鳍的附加优点。
现在来看图6，图中例示了晶片部分200在氧化形成了鳍210之间的隔离214后的情况。此外，氧化还在鳍210的侧壁上形成了氧化物216。由于鳍之间的衬底区域在氧化前受到损伤，鳍之间的氧化物生长率比在诸如鳍的侧壁之类的其他区域的氧化物生长率高许多。此外，在鳍210上形成氧化物216可以进一步使鳍的宽度变窄。
再来看图1，下一个步骤114是除去无用的氧化物和完成finFET器件。由于在鳍的侧壁上形成的氧化物比在鳍之间形成的氧化物薄许多，因此能从侧壁上除去，而在鳍之间留下足够的隔离氧化物。此外，在鳍的侧壁上形成氧化物可以进一步使鳍本身的宽度变窄。
随着鳍的限定和隔离的形成，于是可以完成finFET。如上所述，所揭示的这些方法可以用于任何类型的finFET制造工艺。下面将简要地说明一个示范性的工艺，但熟悉该技术领域的人员可以理解，也可以采用其他适当的工艺。
这个示范性的工艺的第一个步骤是对鳍掺杂。通常，这可以包括对鳍进行离子注入，以便形成P阱结构和N阱结构。在本发明的CMOS技术中，形成P阱结构和N阱结构，以使NFET和PFET可以集成在一个共同的衬底上。P、As和Sb例如很适合于PFET阱。B、In和Ga例如很适合于NFET阱。离子注入通常设计成能达到浓度例如在1×1017cm-3到5×1018cm-3之间。在一个实施例中，离子注入可以包括倾斜注入半导体层的所暴露的对置垂直侧壁，用来正确地对鳍掺杂。
下一个步骤是形成栅极堆叠。这可以包括在鳍的对置的垂直侧壁和对置的端壁上形成栅极绝缘层。栅极绝缘层可以通过通常以750-800℃的热氧化形成，或者也可以通过淀积一层电介质膜形成。例如，栅极绝缘层可以是SiO2、氮化氧化物材料、高K电介质材料或这些的组合，如在该技术领域所知的那样。
下一个步骤是形成一个覆盖栅极绝缘层的栅极导体层。栅极导体层可以是任何适当的导电材料，通常是多晶硅材料，虽然也可以是非晶态硅、非晶态硅和多晶硅的组合、多晶硅-锗，或者任何可用来形成栅极导体层的任何其他适当的材料。此外，在本发明的一些实施例中，使用诸如W、Mo或Ta或任何其他高熔点金属的金属栅极导体层，或者包括加有Ni或Co的多晶硅的硅化物栅极导体可能是有益的。在栅极导体层是硅材料时，可以淀积为一个掺杂层(在原处掺杂)。如果栅极导体层是一个金属层，这样的层可以用物理或化学气相淀积方法或者任何在该技术领域内已知的其他技术淀积。这样，就形成了与由半导体层部分形成的鳍的对置垂直侧壁上形成的氧化层相邻的栅极结构。
下一个步骤是使栅极导体层和栅极绝缘层形成图案。这通常通过淀积一个硬掩模膜并使硬掩模膜形成图案来实现的。通常，硬掩模膜材料可以是SiO2或Si3N4。因此，栅极导体层可以用众所周知的形成栅极叠层的光刻技术(photolithography)和蚀刻技术来形成其图案和结构，即在对栅极导体层进行定向蚀刻期间用硬掩模膜顶盖作为蚀刻掩模。这包括有选择地除去栅极导体层直到隔离层的部分，但不除去半导体层的形成鳍的由硬掩模膜保护的部分。因此，鳍可以延伸到超出栅极叠层。这样形成图案和结构还留下栅极导体层中限定与鳍主体相邻的栅极结构的部分。
下一个步骤是用源极/漏极(S/D)注入物对鳍的暴露部分掺杂。形成源区/漏区可以用任何已经为形成源区/漏区所开发的适应具体性能要求的方法实现。有许多这样的方法可用来形成具有不同复杂程度的源区/漏区。因此，在本发明的一些实施例中，例如用离子注入可以形成轻掺杂的源区/漏区或其他的源区/漏区。因此，对于NFET来说，通常用例如P、As或Sb进行能量为1至5keV、剂量为5×1014至2×1015cm-3的源区/漏区注入。类似，对于PFET来说，通常用例如B、In或Ga进行能量为0.5至3keV、剂量为5×1014至2×1015cm-3的源区/漏区注入。
可选地，可以形成延伸和晕式(halo)注入，它们可以改善短沟道效应(SCE)。对于NFET来说，通常可以用B、In或Ga进行能量为5至15keV和剂量为1×1013至8×1013cm-3的晕式注入。类似，对于PEET来说，可以用P、As或Sb进行能量为20至45keV剂量为1×1013至8×1013cm-3的晕式注入。
为了完成器件，然后可以形成对源极、漏极和栅极的触点。因此，通常可以用CMP工艺淀积电介质，再予以平整。然后可以用各向异性工艺(例如RIE)之类构成和蚀刻出触点孔。可以用诸如掺杂的多晶硅、硅化物(例如WSi)、金属(例如Au、Al、Mo、W、Ta、Ti、Cu或ITO(铟氧化锡))之类的任何导电材料，通过蒸发、溅射或其他已知技术进行淀积，来填充这些触点孔，从而形成S/D接触。然后可以用RIE工艺之类淀积和构成第一金属层。或者，也可以在镶嵌工艺流程后完成构成第一金属层。
现在来看图7，图中例示了在晶片部分200上完成的finFET器件。本发明的一个实施例示为具有最小的复杂性。在鳍210的每个侧面和鳍的对置端壁上形成栅极绝缘层220。栅极222形成为覆盖了栅极绝缘层220和硬掩模膜224。此外，在这个具体实施例中，栅极导体层222部分跨鳍的两侧是连续的，但是在其他实施例中，栅极导体层被分成两个部分。
按照本发明设计的在同一个衬底上利用对于FET电流沟道的不同晶面的CMOS FinFET可以用于许多不同类型的电路，诸如高性能逻辑电路、低功率逻辑电路或高密度存储器器件，包括高密度十亿比特级DRAM。而且，CMOS FinFET可以很容易与诸如电容、电阻、二极管、存储器单元之类的其他元件结合在一起。
因此，本发明提供了一种可以克服现有技术的许多缺点的形成鳍状场效应晶体管(FET)的器件结构和方法。具体地说，这种方法有利于从体半导体晶片以鳍高度控制得到改善的方式形成finFET器件。此外，这种方法能从体硅片形成finFET，同时提供各个鳍之间和各个finFET的源区与漏区之间的隔离。本发明的器件结构和方法因此具有可以用高效益的体晶片可靠和一致地制造finFET的优点。在这里所提出的实施例和例子在于较好地说明本发明及其实际应用，使一般熟悉该技术领域的人员可以采用本发明。然而，一般熟悉该技术领域的人员可以理解，上述说明和例子只是例示性的。本说明并不是穷举性的或者要将本发明限制在精确为所揭示的形式。根据以上原理许多修改和变动都是可行的，并不背离以下权利要求所给出的本发明的精神实质和专利保护范围。因此，除非另有说明，在附图中或在这里所示出的任何组成部分都是作为可能的组成部分的一个例子而不是作为一个限制。类似，除非另有说明，在这里所指出的本发明的方法的任何步骤或顺序都是作为可能的步骤或顺序的例子而不是作为限制给出的。
工业实用性
本发明的鳍状场效应晶体管(finFET)对于集成电路设计和制造是有用的，并且对于衬底包括体硅片的互补金属氧化物半导体(CMOS)技术特别有用。

Claims (19)

1.一种在半导体衬底(200)中形成一个鳍状场效应晶体管的方法，所述方法包括下列步骤：
在半导体衬底(200)上形成(102，104，106，108)一个鳍(210)；
损伤(110)与鳍(210)相邻的半导体衬底区域的至少一部分(212)；以及
在半导体衬底上生长绝缘体，使得绝缘体在半导体衬底的受损部分(214)内形成得比在鳍侧壁(216)上厚。
2.权利要求1的方法，其中在半导体衬底上生长绝缘体的步骤包括：
对半导体衬底进行氧化(112)，使得氧化物在半导体衬底的受损部分(214)内形成得比在鳍侧壁(216)上厚。
3.权利要求2的方法，其中所述损伤(110)与鳍(210)相邻的半导体衬底的至少一部分(212)的步骤包括对与鳍(210)相邻的半导体衬底的至少一部分执行离子注入。
4.权利要求3的方法，其中所述离子注入包括与鳍(210)平行地执行注入，以尽量减小对鳍的侧壁的损伤。
5.权利要求3的方法，所述方法还包括在鳍(210)的顶上提供(102)一个阻挡层(204)以减少对鳍(210)的损伤的步骤。
6.权利要求2的方法，其中所述损伤(110)与鳍(210)相邻的半导体衬底(200)的至少一部分(212)的步骤包括，执行增大与鳍(210)相邻的半导体衬底的至少一部分的多孔性的阳极反应。
7.权利要求6的方法，其中所述执行增大与鳍(210)相邻的半导体衬底的至少一部分的多孔性的阳极反应的步骤包括，对与鳍(210)相邻的半导体衬底执行p型注入、对半导体衬底(200)退火和使半导体衬底的至少一部分受到化学蚀刻剂的作用。
8.权利要求1的方法，其中所述在半导体衬底(200)上形成(108)鳍(210)的步骤包括下列步骤：
在半导体衬底(200)中形成(106)一个高度控制层；以及
对半导体衬底进行蚀刻(108)以限定鳍(210)，使得高度控制层有利于鳍高度的一致性。
9.权利要求8的方法，其中所述在半导体衬底(200)中形成(106)一个高度控制层的步骤包括对半导体衬底执行离子注入，所述离子注入将损伤衬底，以相对于衬底(200)的未受损部分的蚀刻率改变衬底的受损部分(212)的蚀刻率。
10.权利要求8的方法，其中所述在半导体衬底(200)中形成(106)一个高度控制层的步骤包括，在半导体衬底内形成一个标志层，并且其中所述对半导体衬底进行蚀刻(108)以限定鳍使得高度控制层有利于鳍高度的一致性的步骤包括，在对半导体衬底(200)进行蚀刻(108)期间对标志层进行监视。
11.权利要求1的方法，其中所述使衬底受到在隔离鳍(210)的同时进一步限定鳍(210)的宽度的工艺(110，112，114)处理的步骤使鳍的宽度变窄到小于在半导体衬底(200)上形成(102，104，106，108)鳍(210)的步骤中所用的工艺的最小特征尺寸。
12.一种在半导体衬底(200)中形成一个鳍状场效应晶体管的方法，所述方法包括下列步骤：
在半导体衬底(200)上形成(102，104，106，108)一个鳍(210)，鳍(210)包括一个鳍侧壁，鳍的形成暴露了与鳍(210)相邻的半导体衬底(200)的区域；
损伤(110)与鳍(210)相邻的半导体衬底区域的至少一部分(212)；以及
对半导体衬底进行氧化(112)，使得氧化物在半导体衬底的受损部分(214)内形成得比在鳍侧壁(216)上厚。
13.权利要求12的方法，其中所述损伤(110)与鳍(212)相邻的半导体衬底(200)的至少一部分(212)的步骤包括对与鳍(210)相邻的半导体衬底的至少一部分(212)执行离子注入。
14.权利要求12的方法，其中所述损伤(110)与鳍(212)相邻的半导体衬底(200)的至少一部分(212)的步骤包括执行增大与鳍(210)相邻的半导体衬底的至少一部分的多孔性的阳极反应。
15.权利要求14的方法，其中所述执行增大与鳍(210)相邻的半导体衬底的至少一部分的多孔性的阳极反应的步骤包括，对与鳍(210)相邻的半导体衬底执行p型注入、对半导体衬底(200)退火和使半导体衬底的至少一部分受到化学蚀刻剂的作用。
16.权利要求12的方法，其中所述在半导体衬底(200)上形成(102，104，106，108)鳍(210)的步骤包括下列步骤：
在半导体衬底(200)中形成(106)一个高度控制层；以及
对半导体衬底进行蚀刻(108)以限定鳍(210)，使得高度控制层有利于鳍高度的一致性。
17.权利要求16的方法，其中所述在半导体衬底(200)中形成(106)一个高度控制层的步骤包括，对半导体衬底执行离子注入，所述离子注入将损伤衬底，以相对于衬底(200)的未受损部分的蚀刻率改变衬底的受损部分(212)的蚀刻率。
18.权利要求16的方法，其中所述在半导体衬底(200)中形成(106)一个高度控制层的步骤包括，在半导体衬底内形成一个标志层，并且其中所述对半导体衬底进行蚀刻(210)以限定鳍(210)使得高度控制层有利于鳍高度的一致性的步骤包括，在对半导体衬底(200)进行蚀刻(210)期间对标志层进行监视。
19.一种在体半导体衬底(200)上形成鳍状场效应晶体管器件的方法，所述方法包括下列步骤：
在半导体衬底(200)中形成(106)一个高度控制层；
在半导体衬底(200)上形成(104)一个硬掩模阻挡层(204)；
对硬掩模阻挡层和半导体衬底进行蚀刻(108)以限定多个鳍(210)，使得高度控制层有利于鳍高度的一致性，其中一部分硬掩模阻挡层(204)留在多个鳍(210)中的每个鳍上，并且多个鳍(210)中的每个鳍包括一个侧壁，而对半导体衬底的蚀刻(108)暴露了与鳍(210)相邻的半导体衬底的区域；
损伤(110)与鳍(210)相邻的半导体衬底区域的至少一部分(212)；
氧化(112)半导体衬底，使得氧化物在半导体衬底的受损部分(214)内形成得比在鳍侧壁(216)上厚；以及
从鳍侧壁上除去(114)氧化物(216)，同时留下与鳍(210)相邻的至少一部分氧化物(214)。
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WO2003103019A2 (en) 2003-12-11
EP1532659A2 (en) 2005-05-25
AU2003237320A1 (en) 2003-12-19
JP4425130B2 (ja) 2010-03-03
WO2003103019A3 (en) 2004-03-18
EP1532659A4 (en) 2005-12-14
TW200411833A (en) 2004-07-01
US6642090B1 (en) 2003-11-04
IL165546A0 (en) 2006-01-15
JP2005528793A (ja) 2005-09-22
EP1532659B1 (en) 2011-03-02
KR20050003401A (ko) 2005-01-10

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