CN1287433C - 三栅极器件的加工方法 - Google Patents

三栅极器件的加工方法 Download PDF

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CN1287433C
CN1287433C CNB038005115A CN03800511A CN1287433C CN 1287433 C CN1287433 C CN 1287433C CN B038005115 A CNB038005115 A CN B038005115A CN 03800511 A CN03800511 A CN 03800511A CN 1287433 C CN1287433 C CN 1287433C
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silicon
gate electrode
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semiconductor body
gate
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CN1518771A (zh
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罗伯特·周
布赖恩·多伊尔
杰克·卡瓦列罗斯
道格拉斯·巴拉格
达塔·休曼
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Intel Corp
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Abstract

本发明公开了一种半导体器件,包括形成在衬底上的半导体主体,其具有顶表面和横向相对的侧壁。在半导体主体的顶表面上以及半导体主体的横向相对的侧壁上形成栅极电介质层。在半导体主体的顶表面上的栅极电介质上以及与半导体主体的横向相对的侧壁上的栅极电介质的相邻处形成栅极电极。

Description

三栅极器件的加工方法
技术领域
本发明涉及半导体集成电路制造领域,更具体地说,本发明涉及三栅极全耗尽型衬底晶体管及其加工方法。
背景技术
为了提高器件性能,绝缘体上硅(silicon on insulator,SOI)晶体管已被建议用来加工现代集成电路。图1示出了标准全耗尽型绝缘体上硅(SOI)晶体管100。SOI晶体管100包括单晶硅衬底102,其具有绝缘层104,例如其上形成的氧化埋层。在绝缘层104上形成单晶硅主体106。在单晶硅主体106上形成栅极电介质层108,并在栅极电介质层108上形成栅极电极110。在硅主体106中沿着栅极电极110的侧向相对的侧面形成源极112和漏极114区。
已建议将全耗尽型SOI作为晶体管结构,以利用优化的导通电流/截止电流比的理想亚阈值梯度。为了获得晶体管100的理想亚阈值梯度,硅主体106的厚度必须约是晶体管栅极长度(Lg)的尺寸的1/3,即Tsi=Lg/3。然而,随着栅极长度的变化,尤其是当它们接近30nm时,尽量降低硅膜厚度(Tsi)的需求使得这一接近越来越不实际。对于30纳米的栅极长度,人们认为硅主体的所需厚度需要小于10纳米,而对于20纳米的栅极长度,该厚度需要是6纳米左右。厚度小于10纳米的薄硅膜的加工是极其困难的。一方面,在一个纳米的量级上获得晶片一致性是一顶艰苦的挑战。另一方面,能够接触这些薄硅膜以形成凸起的源极/漏极区从而降低结电阻变得几乎不可能,因为在栅极刻蚀以及栅极刻蚀和隔离层刻蚀之后的各种清洁工艺期间,源极/漏极区中的薄硅层被消耗掉了,从而剩下不足的硅106用于硅的生长。
诸如图2A和图2B中示出的双栅极(DG)器件已被建议用来缓和关于硅厚度的问题。双栅极(DG)器件200包括形成在绝缘衬底204上的硅主体202。在硅主体202的两侧上形成栅极电介质206,并在硅主体202的两侧上形成的栅极电介质206的相邻处形成栅极电极208。足够厚的绝缘层209例如氮化硅使得栅极电极208与硅主体202的顶部之间电绝缘。
双栅极(DG)器件200基本上有2个栅极,分别位于器件沟道的两侧。因为双栅极器件200在沟道两侧都有栅极,所以硅主体的厚度(Tsi)可以是单栅极的两倍,并且仍可以获得全耗尽型晶体管的操作。也就是说,利用双栅极器件200,可以形成全耗尽型晶体管,其中Tsi=(2×Lg)/3。然而,双栅极(DG)器件200最可制造的形式需要使用某种光刻技术来完成硅主体202的图案化,该光刻技术比用来图案化该器件的栅极长度(Lg)的光刻技术要小0.7倍。为了获得高密度集成电路,一般希望将最激进的光刻法应用在栅极电极208的栅极长度(Lg)上。尽管双栅极结构使得硅膜的厚度加倍(由于现在沟道的两侧都有栅极),但是这些结构极难加工。例如,硅主体202需要这样一种硅主体刻蚀,其可产出纵横比(高宽比)约为5∶1的硅主体202。
发明内容
本发明的第一方面提供了一种形成半导体器件的方法,包括:在衬底上形成半导体主体,所述半导体主体具有与所述衬底分开第一距离的平坦顶表面和分开所述第一距离的横向相对的侧壁;在所述半导体主体的所述顶表面上以及所述半导体主体的所述横向相对的侧壁上形成栅极电介质;在所述半导体主体的所述顶表面上的所述栅极电介质上、并与所述半导体主体的所述横向相对的侧壁上的所述栅极电介质相邻形成栅极电极,所述栅极电极具有一对分开所述第一距离的横向相对的侧壁,所述栅极电极的所述横向相对的侧壁与所述半导体主体的所述横向相对的侧壁垂直;以及在所述半导体主体中,在所述栅极电极的相对侧面上形成源极区和漏极区。
根据本发明的第一方面,所述半导体主体可以包含单晶硅。所述单晶硅主体可以是本征硅。所述半导体主体还可以是从由硅、锗、硅锗合金、砷化镓、InSb、GaP、GaSb以及碳纳米管构成的组中选择的半导体。
根据本发明的第一方面,其中所述形成半导体器件的方法还可以包括:在所述栅极电极的所述横向相对的侧壁的相对侧面上、但不在所述半导体主体的所述横向相对的侧壁上形成一对侧壁隔离层;在所述半导体主体的所述顶表面上和所述半导体主体的所述横向相对的侧壁上、并与所述一对侧壁隔离层相邻形成半导体膜。
根据本发明的第一方面,其中还可以将在所述栅极电极之下的所述半导体主体掺杂到第一导电性类型的第一浓度水平;以及在所述栅极电极之下的所述半导体主体中形成具有所述第一导电性类型的第二浓度水平的halo区,其中所述第二浓度水平大于所述第一浓度水平。
在本发明的第一方面中,所述衬底可以是绝缘衬底或可以是半导体衬底。
本发明的第二方面提供了一种形成绝缘体上硅晶体管的方法,包括:将形成在绝缘衬底上的硅膜图案化成一种硅主体,其具有与形成在所述绝缘膜上的底表面相对的平坦的顶表面,其中所述顶表面与所述底表面分开第一距离,并且所述硅主体具有分开所述第一距离的第一和第二横向相对的侧壁;在所述硅主体的所述顶表面上和所述硅主体的所述侧壁上形成栅极电介质层;在所述硅主体上和所述绝缘衬底上沉积栅极材料;图案化所述栅极材料,以在所述硅主体的所述平坦的顶表面上的所述栅极电介质层之上、并与所述硅主体的所述侧壁上的所述栅极电介质相邻形成栅极电极,所述栅极电极具有垂直于所述硅主体的所述横向相对的侧壁而延伸的横向相对的侧壁,所述栅极电极的所述横向相对的侧壁分开所述第一距离;以及在所述硅主体中,在所述栅极电极的所述横向相对的侧壁的相对侧面上形成一对源极区和漏极区。
根据本发明的第二方面,还可以包括在所述栅极电极的所述横向相对的侧壁的相对侧面上、但不在所述硅主体的所述横向相对的侧壁上形成一对侧壁隔离层;在所述硅主体的所述顶表面上和所述硅主体的所述横向相对的侧壁上、并与在所述栅极电极的所述横向相对的侧壁的相对侧面上的所述一对侧壁隔离层相邻形成第二硅膜。
根据本发明的第二方面,所述硅膜可以是单晶硅。所述单晶硅膜可以是本征硅。
根据本发明的第二方面,其中还可以将在所述栅极电极之下的所述硅主体掺杂到第一导电性类型的第一浓度水平;以及在所述栅极电极之下的所述半导体主体中形成具有所述第一导电性类型的第二浓度水平的halo区,其中所述第二浓度水平大于所述第一浓度水平。
根据本发明的第二方面,还可以包括在形成于所述硅主体上的第二硅膜上形成硅化物。
根据本发明的第二方面,还可以包括:在所述绝缘衬底上形成第二硅主体,其具有顶表面和横向相对的侧壁;在所述第二硅主体所述顶表面和所述第二硅主体的所述侧壁上形成第二栅极电介质层;在所述第二硅主体的所述顶表面上的所述栅极电介质层上、并与在所述第二硅主体的所述侧壁上的所述栅极电介质层相邻形成所述栅极电极;由所述硅膜形成将所述第一源极区与所述第二源极区连接的源极附着块;以及由所述硅膜形成将所述第一漏极区与所述第二漏极区连接的漏极附着块。
附图说明
图1是耗尽型衬底晶体管的截面图的示例。
图2A和图2B图示了双栅极耗尽型衬底晶体管。
图3是根据本发明实施例的三栅极晶体管的示例。
图4A是根据本发明实施例的三栅极晶体管的示例。
图4B是根据本发明实施例的三栅极晶体管的示例。
图5A-5J图示了加工根据本发明实施例的三栅极晶体管的方法。
图6是一张曲线图表,图示了可用于获得具有30nm和20nm的栅极长度(Lg)的部分耗尽型和全耗尽型晶体管的主体高度和主体宽度。
具体实施方式
本发明是一种新型三栅极晶体管结构及其加工方法。在下面的描述中,给出了大量具体细节,以提供对本发明的透彻的了解。在其他情况下,没有以具体的细节来描述公知的半导体工艺和制造技术,以免不必要地混淆本发明。
本发明是一种新型三栅极晶体管结构及其加工方法。在本发明的实施例中,三栅极晶体管是绝缘体上硅(SOI)晶体管。将三栅极晶体管用于全耗尽型晶体管应用中是很理想的。三栅极晶体管包括在衬底上形成的薄半导体主体,该衬底可以是绝缘衬底或半导体衬底。在半导体主体的顶表面和侧壁上形成栅极电介质。在半导体主体顶表面上的栅极电介质上、以及在半导体主体侧壁上形成的栅极电介质相邻处形成栅极电极。在半导体主体中栅极电极的相对侧上形成源极和漏极区。因为栅极电极和栅极电介质包围在半导体主体的三个侧面上,因此晶体管本质上具有三个分离的沟道和栅极。晶体管的栅极“宽度”等于半导体主体三个侧面中的每一个侧面的总和。可以通过将几个三栅极晶体管连接在一起来形成更大“宽度”的晶体管。
因为在半导体主体中形成了三个分离的沟道,所以当晶体管被“导通”时半导体主体可以是完全耗尽的,从而使得可用小于30纳米的栅极长度来形成全耗尽型晶体管,而不需要使用超薄半导体主体或需要半导体主体的光刻图案的尺寸小于器件的栅极长度(Lg)。也就是说,在半导体主体的厚度以及半导体主体的宽度等于器件的栅极长度的情况下,本发明的三栅极晶体管的结构使得可加工出全耗尽型晶体管。因为本发明的新型三栅极晶体管可以按全耗尽的方式操作,所以器件具有下述特征:理想的(即非常陡峭的)亚阈值斜率;降低的漏场感应势垒降低(DIBL)短沟道效应,其小于100mV/V,理想值约为60mV/V,获得了器件“截止”时较小的漏电流,从而获得了较低的功耗。
图3中图示了根据本发明实施例的三栅极晶体管300的例子。三栅极晶体管300形成在衬底302上。在本发明的实施例中,衬底302是绝缘衬底,其包括较下面的单晶硅衬底304,在此单晶硅衬底上形成绝缘层306,例如二氧化硅膜。然而,三栅极晶体管300可在任意公知的绝缘衬底上形成,例如由二氧化硅、氮化物、氧化物和蓝宝石(sapphires)形成的衬底。在本发明的实施例中,衬底302可以是半导体衬底,例如但不局限于单晶硅衬底和砷化镓衬底。
三栅极晶体管300包括形成在绝缘衬底302的绝缘体306上的半导体主体308。半导体主体308可由任意公知的半导体材料形成,例如但不局限于硅(Si)、锗(Ge)、锗化硅(SixGey)、砷化镓(GaAs)、InSb、GaP、GaSb和碳纳米管。半导体主体308可由任意这样的公知材料形成,该材料可以通过施加外部电控制而从绝缘状态可逆地改变成导电状态。当希望得到晶体管300的最佳电学性能时,半导体主体308理想地是单晶体膜。例如,当晶体管300用于高性能应用例如像微处理器之类的高密度电路中时,半导体主体308是单晶体膜。然而,当晶体管300用于需要较低性能的应用例如液晶显示器中时,半导体主体308可以是多晶体膜。绝缘体306将半导体主体308从单晶硅衬底302绝缘开来。在本发明的实施例中,半导体主体308是单晶硅膜。半导体主体308具有一对横向相对的侧壁310和312,二者被一段界定了半导体主体宽度314的距离所分开。另外,半导体主体308具有与形成在衬底302上的底表面318相对的顶表面316。顶表面316和底表面318之间的距离界定了主体高度320。在本发明的实施例中,主体高度320与主体宽度314基本相等。在本发明的实施例中,主体308具有小于30纳米的宽度314和高度320,理想情况下小于20纳米。在本发明的实施例中,主体高度320介于主体宽度314的1/2和主体宽度314的2倍之间。
三栅极晶体管300具有栅极电介质层322。栅极电介质层322形成在半导体主体308的三个侧面上并包围这三个侧面,如图3所示。栅极电介质层322形成在主体308的侧壁312上或与之相邻、顶表面316上以及侧壁310上或与之相邻,如图3所示。栅极电介质层322可以是任意公知的栅极电介质层。在本发明的实施例中,栅极电介质层是二氧化硅(SiO2)、氮氧化硅(SiOxNy)或氮化硅(Si3N4)电介质层。在本发明的实施例中,栅极电介质层322是厚度形成在5-20之间的氮氧化硅膜。在本发明的实施例中,栅极电介质层322是高K栅极电介质层,例如金属氧化物电介质,例如但不局限于五氧化钽(Ta2O5)和二氧化钛(TiO2)。栅极电介质层322可以是其他类型的高K电介质,例如但不局限于PZT。
三栅极器件300具有栅极电极324。栅极电极324形成在栅极电介质层322上并包围栅极电介质层322,如图3所示。栅极电极324形成在形成于半导体主体308的侧壁312上的栅极电介质322之上或与之相邻、形成于半导体主体308的顶表面316上的栅极电介质322之上以及形成于半导体主体308的侧壁310上的栅极电介质层322之上或与之相邻。栅极电极324具有一对横向相对的侧壁326和328,二者被一段界定了晶体管300的栅极长度(Lg)360的距离所分开。在本发明的实施例中,栅极电极324的横向相对的侧壁326和328与半导体主体308的横向相对的侧壁310和312垂直。
栅极电极324可以由任意合适的栅极电极材料形成。在本发明的实施例中,栅极电极324由掺杂到浓度为1×1019原子数/cm3-1×1020原子数/cm3之间的多晶硅构成。在本发明的实施例中,栅极电极可以是金属栅极电极,例如但不局限于钨、钽、钛及其氮化物。在本发明的实施例中,栅极电极由具有在4.6-4.8eV之间的中间带隙(mid-gap)功函数的材料而形成。应该认识到,栅极电极324不一定需要是单种材料,而可以是多个薄膜的复合叠层,例如但不局限于多晶硅/金属电极或金属/多晶硅电极。
三栅极晶体管300具有源极区330和漏极区332。源极区330和漏极区332形成在半导体主体308中栅极电极324的相对两侧,如图3所示。源极区330和漏极区332由相同的导电性类型形成,例如N型或P型导电性。在本发明的实施例中,源极区330和漏极区332具有1×1019和1×1020原子数/cm3之间的掺杂浓度。源极区330和漏极区332可以形成为具有均匀的浓度,或者可以包括具有不同浓度或掺杂特性的子区域,例如尖端区域(tip region)(例如源极/漏极延伸)。在本发明的实施例中,当晶体管300是对称晶体管时,源极区330和漏极区332将具有相同的掺杂浓度和特性。在本发明的实施例中,当三栅极晶体管300形成为非对称晶体管时,源极区330和漏极区332的掺杂浓度和特性可以不同,以获得特定的电学特性。
半导体主体308位于源极区330和漏极区332之间的部分界定了晶体管300的沟道区350。沟道区350也可以定义为半导体主体308被栅极电极324所包围的区域。然而,源极/漏极区有时候可以通过例如扩散而稍微延伸到栅极电极的下面,以定义稍小于栅极电极长度(Lg)的沟道区。在本发明的一个实施例中,沟道区350是本征的或未掺杂的单晶硅。在本发明的一个实施例中,沟道区350是掺杂的单晶硅。当沟道区350掺杂时,它一般掺杂到1×1016和1×1019原子数/cm3之间的导电性水平。在本发明的实施例中,当沟道区掺杂时,它一般掺杂成与源极区330和漏极区332相反的导电性类型。例如,当源极和漏极区是N型导电性时,沟道区就被掺杂成P型导电性。类似地,当源极和漏极区是P型导电性时,沟道区就是N型导电性。以这种方式,三栅极晶体管300可以分别被形成为NMOS晶体管或PMOS晶体管。沟道区350可以被均匀地掺杂,或者可以非均匀地或以不同浓度掺杂,以提供特定的电学和性能特性。例如,如果希望的话,沟道区350可以包括公知的“halo”区。
通过提供在三个侧面上包围半导体主体的栅极电介质和栅极电极,三栅极晶体管就具有了包括三个沟道和三个栅极的特性,其中一个(g1)延伸在硅主体308的侧面312上的源极和漏极区之间,第二个(g2)延伸在硅主体308的顶表面316上的源极和漏极区之间,而第三个(g3)延伸在硅主体308的侧壁310上的源极和漏极区之间。晶体管300的栅极“宽度”(Gw)是这三个沟道区的宽度的总和。也就是说,晶体管300的栅极宽度等于硅主体308在侧壁310处的高度,加上硅主体308在顶表面316处的宽度,再加上硅主体308在侧壁312处的高度。通过使用耦合在一起的多个器件(例如,单个栅极电极324所包围的多个硅主体308),可以获得更大“宽度”的晶体管。
因为沟道区350在三个侧面上被栅极电极324和栅极电介质322所包围,所以晶体管300可以按全耗尽方式而操作,其中,当晶体管300“导通”时,沟道区350是全耗尽的,从而提供了全耗尽型晶体管的有利的电学特性和性能。也就是说,当晶体管300“导通”时,在沟道区350处形成了耗尽区,并在区350的表面处形成反转层(即,在半导体主体的侧表面和顶表面形成反转层)。所述反转层具有和源极与漏极区相同的导电性类型,并在源极和漏极区之间形成导电沟道,以使得电流可在二者之间流动。本发明的三栅极晶体管可以说是一种非平面的晶体管,因为在半导体主体308的水平和垂直方向上都形成了沟道区。耗尽区将来自反转层下面的自由载波耗尽。耗尽区延伸到沟道区350的底部,因此该晶体管可以说是“全耗尽型”晶体管。全耗尽型晶体管与非全耗尽型或部分耗尽型晶体管相比具有改进的电学性能特性。例如,通过按全耗尽方式来操作晶体管300,可以使得晶体管300具有理想的或非常陡峭的亚阈值斜率。三栅极晶体管可以被加工成具有非常陡峭的小于80mV/decade的亚阈值斜率,理想情况下约是60mV/decade,即使该晶体管是用厚度小于30nm的半导体主体加工而成的。另外,以全耗尽方式操作晶体管300时,晶体管300具有改进的漏场感应势垒降低(DIBL)效应,其提供了更好的“截止”状态漏电流,导致了更小漏电流,从而降低了功耗。在本发明的实施例中,三栅极晶体管300具有小于100mV/V的DIBL效应,理想状况下小于40mV/V。
图6图示了两张曲线图表,给出可产出栅极长度分别为30nm(602)和20nm(604)的全耗尽(F.D)或部分耗尽(P.D)三栅极晶体管的主体高度和主体宽度。在本发明的实施例中,选择具有这样尺寸的主体高度、主体宽度和栅极长度,即在这些尺寸中可以形成全耗尽型晶体管。在其他实施例中,三栅极晶体管具有使得可形成部分耗尽型晶体管的主体高度、主体宽度和栅极长度。
在本发明的实施例中,三栅极晶体管300的源极和漏极区可包括形成在半导体主体308之上及其周围的硅或其他半导体膜,如图4A所示。例如,半导体膜410可以是硅膜或诸如锗化硅(SixGey)的硅合金。在本发明的实施例中,半导体膜410是形成有与源极区330和漏极区332相同的导电性类型的单晶硅膜。在本发明的实施例中,该半导体膜可以是硅合金例如锗化硅,其中硅构成该合金约1到99的原子百分比。半导体膜410不一定需要是单晶体半导体膜,并且在一个实施例中,可以是多晶体膜。在本发明的实施例中,半导体膜410形成在半导体主体308的源极区330和漏极区332上,以形成“凸起”的源极和漏极区。半导体膜410可以通过一对电介质侧壁隔离层420例如氮化硅或二氧化硅或其组合物而与栅极电极324电绝缘。侧壁隔离层420沿着栅极电极324的横向相对的侧壁326和328延伸,如图4A所示,从而将半导体膜410与栅极电极324电绝缘,如图4A所示。在本发明的实施例中,侧壁隔离层420具有20-200之间的厚度。通过向半导体主体的源极和漏极区330和332添加硅或半导体膜并形成“凸起”的源极和漏极区,提高了源极和漏极区的厚度,从而减少了源极/漏极到晶体管300的接触电阻,并改进了其电学特性和性能。
在本发明的实施例中,在源极区330和漏极区332上形成硅化物膜430,例如但不局限于硅化钛、硅化镍和硅化钴。在本发明的实施例中,在硅主体308的硅膜410上形成硅化物膜430,如图4A所示。然而,也可将硅化物膜430直接形成到硅主体308的顶表面316上。例如,通过先形成诸如未掺杂硅膜的硅膜和硅主体,然后在硅化工艺中完全消耗该硅膜,可以在硅主体308上形成硅化物膜430。电介质隔离层420使得可在一个自对齐工艺(即硅化工艺)中在半导体主体308或硅膜410上形成硅化物膜430。
另外,在本发明的所述实施例中,也可在栅极电极324的顶部上形成半导体或硅膜440,如在栅极电极325的顶表面上形成硅化物膜450一样。硅化物膜450和硅膜440一般与在硅主体308上形成硅化物膜430和硅膜410的相同时间形成。在栅极电极上的硅化物膜450上形成硅膜440减小了到栅极的接触电阻,从而改进了晶体管300的电学性能。
如上所述,晶体管300的栅极“宽度”等于从晶体管300的半导体主体308创建的三个栅极宽度的总和。为了加工出具有更大栅极宽度的晶体管,晶体管300可以包括额外的或多个半导体主体或者指形(finger)308,如图4B所示。每个半导体主体308具有形成在其顶表面和侧壁上的栅极电介质层322,如图4B所示。栅极电极324形成在所述多个半导体主体308中的每一个的每个栅极电介质322上或与其相邻。每个半导体主体308还包括源极区330和漏极区332,二者形成在半导体主体308中与栅极电极324相对的侧面上,如图4B所示。在本发明的实施例中,每个半导体主体308形成为具有与其他半导体主体308相同的宽度和高度(厚度)。在本发明的实施例中,所述多个半导体主体308的每个源极区330和漏极区332被用来形成半导体主体308的半导体材料电耦合在一起,以形成源极附着块460和漏极附着块480,如图4B所示。或者,可以通过用于将各种晶体管300电互连成功能电路的高级别敷金属(metalization)处理(例如金属1、金属2、金属3……)而将多个源极330和多个漏极332耦合在一起。图4B所示的晶体管300的栅极宽度等于所述多个半导体主体308中的每一个所创建的栅极宽度的总和。按这种方式,可形成具有任意所需栅极宽度的三栅极晶体管300。
图5A-5J中图示了根据本发明实施例的三栅极晶体管的加工方法。三栅极晶体管的加工开始于衬底502。在衬底502上形成硅或半导体膜508,如图5A所示。在本发明的实施例中,衬底502是绝缘衬底,如在图5A中所示。在本发明的实施例中,绝缘衬底502包括较下层的单晶硅衬底504和顶部绝缘层506,例如二氧化硅膜或氮化硅膜。绝缘层506将半导体膜508与衬底504绝缘开来,在实施例中形成为厚度在200-2000之间。有时将绝缘层506称为“氧化埋”层。当在绝缘衬底502上形成硅或半导体膜508时,也就创建了绝缘体上硅或半导体(SOI)衬底500。在本发明的其他实施例中,衬底502可以是半导体衬底,例如但不局限于硅单晶体衬底和砷化镓衬底。
尽管理想情况下半导体膜508是硅膜,单在其他实施例中,它可以是其他类型的半导体膜,例如但不局限于锗(Ge)、硅锗合金(SixGey)、砷化镓(GaAs)、InSb、GaP、GaSb以及碳纳米管。在本发明的实施例中,半导体膜508是本征(即未掺杂)硅膜。在其他实施例中,半导体膜508掺杂成P型或N型导电性,具有在1×1016-1×1019原子数/cm3之间的浓度水平。通过例如离子注入,半导体膜508可以被即时(insitu)掺杂(即在沉积时掺杂),或当其在衬底502上形成后来掺杂。形成后掺杂使得可在相同绝缘衬底上同时加工出PMOS和NMOS三栅极器件。此时半导体主体的掺杂水平确定了器件的沟道区的掺杂水平。
半导体膜508被形成为具有这样一个厚度,其约等于随后形成的所加工三栅极晶体管的半导体主体或多个主体的所期望的高度。在本发明的实施例中,半导体膜508具有小于30纳米的厚度或者高度509,理想情况下小于20纳米。在本发明的实施例中,半导体膜508被形成为具有约等于所加工出的三栅极晶体管所期望的栅极“长度”的厚度。在本发明的实施例中,半导体膜508被形成为比器件所期望的栅极长度要厚。在本发明的实施例中,半导体膜508被形成为具有这样一个厚度,其使得所加工出的三栅极晶体管对于其设计栅极长度(Lg)可以按全耗尽方式操作。
可以按任何公知方法来在绝缘衬底502上形成半导体膜508。在一种称为SIMOX技术的形成绝缘体上硅衬底的方法中,将高剂量的氧原子注入到单晶硅衬底中,然后退火,以在衬底内形成氧化埋层506。单晶硅衬底在氧化埋层上的部分成为硅膜508。另一种当前用来形成SOI衬底的技术是外延硅膜转移(epitaxial silicon film transfer)技术,一般称为粘结SOI(bonded SOI)。在此技术中,第一硅晶片具有在其表面上生长的薄层氧化物,该氧化物后面将用作SOI结构中的氧化埋层506。然后,向第一硅晶片中注入高剂量的氢,以在第一晶片的硅表面下形成高压区。然后将此第一晶片翻转并粘结到第二硅晶片的表面。然后沿着由氢注入而产生的高压平面将第一晶片劈开。这样就得到了一种SOI结构,在顶部具有薄硅层,其下是在单晶硅衬底的顶部上的氧化埋层。可以使用多种公知平滑技术例如HC平滑或化学机械抛光(CMP)来平滑半导体膜508的顶表面,直至得到所希望的厚度。
此时,如果希望的话,可以在SOI衬底500中形成绝缘区(未示出),以将其中要形成的各晶体管彼此绝缘。通过使用例如公知的光刻和刻蚀技术来将衬底508包围三栅极晶体管的部分刻蚀掉,然后用绝缘膜例如SiO2来回填所刻蚀的区域,可形成绝缘区。
为了在衬底500上形成三栅极晶体管,在半导体膜508上形成光阻掩膜510,如图5B所示。光阻掩膜510包含一个图案或多个图案512,所述图案界定了随后在半导体膜508中形成半导体主体或者鳍状部分的位置。光阻图案512界定了随后形成的三栅极晶体管的半导体主体或者鳍状部分的所希望的宽度518。在本发明的实施例中,图案512界定了具有宽度518的鳍状部分或者主体,其中宽度518等于或大于所加工出的晶体管的栅极长度(Lg)的所希望的宽度。以这种方式,将用于加工晶体管的最严格的光刻约束与栅极电极图案相关联,而不是半导体主体或者鳍状部分定义。在本发明的实施例中,半导体主体或者鳍状部分将具有小于或等于30纳米的宽度518,理想情况下小于或等于20纳米。在本发明的实施例中,用于半导体主体或者鳍状部分的图案512具有约等于硅主体高度509的宽度518。在本发明的实施例中,光阻图案512具有在半导体主体高度509的1/2和半导体主体高度509的两倍之间的宽度518。
另外,如图5B所示,光阻掩膜510还可包括图案514和516,用于定义分别形成源极附着块和漏极附着块的位置。所述附着块可以用来将加工出的晶体管的各源极区连接到一起,并将各漏极区连接到一起。通过包括对覆盖沉积光阻膜进行掩膜设置、曝光及显影在内的公知光刻技术,可形成光阻掩膜510。
在形成光阻掩膜510之后,与光阻掩膜510对齐地刻蚀半导体膜508,以形成一个或多个硅主体或者鳍状部分,以及源极和漏极附着块(如果希望的话),如图5C所示。刻蚀半导体膜508,直到暴露出下面的氧化埋层506。可以使用公知的半导体刻蚀技术例如各向异性等离子刻蚀或活性离子刻蚀来与掩膜510对齐地刻蚀半导体膜508,如图5C所示。
在刻蚀半导体膜508以形成半导体主体或者鳍状部分520(以及源极/漏极附着块522和524,如果希望的话)之后,通过公知技术例如通过化学剥离和O2除灰来去除光阻掩膜以产出图5D所示的衬底。
然后,在每个半导体主体520上及其周围形成栅极电介质层526。也就是说,在每个半导体主体520的顶表面527上,以及在每个半导体主体520的横向相对的侧壁528和529上形成栅极电介质层526。该栅极电介质可以是沉积的电介质或生长的电介质。在本发明的实施例中,栅极电介质层526是用干/湿氧化工艺生长的二氧化硅电介质膜。在本发明的实施例中,该二氧化硅膜生长到厚度在5-15之间。在本发明的实施例中,栅极电介质膜526是沉积的电介质,例如但不局限于介电常数较高的膜,例如金属氧化物电介质,例如五氧化钽(Ta2O5)和氧化钛(TiO2)以及其他高K电介质,例如PZT和BST。可以通过任意公知的技术例如化学气相沉积(CVD)来形成介电常数较高的膜。
然后,如图5E所示,形成栅极电极530。栅极电极530形成在形成于每个半导体主体520的顶表面527上的栅极电介质层526之上,以及形成在形成于每个半导体主体的侧壁528和529之上或与之相邻的栅极电介质526之上或与之相邻,如图5E所示。栅极电极530具有与其形成在绝缘衬底502之上的底表面相对的顶表面532,并具有一对横向相对的侧壁534和536。横向相对的侧壁534和536之间的距离界定了三栅极晶体管的栅极长度(Lg)538。栅极电极530可以通过在图5D所示的衬底上覆盖沉积合适的栅极电极材料而形成。栅极电极可以形成为具有在200-3000之间的厚度。在实施例中,栅极电极具有至少3倍于半导体主体520的高度509的厚度或者高度533。然后可用公知的光刻或刻蚀技术对栅极电极材料进行图案化,以从栅极电极材料形成栅极电极530。在本发明的实施例中,栅极电极材料包括多晶硅。在本发明的另一个实施例中,栅极电极材料包括多晶体锗化硅合金。在本发明的另一个实施例中,栅极电极材料可以包括金属膜,例如钨、钽及其氮化物。栅极电极530可以通过公知的技术而形成,例如在图5D的衬底上覆盖沉积栅极电极材料,然后用公知的光刻或刻蚀技术对栅极电极材料进行图案化。在本发明的另一实施例中,用于定义栅极电极530的光刻工艺利用了用于加工三栅极晶体管的最低限度或者最小尺寸的光刻工艺。(也就是说,在本发明的实施例中,栅极电极530的栅极长度(Lg)538具有由光刻定义的晶体管最小特征尺寸。)在本发明的实施例中,栅极长度538小于或等于30纳米,理想情况下小于或等于20纳米。
然后,在半导体主体520中相对于栅极电极530的侧面上形成晶体管的源极和漏极区。在本发明的实施例中,源极和漏极区包括尖端或者源/漏区延伸区。可以通过下述方式分别形成源极和漏极延伸区540和542,即将掺杂剂544放置于半导体主体520中栅极电极530的两个侧面532和534中,以形成尖端区540和542,如图5F所示。在图5F-5J中没有示出源极和漏极附着块522和524,以更好地图示本发明的各方面。如果利用了源极和漏极附着块522和524,它们也可以在此时进行掺杂。对PMOS三栅极晶体管来说,半导体鳍状部分或者主体520被掺杂成P型导电性,并具有1×1020-1×1021原子数/cm3的浓度。对NMOS三栅极晶体管来说,半导体鳍状部分或者主体520以n型导电性离子而被掺杂成具有1×1020-1×1021原子数/cm3的浓度。在本发明的实施例中,用离子注入来对硅膜进行掺杂。在本发明的实施例中,在垂直方向(即与衬底500垂直的方向)上进行离子注入,如图5F所示。当栅极电极530是多晶硅栅极电极时,可以在离子注入工艺期间对它进行掺杂。栅极电极530用作掩膜,以防止离子注入步骤对三栅极晶体管的(多个)沟道区548产生掺杂。沟道区548是硅主体520位于栅极电极530下面或被其所包围的部分。如果栅极电极530是金属电极,则可以使用电介质硬掩膜来阻塞离子注入工艺期间的掺杂。在其他实施例中,可以使用其他方法例如固态源扩散来对半导体主体进行掺杂以形成源极和漏极延伸。
在本发明的多个实施例中,在形成源/漏区或源极/漏极延伸区之前,可在硅主体中形成“halo”区。Halo区是在器件的沟道区548中形成的掺杂区,具有与器件道沟区相同的导电性,但具有稍高于器件沟道区的掺杂浓度。利用成较大角度的离子注入技术,通过在栅极电极下离子注入掺杂剂,可形成halo区。
然后,如果希望的话,可以进一步处理图5F中的衬底,以形成额外特征,例如重掺杂的源极/漏极接触区、源极和漏极区以及栅极电极上的沉积硅,以及在源极/漏极接触区和栅极电极上形成硅化物。
在本发明的多个实施例中,电介质侧壁隔离层550可以形成在栅极电极的侧壁上。可以利用侧壁隔离层来补偿重源极/漏极接触注入,在选择性硅沉积工艺中将源极/漏极区与栅极电极绝缘开来,以及在硅化工艺中在源极和漏极区以及栅极电极上形成硅化物。可以通过在图5F的衬底500上覆盖沉积适形的(conformal)电介质膜550来形成隔离层,所述电介质膜例如是但不局限于氮化硅、氧化硅、氮氧化硅或其组合物。以适形的方式沉积电介质膜,以使得它在垂直表面以及水平表面上形成为具有大致相等的高度,所示垂直表面例如是栅极电极530的侧壁534和536,而所述水平表面例如是硅膜520的顶部526和栅极电极530的顶部。在本发明的实施例中,所述电介质膜是由热壁低压化学气相沉积(LPCVD)工艺形成的氮化硅膜。电介质膜的沉积厚度确定了所形成的隔离层的宽度或者厚度。在本发明的实施例中,所示电介质膜形成为具有20-200之间的厚度。
然后,如图5G所示,通过例如等离子刻蚀或活性离子刻蚀来对电介质膜进行各向异性刻蚀,以形成侧壁隔离层550。电介质膜的各向异性刻蚀从水平表面例如栅极电极530的顶部(以及附着块522和524的顶部,如果使用了的话)上去除电介质膜,而留下了与垂直表面例如栅极电极530的侧壁534和536相邻的电介质侧壁隔离层。所述刻蚀持续了一段充分长的时间,以从所有水平表面上去除电介质膜。在本发明的实施例中,利用了过度刻蚀,以使得可去除半导体主体520的侧壁上的隔离层材料,如图5G所示。结果就形成了侧壁隔离层550,其沿着栅极电极530的侧壁532和534而延伸并与之相邻,如图5H所示。
然后,如果希望的话,可以在半导体主体520的暴露表面上(以及在附着块522和524上)形成半导体膜560,如图5H所示。另外,如果希望的话,可以在栅极电极530的顶部上形成半导体膜562。所述半导体膜可以是单晶体膜或多晶体膜。在本发明的实施例中,半导体膜560是外延(单晶体)硅膜。在本发明的实施例中,硅膜560是由选择性沉积工艺形成的,从而使得只在含有硅的暴露区域上形成硅,例如硅主体520的顶表面527以及侧壁528和529。在选择性沉积工艺中,不在电介质区域例如侧壁隔离层555上形成硅膜。当栅极电极530包括多晶硅膜时,也可在栅极电极530的顶表面上选择性地形成硅膜,以形成硅膜562。在本发明的实施例中,硅膜560形成为具有在50-500之间的厚度。在本发明的实施例中,硅膜形成为具有这样的厚度,即该厚度足以提供足够的硅,以在源极和漏极区上形成硅膜期间被使用或消耗。所述硅膜可以是即时掺杂(即在沉积期间掺杂)或随后掺杂的,通过例如离子注入或固态源扩散。硅膜被掺杂成器件的源极和漏极区所希望的导电性类型。在本发明的实施例中,沉积硅膜560和562是本征硅膜(即未掺杂硅膜)。半导体膜560的沉积形成了凸起的源极和漏极区,提高了器件的寄生效应。
在本发明的实施例中,如图5I所示,通过利用垂直离子注入角度的离子注入来对沉积硅膜560和562进行掺杂。离子注入工艺将沉积硅膜560和位于下面的硅主体520掺杂成具有在1×1020-1×1021原子数/cm3的浓度,以形成源极接触区570和漏极接触区572。侧壁隔离层550补偿源极/漏极接触注入步骤,并将已掺杂的硅主体在侧壁隔离层550下的区域定义为所述尖端区域。上述工艺形成了源极区570和漏极区572,二者都包括尖端区和接触区。尖端区是硅主体520位于侧壁隔离层550下面的区域。接触区是硅主体和沉积硅膜与侧壁隔离层550的外部边缘相邻的区域。另外,如果利用了源极和漏极附着块522和524的话,源极/漏极接触区包括源极和漏极附着块522和524。
然后,如果希望的话,可以在源极和漏极接触区以及栅极电极530的顶表面(或硅膜562)上形成耐火金属硅化物,如图5J所示。可用自对齐工艺例如硅化工艺来形成耐火金属硅化物膜。在硅化工艺中,在图5J的衬底上覆盖沉积耐火金属膜,例如钛、钨、镍、钴等等。然后将衬底加热到合适的温度,以使得耐火金属膜与衬底500的硅部分反应,以形成耐火金属硅化物,所述硅部分例如是形成在硅主体上的硅膜560和形成在栅极电极上的硅膜562。没有硅可发生反应的位置例如电介质隔离层555和氧化埋层506的暴露部分不发生反应,仍然是耐火金属。然后可用选择性刻蚀例如湿刻蚀来去除未反应的耐火金属,而保留接触区上的耐火金属硅化物。按这种方式,金属硅化物膜可与三栅极晶体管的接触区自对齐。这就根据本发明完成了三栅极晶体管的加工。
至此,已描述了三栅极晶体管及加工方法。

Claims (15)

1.一种形成半导体器件的方法,包括:
在衬底上形成半导体主体,所述半导体主体具有与所述衬底分开第一距离的平坦顶表面和分开所述第一距离的横向相对的侧壁;
在所述半导体主体的所述顶表面上以及所述半导体主体的所述横向相对的侧壁上形成栅极电介质;以及
在所述半导体主体的所述顶表面上的所述栅极电介质上、并与所述半导体主体的所述横向相对的侧壁上的所述栅极电介质相邻形成栅极电极,所述栅极电极具有一对分开所述第一距离的横向相对的侧壁,所述栅极电极的所述横向相对的侧壁与所述半导体主体的所述横向相对的侧壁垂直;
在所述半导体主体中,在所述栅极电极的相对侧面上形成源极区和漏极区。
2.如权利要求1所述的方法,其中所述半导体主体包含单晶硅。
3.如权利要求2所述的方法,其中所述单晶硅主体是本征硅。
4.如权利要求1所述的方法,其中所述半导体主体是从由硅、锗、硅锗合金、砷化镓、InSb、GaP、GaSb以及碳纳米管构成的组中选择的半导体。
5.如权利要求1所述的方法,其中所述形成半导体器件的方法还包括:
在所述栅极电极的所述横向相对的侧壁的相对侧面上、但不在所述半导体主体的所述横向相对的侧壁上形成一对侧壁隔离层;
在所述半导体主体的所述顶表面上和所述半导体主体的所述横向相对的侧壁上、并与所述一对侧壁隔离层相邻形成半导体膜。
6.如权利要求1所述的方法,其中将在所述栅极电极之下的所述半导体主体掺杂到第一导电性类型的第一浓度水平;以及
在所述栅极电极之下的所述半导体主体中形成具有所述第一导电性类型的第二浓度水平的halo区,其中所述第二浓度水平大于所述第一浓度水平。
7.如权利要求1所述的方法,其中所述衬底是绝缘衬底。
8.如权利要求1所述的方法,其中所述衬底是半导体衬底。
9.一种形成绝缘体上硅晶体管的方法,包括:
将形成在绝缘衬底上的硅膜图案化成一种硅主体,其具有与形成在所述绝缘膜上的底表面相对的平坦的顶表面,其中所述顶表面与所述底表面分开第一距离,并且所述硅主体具有分开所述第一距离的第一和第二横向相对的侧壁;
在所述硅主体的所述顶表面上和所述硅主体的所述侧壁上形成栅极电介质层;
在所述硅主体上和所述绝缘衬底上沉积栅极材料;
图案化所述栅极材料,以在所述硅主体的所述平坦的顶表面上的所述栅极电介质层之上、并与所述硅主体的所述侧壁上的所述栅极电介质相邻形成栅极电极,所述栅极电极具有垂直于所述硅主体的所述横向相对的侧壁而延伸的横向相对的侧壁,所述栅极电极的所述横向相对的侧壁分开所述第一距离;以及
在所述硅主体中,在所述栅极电极的所述横向相对的侧壁的相对侧面上形成一对源极区和漏极区。
10.如权利要求9所述的方法,还包括在所述栅极电极的所述横向相对的侧壁的相对侧面上、但不在所述硅主体的所述横向相对的侧壁上形成一对侧壁隔离层;
在所述硅主体的所述顶表面上和所述硅主体的所述横向相对的侧壁上、并与在所述栅极电极的所述横向相对的侧壁的相对侧面上的所述一对侧壁隔离层相邻形成第二硅膜。
11.如权利要求9所述的方法,其中所述硅膜是单晶硅。
12.如权利要求11所述的方法,其中所述单晶硅膜是本征硅。
13.如权利要求9所述的方法,其中将在所述栅极电极之下的所述硅主体掺杂到第一导电性类型的第一浓度水平;以及
在所述栅极电极之下的所述半导体主体中形成具有所述第一导电性类型的第二浓度水平的halo区,其中所述第二浓度水平大于所述第一浓度水平。
14.如权利要求10所述的方法,还包括在形成于所述硅主体上的第二硅膜上形成硅化物。
15.如权利要求9所述的方法,还包括:
在所述绝缘衬底上形成第二硅主体,其具有顶表面和横向相对的侧壁;
在所述第二硅主体所述顶表面和所述第二硅主体的所述侧壁上形成第二栅极电介质层;
在所述第二硅主体的所述顶表面上的所述栅极电介质层上、并与在所述第二硅主体的所述侧壁上的所述栅极电介质层相邻形成所述栅极电极;
由所述硅膜形成将所述第一源极区与所述第二源极区连接的源极附着块;以及
由所述硅膜形成将所述第一漏极区与所述第二漏极区连接的漏极附着块。
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