CN1273695A - 半导体装置及其制造方法、电路基板和电子装置 - Google Patents
半导体装置及其制造方法、电路基板和电子装置 Download PDFInfo
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- CN1273695A CN1273695A CN99801066A CN99801066A CN1273695A CN 1273695 A CN1273695 A CN 1273695A CN 99801066 A CN99801066 A CN 99801066A CN 99801066 A CN99801066 A CN 99801066A CN 1273695 A CN1273695 A CN 1273695A
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Abstract
在半导体装置的制造方法中,准备形成了布线图形10、在除了与半导体元件20的电极22导电性地连接的部分外用保护层50覆盖的基板12,该方法包括:将各向异性导电材料16设置在布线图形10与电极22之间、且设置在从基板12的半导体元件20的安装区到保护层50上的第1工序;以及利用各向异性导电材料16粘接基板12与半导体元件20、使布线图形10与电极22导电性地导通的第2工序。
Description
技术领域
本发明涉及半导体装置及其制造方法、电路基板和电子装置。
背景技术
随着近年来的电子装置的小型化,要求适合于高密度安装的半导体装置的封装。为了适应这一情况,已开发了BGA(球状栅格阵列)及CSP(芯片比例/尺寸封装)那样的表面安装型封装。在表面安装型封装中,有时使用与半导体芯片连接的、形成了布线图形的基板。
在现有的表面安装型封装中,由于难以为了没有间隙地保护布线图形等而形成保护膜,故难以提高生产性。
本发明是为了解决该问题而进行的,其目的在于提供在可靠性和生产性方面良好的半导体装置的制造方法和利用该方法制造的半导体装置、电路基板和电子装置。
发明的公开
(1)与本发明有关的半导体装置的制造方法是利用粘接剂来连接形成了电极的半导体元件与基板的半导体装置的制造方法,其中,在上述基板上形成了布线图形,上述基板在除了与上述布线图形中的上述电极的导电性的连接部分外用保护层来覆盖,上述半导体装置的制造方法包括:
在上述布线图形与上述电极之间、且从上述基板中的上述半导体元件的安装区到上述保护层上设置上述粘接剂的第1工序;以及利用上述粘接剂粘接上述基板与上述半导体元件,使上述布线图形与上述电板导电性地导通的第2工序。
按照本发明,由于以覆盖保护层的方式来设置粘接剂,故在粘接剂与保护层之间不形成间隙,布线图形不露出,可防止其迁移现象。
(2)在该半导体装置的制造方法中,导电粒子可被分散于上述粘接剂中,利用上述导电粒子使上述布线图形与上述电极导电性地导通。
按照这一点,由于利用导电粒子使布线图形与电极导电性地导通,故可以在可靠性和生产性方面良好的方法来制造半导体装置。
(3)在该半导体装置的制造方法中,可在上述第1工序之前预先在上述半导体元件的形成了上述电极的上述面上设置上述粘接剂。
(4)在该半导体装置的制造方法中,可在上述第1工序之前预先在上述基板的形成了上述布线图形的面上设置上述粘接剂。
(5)在该半导体装置的制造方法中,上述粘接剂可以是热硬化性的粘接剂。
(6)在该半导体装置的制造方法中,在上述第1工序中,在从上述半导体元件溢出的状态下设置上述粘接剂,在上述第2工序中,在上述半导体元件与上述基板之间加热,在上述半导体元件与上述基板之间使上述粘接剂硬化,在上述第2工序后,可包括对上述粘接剂中的在上述第2工序中未结束硬化的部分加热的第3工序。
(7)在该半导体装置的制造方法中,在上述第3工序中,可利用加热夹具来加热上述粘接剂。
(8)在该半导体装置的制造方法中,也可使与上述粘接剂的脱模性高的脱模层介入到上述加热夹具与上述粘接剂之间,来加热上述粘接剂。
(9)在该半导体装置的制造方法中,也可在上述加热夹具中设置上述脱模层。
(10)在该半导体装置的制造方法中,也可在上述粘接剂上设置上述脱模层。
(11)在该半导体装置的制造方法中,在上述第3工序中,也可以非接触方式加热上述粘接剂。
(12)在该半导体装置的制造方法中,也可包括在上述基板上形成与上述布线图形连接的焊锡球时的回流工序,在上述回流工序中进行上述第3工序。
(13)在该半导体装置的制造方法中,也可包括在将除了上述半导体元件外的电子部件导电性地接合到上述布线图形上时的回流工序,在上述回流工序中进行上述第3工序。
(14)在该半导体装置的制造方法中,可在上述第2工序后,在上述粘接剂的与上述半导体元件接触的区域以外的区域中切断上述基板。
(15)在该半导体装置的制造方法中,切断上述基板的位置也可以是在上述基板的上述布线图形的端部的外侧的区域。
(16)在该半导体装置的制造方法中,也可在切断上述基板前使上述粘接剂的整体硬化,与上述基板一起切断已硬化的上述粘接剂。
(17)在该半导体装置的制造方法中,在上述第2工序中,也可使上述粘接剂绕入到上述半导体元件的侧面的至少一部分上。
按照这一点,由于粘接剂覆盖半导体元件的侧面的至少一部分,故可保护半导体元件免受机械的破坏,除此以外,可防止水分到达电极,可防止电极受到腐蚀。
(18)在该半导体装置的制造方法中,上述粘接剂也可在上述第1工序中以比上述第2工序结束后的上述半导体元件与上述基板的间隔大的厚度被设置,在上述第2工序中在上述半导体元件与上述基板之间被加压,从上述半导体元件溢出。
(19)在该半导体装置的制造方法中,上述粘接剂可含有遮光性材料。
按照这一点,由于粘接剂含有遮光性材料,故可遮住朝向半导体元件的具有电极的面的散光。由此,可防止半导体元件的误操作。
(20)在该半导体装置的制造方法中,可预先准备在除了上述半导体元件的安装区及其周边外用上述保护层覆盖的上述基板。
(21)与本发明有关的半导体装置包括:具有电极的半导体元件;形成了布线图形的基板;在除了上述布线图形中的与半导体元件的电极导电性地连接的部分外在上述基板上设置的保护层;以及粘接剂,上述粘接剂被设置在从上述半导体元件的安装区到上述保护层上,上述半导体元件的上述电极与上述布线图形导电性地导通。
按照本发明,由于以覆盖保护层的方式来设置粘接剂,故在粘接剂与保护层之间不形成间隙,布线图形不露出,可防止其迁移现象。
(22)在该半导体装置中,导电粒子可被分散于上述粘接剂中来构成各向异性导电材料。
按照这一点,由于利用各向异性导电材料使布线图形与电极导电性地导通,故在可靠性和生产性方面良好。
(23)在该半导体装置中,上述各向异性导电材料可覆盖上述布线图形的全部而被设置。
(24)在该半导体装置中,上述粘接剂也可覆盖上述半导体元件的侧面的至少一部分。
按照这一点,由于粘接剂覆盖半导体元件的侧面的至少一部分,故可保护半导体元件免受机械的破坏。此外,在半导体元件中,由于用粘接剂覆盖到离电极远的位置,故水分难以到达电极,可防止电极受到腐蚀。
(25)在该半导体装置中,上述粘接剂可含有遮光性材料。
按照这一点,由于粘接剂含有遮光性材料,故可遮住朝向半导体元件的具有电极的面的散光。由此,可防止半导体元件的误操作。
(26)在该半导体装置中,可在除了上述半导体元件的安装区及其周边外形成了上述保护层。
(27)与本发明有关的半导体装置利用上述方法来制造。
(28)在与本发明有关的电路基板中安装了上述半导体装置。
(29)与本发明有关的电子装置具有上述电路基板。
附图的简单说明
图1A-图1D是示出与第1参考形态有关的半导体装置的制造方法的图,图2A和图2B是示出第1参考形态的变形例的图,图3A和图3B是示出与第2参考形态有关的半导体装置的制造方法的图,图4A和图4B是示出与实施形态有关的半导体装置的制造方法的图,图5A和图5B是示出与第3参考形态有关的半导体装置的制造方法的图,图6是示出安装了与本实施形态有关的半导体装置的电路基板的图,图7是示出具备安装了与本实施形态有关的半导体装置的电路基板的电子装置的图。
实施发明用的最佳形态
以下,参照附图说明本发明的优选实施形态。在图5A和图5B中示出了本发明的实施形态。在本发明的实施中,可应用以下的参考形态。
(第1参考形态)
图1A~图1D是示出与第1参考形态有关的半导体装置的制造方法的图。在本参考形态中,如图1A中所示,使用在至少一个面18上形成了布线图形10的基板12。
基板12可以是柔性基板等的由有机系列材料形成的基板、金属系列基板等的由无机系列材料形成的基板、或将两者组合起来的基板中的任一种。作为柔性基板,可使用带载体(tape carrier)。在基板12的导电性高的情况下,在基板12与布线图形10之间和在通孔14的内侧、或除此以外,在与布线图形10的形成面相反的面上形成绝缘膜。
在基板12上形成了通孔14,布线图形10跨过通孔14之上而被形成。此外,作为布线图形10的一部分,在通孔14上形成了外部电极形成用的接合区(land)17。
如果准备这样的基板12,则作为粘接剂的一例,在基板12上设置各向异性导电材料16。在以下的说明中,各向异性导电材料是粘接剂的一例。各向异性导电材料16是在粘接剂(binder)中分散了导电粒子(导电性填料)的材料,也有添加分散剂的情况。可将各向异性导电材料16预先形成为片状之后粘贴在基板12上,也可以液状直接设置在基板12上。此外,可将各向异性导电材料16设置成比半导体元件20的具有电极22的面24大,但也可设置成比面24小,以通过被挤压而从面24溢出的量来设置。
或者,也可在半导体元件20的面24上以通过被挤压而从面24溢出的量来设置各向异性导电材料16。再有,即使使用不含有导电粒子的粘接剂,也能导电性地连接电极22与布线图形10。
在本参考形态中,可使用热硬化性粘接剂作为各向异性导电材料,再者,各向异性导电材料16可含有遮光性材料。作为遮光性材料,例如可使用使黑色染料或黑色颜料分散在粘接剂树脂中的材料。
作为所使用的粘接剂,可使用以环氧系列为代表例的热硬化型粘接剂,也可使用以环氧系列或丙烯酸系列为代表例的光硬化型粘接剂。再者,也可使用电子束硬化类型、热塑(热粘接)类型的粘接剂。在使用热硬化型以外的粘接剂的情况下,在以下的全部实施形态中,施加能量来代替加热或加压即可。
其次,例如在各向异性导电材料16上放置半导体元件20。详细地说,将半导体元件20的具有电极22的面24朝向各向异性导电材料16来放置半导体元件20。此外,这样来配置半导体元件20,使得电极22位于布线图形10的电极连接用的接合区(未图示)上。再有,可只在半导体元件20的两边上形成了电极22,也可在四边上形成了电极22。关于电极22,大多使用在铝焊区(pad)上设置了金或焊锡等凸起的电极,但也可使用在布线图形10一侧对上述的凸起或布线图形10进行刻蚀而作成的凸起。
利用以上的工序,各向异性导电材料16介入到半导体元件20的形成了电极22的面24与基板12的形成了布线图形10的面18之间。然后,将夹具30压在与形成了电极22的面24相反的面26上,在基板12的方向上对半导体元件20进行加压。或者,在半导体元件20与基板12之间,施加压力。作为粘接剂的一例的各向异性导电材料16,即使在被设置在半导体元件20的面24的区域内的情况下,也由于压力而从面24溢出。此外,夹具30内置了加热器32,对半导体元件20进行加热。再有,作为夹具30,如果考虑对各向异性导电材料16的已溢出的部分也打算尽可能地施加热量,则最好使用具有比半导体元件20的平面面积大的平面面积。通过这样做,热量容易施加到半导体元件20的周围。
这样,如图1B中所示,半导体元件20的电极22与布线图形10通过各向异性导电材料16的导电粒子导电性地连接。按照本参考形态,由于利用各向异性导电材料16使布线图形10与电极22导电性地导通,故可用在可靠性和生产性方面良好的方法来制造半导体装置。
此外,由于利用夹具30来加热半导体元件20,故各向异性导电材料16在与半导体元件20接触的区域中硬化。但是,在该状态下,由于在没有与半导体元件20接触的区域或离开半导体元件20的区域中,热量不能到达各向异性导电材料16上,故没有完全硬化。用以下的工序来进行该区域的硬化。
如图1C中所示,在基板12的通孔14内及其附近,设置了焊锡34。焊锡34例如可采用膏状焊锡、利用印刷法来设置。此外,也可在上述位置上放置预先形成的焊锡球。
接着,在回流(reflow)工序中加热焊锡34,如图1D中所示,形成焊锡球36。焊锡球36成为外部电极。在该回流工序中,不仅对焊锡34进行加热,也对各向异性导电材料16进行加热。利用该热量,使各向异性导电材料16的未硬化的区域也硬化了。即,在各向异性导电材料16中,没有与半导体元件20接触的区域或离开半导体元件20的区域利用形成焊锡球36用的回流工序进行硬化。
按照这样得到的半导体装置1,由于全部各向异性导电材料16已硬化,故可防止在半导体元件20的外周部处各向异性导电材料16从基板12剥落、水分侵入而引起布线图形10的迁移(migration)。此外,由于整个各向异性导电材料16硬化了,故也可防止各向异性导电材料16中含有水分。
再者,在半导体装置1中,由于利用含有遮光性材料的各向异性导电材料16来覆盖半导体元件20的具有电极22的面24,故可遮住朝向面24的散光。由此,可防止半导体元件20的误操作。
图2A和图2B是示出第1参考形态的变形例的图。在该变形例中,在与第1参考形态相同的结构中采用相同的符号,省略关于该结构和起因于该结构的效果的说明。这一点在以下的实施形态中也是同样的。
图2A中示出的工序在图1B的工序后及图1C的工序前进行。具体地说,利用加热夹具38加热各向异性导电材料16中的没有与半导体元件20接触的区域或离开半导体元件20的区域。最好设置由与作为粘接剂的一例的各向异性导电材料16的脱模性高的聚四氟乙烯构成的脱模层39,使得未硬化的各向异性导电材料16难以附着于加热夹具38上。或者,也可将脱模层39设置在作为粘接剂的一例的各向异性导电材料16上。再者,也可以不与作为粘接剂的一例的各向异性导电材料16接触的方式对其进行加热。通过这样做,可使各向异性导电材料16中的没有与半导体元件20接触的区域或离开半导体元件20的区域硬化。也可不使用夹具,而是使用能部分地进行加热的热风或光加热器。
或者,如图2B中所示,也可在图1B的工序后及图1C的工序前进行将与半导体元件20有区别的电子部件40导电性地接合到布线图形10上用的回流工序。利用该回流工序,各向异性导电材料16中的没有与半导体元件20接触的区域或离开半导体元件20的区域被加热而硬化。再有,作为电子部件40,例如有电阻器、电容器、线圈、振荡器、滤波器、温度传感器、热敏电阻、变阻器、电位器或熔断器等。
由于利用这些变形例也能使全部各向异性导电材料16硬化,故可防止各向异性导电材料16从基板12剥落、水分侵入而引起布线图形10的迁移。此外,由于整个各向异性导电材料16硬化了,故也可防止含有水分。
此外,在上述工序后,可在作为粘接剂的一例的各向异性导电材料16从半导体元件20溢出的区域中切断基板12。
在本参考形态中,叙述了使用单面布线基板作为基板12的例子,但不限于此,也可使用两面布线板或多层布线板。此时,可在通孔中不形成焊锡,而在与半导体元件放置面相反的面上设置的接合区上来形成焊锡球。此外,也可使用其它的导电性凸起来代替焊锡球。再者,也可利用引线键合来进行半导体元件与基板的连接。这些在以后的实施形态中也是同样的。
此外,在本实施形态中,不仅可使用作为热硬化性的粘接剂的一例的各向异性导电材料16,也可使用作为热塑性的粘接剂的一例的各向异性导电材料16。热塑性的粘接剂冷却后可使其硬化。或者,也可使用由紫外线等的放射线进行硬化的粘接剂。这一点在以下的实施形态中也是同样的。
(第2参考形态)
图3A和图3B是示出与第2参考形态有关的半导体装置的制造方法的图。本参考形态接着第1参考形态来进行。
即,在本参考形态中,接着图1D的工序,如图3A中所示,在用固定刃41压住的同时利用可动刃42以比半导体元件20稍大的的尺寸来切断各向异性导电材料16和基板12,得到如图3B中示出的半导体装置2。切断的装置不限于此,如果有其它的切断装置和固定装置,则也可应用。由于与各向异性导电材料16一起切断基板12,故两者的切断面为同一面,各向异性导电材料16覆盖基板12的整个面。而且,由于布线图形10不露出,故水分不到达布线图形10,可防止迁移现象。
此外,按照本参考形态,由于各向异性导电材料16被切断,故也没有必要预先以与半导体元件20相等或稍大的尺寸进行切断,没有必要准确地进行位置重合以便与半导体元件20的位置对应。
再有,本参考形态是在形成了焊锡球36之后切断各向异性导电材料16和基板12的例子,但只要是在各向异性导电材料16上至少放置了半导体元件20之后,则切断的时期可以是与焊锡球36的形成无关的任何时间。但是,各向异性导电材料16最好至少在与半导体元件20的接触区域中进行硬化。此时,可防止半导体元件20与布线图形10的位置偏移。此外,各向异性导电材料16在切断部位处与处于未硬化的状态相比,处于硬化状态的切断工序比较容易。
再有,如果切断基板12,则可一度使作为粘接剂的一例的各向异性导电材料16的整体硬化。例如,在导电性地连接半导体元件20的电极22与布线图形10时,相对于作为粘接剂的一例的各向异性导电材料16的整体,或是加热或是冷却即可。在使用热硬化性的粘接剂时,具体地说,也可使用与半导体元件20和从半导体元件20溢出的粘接剂的两者接触的夹具。或者,也可利用烘箱来加热。
(实施形态)
图4A和图4B是示出与实施形态有关的半导体装置的制造方法的图。在本实施形态中,使用第1参考形态的基板12,在基板12上形成保护层50。由于保护层50覆盖布线图形10使其不接触水分,故例如使用焊剂刻蚀剂。
在除了比将半导体元件20安装在基板12上用的区域宽的区域52之外,形成了保护层50。即,区域52比半导体元件20的具有电极22的面24大,在该区域52内,在布线图形10上形成了与半导体元件20的电极22连接用的接合区(未图示)。或者,也可至少避开与半导体元件20的电极22的导电性的连接部来形成保护层50。
在这样的基板12上,作为第1参考形态的各向异性导电材料16设置由可选择的材料构成的各向异性导电材料54(粘接剂)。再有,各向异性导电材料54不必含有遮光性材料,但如果含有遮光性材料,则可得到与第1参考形态同样的效果。
在本实施形态中,从半导体元件20的安装区到保护层50设置各向异性导电材料54。即,各向异性导电材料54在不形成保护层50的区域52中覆盖布线图形10和基板12,同时,重叠在形成保护层50的区域52的端部上而被形成。或者,也可在半导体元件20一侧设置作为粘接剂的一例的各向异性导电材料54。详细地说,可应用在第1参考形态中已说明的内容。
然后,如图4A中所示,通过夹具30在基板12的方向上将半导体元件20加压并加热。或者,至少在半导体元件20与基板12之间施加压力。这样,如图4B中所示,半导体元件20的电极22与布线图形10导电性地导通。其后,利用与图1C和图1D中示出的同样的工序,形成焊锡球,可得到半导体装置。
按照本实施形态,各向异性导电材料54不仅在不形成保护层50的区域52中形成,而且重叠在形成保护层50的区域52的端部上而被形成。因而,由于在各向异性导电材料54与保护层50之间不形成间隙,故布线图形10不露出,可防止迁移现象。
再有,在本实施形态中,最好也在从半导体元件20溢出的区域中使各向异性导电材料54硬化。该硬化的工序可应用与第1参考形态同样的工序。
(第3参考形态)
图5A和图5B是示出与第3参考形态有关的半导体装置的制造方法的图。在本参考形态中,使用第1参考形态的基板12,在基板12上设置各向异性导电材料56(粘接剂)。本参考形态与第1参考形态的不同点在于各向异性导电材料56的厚度。即,如图5A中所示,在本参考形态中,各向异性导电材料56的厚度比图1A中示出的各向异性导电材料16的厚度厚。具体地说,各向异性导电材料56的厚度比半导体元件20的具有电极22的面24与在基板12上形成的布线图形10的间隔厚。此外,各向异性导电材料56至少比半导体元件20大一些。再有,关于该厚度和大小的条件,至少满足某一方即可。
然后,如图5A中所示,通过夹具30在基板12的方向上将半导体元件20加压并加热。如果这样做,则如图5B中所示,各向异性导电材料56绕入到半导体元件20的侧面28的一部分或全部上。其后,利用与图1C和图1D中示出的同样的工序,形成焊锡球,可得到半导体装置。
按照本参考形态,由于半导体元件20的侧面28的至少一部分被各向异性导电材料56覆盖,故可保护半导体元件20免受机械的破坏,除此以外,由于各向异性导电材料56覆盖到离电极22远的位置,故可防止电极22等受到腐蚀。
上述的实施形态以FDB(倒装键合)的CSP(芯片比例/尺寸封装)为中心进行了记述,但即使在应用了FDB的半导体装置、例如应用了COF(在膜上的芯片)及COB(在板上的芯片)的半导体装置等中,也可应用本发明。
在图6中,示出了安装了利用与上述的实施形态有关的方法制造的半导体装置1100的电路基板1000。一般使用例如玻璃环氧基板等的有机系列基板作为电路基板1000。在电路基板1000上以成为所希望的电路的方式形成了例如由铜构成的布线图形。而且,通过以机械方式连接布线图形与半导体装置1100来谋求它们的导电性的导通。
再有,由于可使半导体装置1100的安装面积减小到用裸芯片安装的面积,故如果在电子装置中使用该电路基板1000,就可谋求电子装置本身的小型化。此外,在同一面积内可确保更大的安装空间,也可谋求高功能化。
而且,作为具备该电路基板1000的电子装置,在图7中示出了笔记本型个人计算机1200。
再有,也可将本发明应用于各种面安装用的电子部件,不管其是有源部件还是无源部件。作为电子部件,例如有电阻器、电容器、线圈、振荡器、滤波器、温度传感器、热敏电阻、变阻器、电位器或熔断器等。
Claims (29)
1.一种半导体装置的制造方法,该方法是利用粘接剂来连接形成了电极的半导体元件与基板的半导体装置的制造方法,其中,在上述基板上形成了布线图形,上述基板在除了与上述布线图形中的上述电极的导电性的连接部分外用保护层来覆盖,其特征在于,包括:
在上述布线图形与上述电极之间、且从上述基板中的上述半导体元件的安装区到上述保护层上设置上述粘接剂的第1工序;以及
利用上述粘接剂粘接上述基板与上述半导体元件,使上述布线图形与上述电极导电性地导通的第2工序。
2.如权利要求1中所述的半导体装置的制造方法,其特征在于:
导电粒子被分散于上述粘接剂中,利用上述导电粒子使上述布线图形与上述电极导电性地导通。
3.如权利要求1中所述的半导体装置的制造方法,其特征在于:
在上述第1工序之前预先在上述半导体元件的形成了上述电极的上述面上设置上述粘接剂。
4.如权利要求1中所述的半导体装置的制造方法,其特征在于:
在上述第1工序之前预先在上述基板的形成了上述布线图形的面上设置上述粘接剂。
5.如权利要求1中所述的半导体装置的制造方法,其特征在于:
上述粘接剂是热硬化性的粘接剂。
6.如权利要求5中所述的半导体装置的制造方法,其特征在于:
在上述第1工序中,在从上述半导体元件溢出的状态下设置上述粘接剂,
在上述第2工序中,在上述半导体元件与上述基板之间加热,在上述半导体元件与上述基板之间使上述粘接剂硬化,
在上述第2工序后,包括对上述粘接剂中的在上述第2工序中未结束硬化的部分加热的第3工序。
7.如权利要求6中所述的半导体装置的制造方法,其特征在于:
在上述第3工序中,利用加热夹具来加热上述粘接剂。
8.如权利要求7中所述的半导体装置的制造方法,其特征在于:
使与上述粘接剂的脱模性高的脱模层介入到上述加热夹具与上述粘接剂之间,来加热上述粘接剂。
9.如权利要求8中所述的半导体装置的制造方法,其特征在于:
在上述加热夹具中设置上述脱模层。
10.如权利要求8中所述的半导体装置的制造方法,其特征在于:
在上述粘接剂上设置上述脱模层。
11.如权利要求6中所述的半导体装置的制造方法,其特征在于:
在上述第3工序中,以非接触方式加热上述粘接剂。
12.如权利要求6中所述的半导体装置的制造方法,其特征在于:
包括在上述基板上形成与上述布线图形连接的焊锡球时的回流工序,
在上述回流工序中进行上述第3工序。
13.如权利要求6中所述的半导体装置的制造方法,其特征在于:
包括在将除了上述半导体元件外的电子部件导电性地接合到上述布线图形上时的回流工序,
在上述回流工序中进行上述第3工序。
14.如权利要求1中所述的半导体装置的制造方法,其特征在于:
在上述第2工序后,在上述粘接剂的与上述半导体元件接触的区域以外的区域中切断上述基板。
15.如权利要求14中所述的半导体装置的制造方法,其特征在于:
切断上述基板的位置是在上述基板的上述布线图形的端部的外侧的区域。
16.如权利要求14中所述的半导体装置的制造方法,其特征在于:
在切断上述基板前使上述粘接剂的整体硬化,与上述基板一起切断已硬化的上述粘接剂。
17.如权利要求1中所述的半导体装置的制造方法,其特征在于:
在上述第2工序中,使上述粘接剂绕入到上述半导体元件的侧面的至少一部分上。
18.如权利要求17中所述的半导体装置的制造方法,其特征在于:
上述粘接剂在上述第1工序中以比上述第2工序结束后的上述半导体元件与上述基板的间隔大的厚度被设置,在上述第2工序中在上述半导体元件与上述基板之间被加压,从上述半导体元件溢出。
19.如权利要求1中所述的半导体装置的制造方法,其特征在于:
上述粘接剂含有遮光性材料。
20.如权利要求1中所述的半导体装置的制造方法,其特征在于:
预先准备在除了上述半导体元件的安装区及其周边外用上述保护层覆盖的上述基板。
21.一种半导体装置,其特征在于:
包括:
具有电极的半导体元件;
形成了布线图形的基板;
在除了上述布线图形中的与半导体元件的电极导电性地连接的部分外在上述基板上被设置的保护层;以及
粘接剂,
上述粘接剂被设置在从上述半导体元件的安装区到上述保护层上,
上述半导体元件的上述电极与上述布线图形导电性地导通。
22.如权利要求21中所述的半导体装置,其特征在于:
导电粒子被分散于上述粘接剂中来构成各向异性导电材料。
23.如权利要求22中所述的半导体装置,其特征在于:
上述各向异性导电材料覆盖上述布线图形的全部而被设置。
24.如权利要求21中所述的半导体装置,其特征在于:
上述粘接剂覆盖上述半导体元件的侧面的至少一部分。
25.如权利要求21中所述的半导体装置,其特征在于:
上述粘接剂含有遮光性材料。
26.如权利要求21中所述的半导体装置,其特征在于:
在除了上述半导体元件的安装区及其周边外形成了上述保护层。
27.一种半导体装置,其特征在于:
利用权利要求1至权利要求20的任一项中所述的方法来制造。
28.一种电路基板,其特征在于:
安装了权利要求21至权利要求26的任一项中所述的半导体装置。
29.一种电子装置,其特征在于:
具有权利要求28中所述的电路基板。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1316579C (zh) * | 2003-06-27 | 2007-05-16 | 精工爱普生株式会社 | 半导体装置及其制造方法 |
CN100431833C (zh) * | 2002-08-09 | 2008-11-12 | 日东电工株式会社 | 用于透明导电基板的表面保护膜和具有表面保护膜的透明导电基板 |
CN108427520A (zh) * | 2018-04-02 | 2018-08-21 | 业成科技(成都)有限公司 | 触控面板与其制造方法 |
Families Citing this family (71)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3815149B2 (ja) * | 1999-11-04 | 2006-08-30 | セイコーエプソン株式会社 | 部品実装方法および電気光学装置の製造方法 |
US7102892B2 (en) * | 2000-03-13 | 2006-09-05 | Legacy Electronics, Inc. | Modular integrated circuit chip carrier |
US6487078B2 (en) * | 2000-03-13 | 2002-11-26 | Legacy Electronics, Inc. | Electronic module having a three dimensional array of carrier-mounted integrated circuit packages |
US6713854B1 (en) | 2000-10-16 | 2004-03-30 | Legacy Electronics, Inc | Electronic circuit module with a carrier having a mounting pad array |
DE10019443A1 (de) * | 2000-04-19 | 2001-10-31 | Texas Instruments Deutschland | Vorrichtung zum Befestigen eines Halbleiter-Chips auf einem Chip-Träger |
US6395326B1 (en) * | 2000-05-31 | 2002-05-28 | Advanced Cardiovascular Systems, Inc. | Apparatus and method for depositing a coating onto a surface of a prosthesis |
DE10046296C2 (de) * | 2000-07-17 | 2002-10-10 | Infineon Technologies Ag | Elektronisches Chipbauteil mit einer integrierten Schaltung und Verfahren zu seiner Herstellung |
JP2002076589A (ja) * | 2000-08-31 | 2002-03-15 | Hitachi Ltd | 電子装置及びその製造方法 |
US7337522B2 (en) * | 2000-10-16 | 2008-03-04 | Legacy Electronics, Inc. | Method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips |
JP3653460B2 (ja) * | 2000-10-26 | 2005-05-25 | 三洋電機株式会社 | 半導体モジュールおよびその製造方法 |
EP1378152A4 (en) * | 2001-03-14 | 2006-02-01 | Legacy Electronics Inc | METHOD AND DEVICE FOR PREPARING A PCB WITH A THREE-DIMENSIONAL ARRAY OF SEMICONDUCTOR CHIPS USED ON THE SURFACE |
WO2002093637A2 (en) * | 2001-05-17 | 2002-11-21 | Koninklijke Philips Electronics N.V. | Product comprising a substrate and a chip attached to the substrate |
JP2002353369A (ja) * | 2001-05-28 | 2002-12-06 | Sharp Corp | 半導体パッケージおよびその製造方法 |
US20030059520A1 (en) | 2001-09-27 | 2003-03-27 | Yung-Ming Chen | Apparatus for regulating temperature of a composition and a method of coating implantable devices |
JP2004134646A (ja) * | 2002-10-11 | 2004-04-30 | Seiko Epson Corp | バンプ付き半導体素子の実装構造、バンプ付き半導体素子の実装方法、及び電気光学装置、並びに電子機器 |
US20050012225A1 (en) * | 2002-11-15 | 2005-01-20 | Choi Seung-Yong | Wafer-level chip scale package and method for fabricating and using the same |
US7338557B1 (en) * | 2002-12-17 | 2008-03-04 | Advanced Cardiovascular Systems, Inc. | Nozzle for use in coating a stent |
KR100510518B1 (ko) * | 2003-01-30 | 2005-08-26 | 삼성전자주식회사 | 반도체 장치 및 반도체 장치의 패키지 방법 |
US7087115B1 (en) * | 2003-02-13 | 2006-08-08 | Advanced Cardiovascular Systems, Inc. | Nozzle and method for use in coating a stent |
TW587325B (en) * | 2003-03-05 | 2004-05-11 | Advanced Semiconductor Eng | Semiconductor chip package and method for manufacturing the same |
US7104224B2 (en) * | 2003-03-25 | 2006-09-12 | Plasmadrive, Inc. | System for improving the fuel efficiency of an engine |
JP4597972B2 (ja) * | 2003-03-31 | 2010-12-15 | 東京エレクトロン株式会社 | 処理部材上に隣接するコーティングを接合する方法。 |
US7341630B1 (en) * | 2003-06-26 | 2008-03-11 | Advanced Cardiovascular Systems, Inc. | Stent coating system |
US7381361B2 (en) | 2003-06-26 | 2008-06-03 | Intel Corporation | Fabricating structures in micro-fluidic channels based on hydrodynamic focusing |
US7294533B2 (en) * | 2003-06-30 | 2007-11-13 | Intel Corporation | Mold compound cap in a flip chip multi-matrix array package and process of making same |
JP3921459B2 (ja) * | 2003-07-11 | 2007-05-30 | ソニーケミカル&インフォメーションデバイス株式会社 | 電気部品の実装方法及び実装装置 |
US7672872B2 (en) * | 2003-08-22 | 2010-03-02 | Smurfit-Stone Container Enterprises, Inc. | Point-of-purchase display with RFID inventory control |
US7198675B2 (en) | 2003-09-30 | 2007-04-03 | Advanced Cardiovascular Systems | Stent mandrel fixture and method for selectively coating surfaces of a stent |
US6983884B2 (en) * | 2004-02-19 | 2006-01-10 | Neoteric Technology, Limited | Method and apparatus for monitoring transfusion of blood |
JP3943096B2 (ja) * | 2004-03-31 | 2007-07-11 | シャープ株式会社 | 半導体装置、及びその電気的検査方法、並びにそれを備えた電子機器 |
JP4426900B2 (ja) * | 2004-05-10 | 2010-03-03 | 三井金属鉱業株式会社 | プリント配線基板、その製造方法および半導体装置 |
JP4737370B2 (ja) * | 2004-10-29 | 2011-07-27 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
KR100610144B1 (ko) * | 2004-11-03 | 2006-08-09 | 삼성전자주식회사 | 플립 칩 조립 구조를 가지는 칩-온-보드 패키지의 제조 방법 |
US7632307B2 (en) * | 2004-12-16 | 2009-12-15 | Advanced Cardiovascular Systems, Inc. | Abluminal, multilayer coating constructs for drug-delivery stents |
WO2006076381A2 (en) | 2005-01-12 | 2006-07-20 | Legacy Electronics, Inc. | Radial circuit board, system, and methods |
EP1686512A1 (fr) * | 2005-02-01 | 2006-08-02 | NagraID S.A. | Procédé de placement d'un ensemble électronique sur un substrat et dispositif de placement d'un tel ensemble |
US7785932B2 (en) * | 2005-02-01 | 2010-08-31 | Nagraid S.A. | Placement method of an electronic module on a substrate and device produced by said method |
US8119458B2 (en) * | 2005-02-01 | 2012-02-21 | Nagraid S.A. | Placement method of an electronic module on a substrate |
DE102005013500A1 (de) * | 2005-03-23 | 2006-10-05 | Infineon Technologies Ag | Halbleiteranordnung und Verfahren zum Herstellen einer Halbleiteranordnung |
JP2006286798A (ja) * | 2005-03-31 | 2006-10-19 | Toray Eng Co Ltd | 実装方法および装置 |
JP4544143B2 (ja) | 2005-06-17 | 2010-09-15 | セイコーエプソン株式会社 | 半導体装置の製造方法、半導体装置、回路基板及び電子機器 |
CN100433250C (zh) * | 2005-06-17 | 2008-11-12 | 精工爱普生株式会社 | 半导体装置制造方法、半导体装置、电路基板 |
JP2007123413A (ja) * | 2005-10-26 | 2007-05-17 | Elpida Memory Inc | 半導体装置の製造方法 |
KR100753393B1 (ko) * | 2005-11-03 | 2007-09-13 | 아이엔지플렉스(주) | 박판적층 연성회로기판 및 그 제조방법 |
US20070117268A1 (en) * | 2005-11-23 | 2007-05-24 | Baker Hughes, Inc. | Ball grid attachment |
US7867547B2 (en) | 2005-12-19 | 2011-01-11 | Advanced Cardiovascular Systems, Inc. | Selectively coating luminal surfaces of stents |
TW200740320A (en) * | 2006-04-04 | 2007-10-16 | Chicony Electronic Co Ltd | Method of adhering electronic element and apparatus using the method |
JP2007302864A (ja) * | 2006-04-11 | 2007-11-22 | Hitachi Chem Co Ltd | 接着フィルム、これを用いた回路部材の接続構造 |
US8003156B2 (en) | 2006-05-04 | 2011-08-23 | Advanced Cardiovascular Systems, Inc. | Rotatable support elements for stents |
US8603530B2 (en) | 2006-06-14 | 2013-12-10 | Abbott Cardiovascular Systems Inc. | Nanoshell therapy |
US8048448B2 (en) | 2006-06-15 | 2011-11-01 | Abbott Cardiovascular Systems Inc. | Nanoshells for drug delivery |
US8017237B2 (en) | 2006-06-23 | 2011-09-13 | Abbott Cardiovascular Systems, Inc. | Nanoshells on polymers |
JP5020629B2 (ja) * | 2006-12-28 | 2012-09-05 | パナソニック株式会社 | 電子部品の接続方法 |
JP5029026B2 (ja) * | 2007-01-18 | 2012-09-19 | 富士通株式会社 | 電子装置の製造方法 |
KR100891330B1 (ko) * | 2007-02-21 | 2009-03-31 | 삼성전자주식회사 | 반도체 패키지 장치와, 반도체 패키지의 제조방법과,반도체 패키지 장치를 갖는 카드 장치 및 반도체 패키지장치를 갖는 카드 장치의 제조 방법 |
US8048441B2 (en) | 2007-06-25 | 2011-11-01 | Abbott Cardiovascular Systems, Inc. | Nanobead releasing medical devices |
KR20090041756A (ko) * | 2007-10-24 | 2009-04-29 | 삼성전자주식회사 | 접착층을 갖는 프린트 배선 기판 및 이를 이용한 반도체패키지 |
CN101940075A (zh) * | 2008-04-03 | 2011-01-05 | 夏普株式会社 | 配线基板和使用了该配线基板的半导体装置 |
WO2009154464A1 (en) * | 2008-06-20 | 2009-12-23 | Polymer Vision Limited | An integrated circuit comprising light absorbing adhesive |
FR2943849B1 (fr) * | 2009-03-31 | 2011-08-26 | St Microelectronics Grenoble 2 | Procede de realisation de boitiers semi-conducteurs et boitier semi-conducteur |
JP2010239022A (ja) * | 2009-03-31 | 2010-10-21 | Mitsui Mining & Smelting Co Ltd | フレキシブルプリント配線基板及びこれを用いた半導体装置 |
JP5533199B2 (ja) * | 2010-04-28 | 2014-06-25 | ソニー株式会社 | 素子の基板実装方法、および、その基板実装構造 |
JP5066231B2 (ja) * | 2010-07-28 | 2012-11-07 | 日東電工株式会社 | フリップチップ型半導体裏面用フィルム、短冊状半導体裏面用フィルムの製造方法、及び、フリップチップ型半導体装置 |
TWI453872B (zh) * | 2011-06-23 | 2014-09-21 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
US9839143B2 (en) * | 2012-04-10 | 2017-12-05 | Panasonic Intellectual Property Management Co., Ltd. | Electrode joining method, production method of electrode joined structure |
US10522444B2 (en) * | 2013-03-11 | 2019-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Surface treatment method and apparatus for semiconductor packaging |
WO2015131185A1 (en) * | 2014-02-28 | 2015-09-03 | Intellipaper, Llc | Integrated circuitry and methods for manufacturing same |
DE102015112023B3 (de) * | 2015-07-23 | 2016-09-01 | Infineon Technologies Ag | Verfahren zum positionieren eines halbleiterchips auf einem träger und verfahren zum stoffschlüssigen verbinden eines halbleiterchips mit einem träger |
US10249515B2 (en) * | 2016-04-01 | 2019-04-02 | Intel Corporation | Electronic device package |
EP3471135A4 (en) * | 2016-06-08 | 2019-05-01 | Fuji Corporation | CIRCUIT FORMING METHOD |
CN113571430A (zh) * | 2020-04-28 | 2021-10-29 | 西部数据技术公司 | 具有减小的底部填充面积的倒装芯片封装体 |
Family Cites Families (77)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5650546A (en) * | 1979-09-29 | 1981-05-07 | Sharp Corp | Semiconductor device |
JPS61156239A (ja) | 1984-12-28 | 1986-07-15 | Canon Inc | 閃光撮影装置 |
JPS61156239U (zh) * | 1985-03-19 | 1986-09-27 | ||
JPS62190342U (zh) * | 1986-05-26 | 1987-12-03 | ||
US4749120A (en) * | 1986-12-18 | 1988-06-07 | Matsushita Electric Industrial Co., Ltd. | Method of connecting a semiconductor device to a wiring board |
US4811081A (en) * | 1987-03-23 | 1989-03-07 | Motorola, Inc. | Semiconductor die bonding with conductive adhesive |
JPH01129431A (ja) * | 1987-11-16 | 1989-05-22 | Sharp Corp | 半導体チップ実装方式 |
JPH0715087B2 (ja) | 1988-07-21 | 1995-02-22 | リンテック株式会社 | 粘接着テープおよびその使用方法 |
JP2780293B2 (ja) | 1988-12-19 | 1998-07-30 | 松下電器産業株式会社 | 半導体装置 |
US5115545A (en) * | 1989-03-28 | 1992-05-26 | Matsushita Electric Industrial Co., Ltd. | Apparatus for connecting semiconductor devices to wiring boards |
JPH0521655A (ja) * | 1990-11-28 | 1993-01-29 | Mitsubishi Electric Corp | 半導体装置および半導体装置用パツケージ |
US5128746A (en) * | 1990-09-27 | 1992-07-07 | Motorola, Inc. | Adhesive and encapsulant material with fluxing properties |
US5136365A (en) * | 1990-09-27 | 1992-08-04 | Motorola, Inc. | Anisotropic conductive adhesive and encapsulant material |
JPH04292803A (ja) * | 1991-03-20 | 1992-10-16 | Hitachi Ltd | 異方導電性フィルム |
JP2722857B2 (ja) | 1991-04-30 | 1998-03-09 | 日本ビクター株式会社 | レンズ板の製作方法 |
JP2702839B2 (ja) * | 1991-11-20 | 1998-01-26 | シャープ株式会社 | 配線基板の電極構造 |
US5318651A (en) * | 1991-11-27 | 1994-06-07 | Nec Corporation | Method of bonding circuit boards |
JP3050345B2 (ja) | 1992-06-29 | 2000-06-12 | 東京応化工業株式会社 | 集積回路素子の接続方法 |
JP2678958B2 (ja) * | 1992-03-02 | 1997-11-19 | カシオ計算機株式会社 | フィルム配線基板およびその製造方法 |
US5532101A (en) * | 1992-06-15 | 1996-07-02 | Canon Kabushiki Kaisha | Image forming method |
US5535101A (en) * | 1992-11-03 | 1996-07-09 | Motorola, Inc. | Leadless integrated circuit package |
WO1994018701A1 (en) * | 1993-02-05 | 1994-08-18 | W.L. Gore & Associates, Inc. | Stress-resistant semiconductor chip-circuit board interconnect |
JPH0749413A (ja) | 1993-08-05 | 1995-02-21 | Toray Ind Inc | カラーフィルタの製造方法 |
KR0171438B1 (ko) * | 1993-09-29 | 1999-10-15 | 모리시따 요오이찌 | 반도체 장치를 회로 기판상에 장착하는 방법 및 반도체 장치가 장착된 회로 기판 |
JPH07225391A (ja) | 1994-02-14 | 1995-08-22 | Toshiba Corp | 液晶表示モジュール |
JPH07312377A (ja) | 1994-05-19 | 1995-11-28 | Fujitsu Ltd | 半導体チップの実装方法と実装装置 |
US5677246A (en) * | 1994-11-29 | 1997-10-14 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor devices |
US5864178A (en) * | 1995-01-12 | 1999-01-26 | Kabushiki Kaisha Toshiba | Semiconductor device with improved encapsulating resin |
KR0181615B1 (ko) * | 1995-01-30 | 1999-04-15 | 모리시다 요이치 | 반도체 장치의 실장체, 그 실장방법 및 실장용 밀봉재 |
CN1123067C (zh) * | 1995-05-22 | 2003-10-01 | 日立化成工业株式会社 | 具有与布线基板电连接的半导体芯片的半导体器件 |
ID19376A (id) | 1995-06-12 | 1998-07-09 | Matsushita Electric Ind Co Ltd | Paket unit semikonduktor, metode pemaketan unit semikonduktor, dan bahan pengkapsul untuk penggunaan dalam pemaketan unit semikonduktor (pecahan dari p-961658) |
US5578527A (en) | 1995-06-23 | 1996-11-26 | Industrial Technology Research Institute | Connection construction and method of manufacturing the same |
US5627405A (en) * | 1995-07-17 | 1997-05-06 | National Semiconductor Corporation | Integrated circuit assembly incorporating an anisotropic elecctrically conductive layer |
JP3435925B2 (ja) * | 1995-08-25 | 2003-08-11 | ソニー株式会社 | 半導体装置 |
JP2970491B2 (ja) * | 1995-09-20 | 1999-11-02 | ソニー株式会社 | 半導体パッケージ及びその製造方法 |
WO1997016848A1 (fr) * | 1995-10-31 | 1997-05-09 | Ibiden Co., Ltd. | Module de composant electronique et son procede de fabrication |
JPH09219579A (ja) | 1996-02-13 | 1997-08-19 | Oki Electric Ind Co Ltd | 電子部品の接続方法及び接続装置 |
JP2806348B2 (ja) * | 1996-03-08 | 1998-09-30 | 日本電気株式会社 | 半導体素子の実装構造及びその製造方法 |
JP2828021B2 (ja) * | 1996-04-22 | 1998-11-25 | 日本電気株式会社 | ベアチップ実装構造及び製造方法 |
EP0807980B1 (en) | 1996-05-17 | 2006-06-21 | Canon Kabushiki Kaisha | Photovoltaic device and process for the production thereof |
JP2891184B2 (ja) * | 1996-06-13 | 1999-05-17 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JPH104126A (ja) | 1996-06-14 | 1998-01-06 | Sony Corp | 実装基板、電子部品実装方法及び半導体装置 |
JPH104122A (ja) | 1996-06-14 | 1998-01-06 | Hitachi Ltd | 半導体装置 |
JP3261981B2 (ja) * | 1996-06-17 | 2002-03-04 | 松下電器産業株式会社 | バンプ付きワークのボンディング方法およびボンディング構造 |
JPH1084014A (ja) | 1996-07-19 | 1998-03-31 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法 |
JPH1041615A (ja) * | 1996-07-19 | 1998-02-13 | Matsushita Electric Ind Co Ltd | 半導体チップ実装用基板、及び半導体チップの実装方法 |
JPH1041694A (ja) * | 1996-07-25 | 1998-02-13 | Sharp Corp | 半導体素子の基板実装構造及びその実装方法 |
JP3928753B2 (ja) * | 1996-08-06 | 2007-06-13 | 日立化成工業株式会社 | マルチチップ実装法、および接着剤付チップの製造方法 |
US6020047A (en) | 1996-09-04 | 2000-02-01 | Kimberly-Clark Worldwide, Inc. | Polymer films having a printed self-assembling monolayer |
JPH1098076A (ja) * | 1996-09-24 | 1998-04-14 | Oki Electric Ind Co Ltd | 半導体素子の実装方法 |
JPH10116855A (ja) * | 1996-10-09 | 1998-05-06 | Oki Electric Ind Co Ltd | 半導体部品の実装装置および実装方法 |
JPH10125725A (ja) * | 1996-10-18 | 1998-05-15 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2800806B2 (ja) | 1996-10-31 | 1998-09-21 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JPH10168411A (ja) | 1996-12-06 | 1998-06-23 | Seiko Epson Corp | 異方性導電接着剤、液晶表示装置及び電子機器 |
JPH10173003A (ja) * | 1996-12-13 | 1998-06-26 | Sharp Corp | 半導体装置とその製造方法およびフィルムキャリアテープとその製造方法 |
US5814401A (en) * | 1997-02-04 | 1998-09-29 | Motorola, Inc. | Selectively filled adhesive film containing a fluxing agent |
AUPO515297A0 (en) | 1997-02-19 | 1997-04-11 | Future Fibre Technologies Pty Ltd | A method of providing in-situ chirped gratings in waveguides and waveguides made by that method |
TW442693B (en) * | 1997-02-24 | 2001-06-23 | Seiko Epson Corp | Color filter and its manufacturing method |
JPH10270496A (ja) * | 1997-03-27 | 1998-10-09 | Hitachi Ltd | 電子装置、情報処理装置、半導体装置並びに半導体チップの実装方法 |
US5783465A (en) * | 1997-04-03 | 1998-07-21 | Lucent Technologies Inc. | Compliant bump technology |
US6077382A (en) * | 1997-05-09 | 2000-06-20 | Citizen Watch Co., Ltd | Mounting method of semiconductor chip |
US6175345B1 (en) | 1997-06-02 | 2001-01-16 | Canon Kabushiki Kaisha | Electroluminescence device, electroluminescence apparatus, and production methods thereof |
EP0993039B1 (en) * | 1997-06-26 | 2006-08-30 | Hitachi Chemical Company, Ltd. | Substrate for mounting semiconductor chips |
US6407461B1 (en) * | 1997-06-27 | 2002-06-18 | International Business Machines Corporation | Injection molded integrated circuit chip assembly |
JPH1167795A (ja) * | 1997-08-08 | 1999-03-09 | Nec Corp | 半導体チップ搭載装置及び半導体チップ搭載方法並びに半導体装置 |
JPH1167979A (ja) * | 1997-08-13 | 1999-03-09 | Citizen Watch Co Ltd | フリップチップ半導体パッケージの実装構造及びその製造方法 |
US6353182B1 (en) * | 1997-08-18 | 2002-03-05 | International Business Machines Corporation | Proper choice of the encapsulant volumetric CTE for different PGBA substrates |
US6049124A (en) * | 1997-12-10 | 2000-04-11 | Intel Corporation | Semiconductor package |
KR100352865B1 (ko) * | 1998-04-07 | 2002-09-16 | 신꼬오덴기 고교 가부시키가이샤 | 반도체 장치 및 그 제조방법 |
US6157085A (en) * | 1998-04-07 | 2000-12-05 | Citizen Watch Co., Ltd. | Semiconductor device for preventing exfoliation from occurring between a semiconductor chip and a resin substrate |
JP2000012609A (ja) * | 1998-06-17 | 2000-01-14 | Shinko Electric Ind Co Ltd | 回路基板への半導体チップの実装方法 |
JP2000022329A (ja) * | 1998-06-29 | 2000-01-21 | Toshiba Corp | 配線基板および電子ユニットおよび電子部品実装方法 |
JP3278055B2 (ja) * | 1998-06-30 | 2002-04-30 | セイコーインスツルメンツ株式会社 | 電子回路装置 |
JP3951462B2 (ja) | 1998-06-30 | 2007-08-01 | カシオ計算機株式会社 | 電子部品実装体及びその製造方法 |
KR100629923B1 (ko) | 1998-09-30 | 2006-09-29 | 돗빤호무즈가부시기가이샤 | 도전성페이스트와 도전성페이스트의 경화방법, 및 도전성페이스트를 이용한 비접촉형 데이터송수신체용 안테나의 형성방법과, 비접촉형 데이터송수신체 |
US6040631A (en) * | 1999-01-27 | 2000-03-21 | International Business Machines Corporation | Method of improved cavity BGA circuit package |
US6225704B1 (en) * | 1999-02-12 | 2001-05-01 | Shin-Etsu Chemical Co., Ltd. | Flip-chip type semiconductor device |
-
1999
- 1999-06-25 US US09/486,317 patent/US6462284B1/en not_active Expired - Lifetime
- 1999-06-25 US US09/486,561 patent/US6995476B2/en not_active Expired - Fee Related
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100431833C (zh) * | 2002-08-09 | 2008-11-12 | 日东电工株式会社 | 用于透明导电基板的表面保护膜和具有表面保护膜的透明导电基板 |
CN1316579C (zh) * | 2003-06-27 | 2007-05-16 | 精工爱普生株式会社 | 半导体装置及其制造方法 |
CN108427520A (zh) * | 2018-04-02 | 2018-08-21 | 业成科技(成都)有限公司 | 触控面板与其制造方法 |
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