CN1251317C - 多栅极晶体管的结构及其制造方法 - Google Patents
多栅极晶体管的结构及其制造方法 Download PDFInfo
- Publication number
- CN1251317C CN1251317C CN03153008.7A CN03153008A CN1251317C CN 1251317 C CN1251317 C CN 1251317C CN 03153008 A CN03153008 A CN 03153008A CN 1251317 C CN1251317 C CN 1251317C
- Authority
- CN
- China
- Prior art keywords
- semiconductor fin
- transistor according
- shaped body
- gated transistor
- manufacture method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 76
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 20
- 238000009413 insulation Methods 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims description 50
- 230000004888 barrier function Effects 0.000 claims description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 11
- 230000003628 erosive effect Effects 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000009499 grossing Methods 0.000 claims description 9
- 229910021332 silicide Inorganic materials 0.000 claims description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 150000004767 nitrides Chemical group 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 10
- 230000012447 hatching Effects 0.000 description 10
- 239000003989 dielectric material Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 7
- 230000006872 improvement Effects 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005470 impregnation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 230000001550 time effect Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- BRGOCSWOKBOIOJ-UHFFFAOYSA-N N.[O-2].[Hf+4] Chemical compound N.[O-2].[Hf+4] BRGOCSWOKBOIOJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052716 thallium Inorganic materials 0.000 description 1
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
- H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
Abstract
本发明提供一种多栅极晶体管的结构及其制造方法，此结构包括一垂直半导体鳍状体、一栅极介电层、一栅极电极与一源极与一漏极。半导体鳍状体位于一衬底上方，衬底包括覆盖于一蚀刻终止层上方的一第一绝缘层，第一绝缘层在半导体鳍状体底部形成一底切，栅极介电层位于半导体鳍状体表面，栅极电极位于栅极介电层表面，而源极与漏极分别座落于栅极电极两侧，并位于半导体鳍状体中。
Description
技术领域
本发明涉及一种栅极晶体管的结构及其制造方法，特别涉及一种多栅极(multiple-gate)晶体管的结构及其制造方法，此结构对于晶体管的开或关状态具有更佳的控制能力，还能抑制短沟道效应(short channel effect)。
背景技术
数十年来金氧半场效应晶体管(metal-oxide-semiconductor field effecttransistor，MOSFET)不断向缩小尺寸的趋势发展，这是为了增加速度、提高组件集成度与降低集成电路的成本。当栅极宽度不断缩短时，意味着源极与漏极对于信道(channel)的电位所造成的影响程度渐渐增加，因此，当栅极宽度缩短至某一程度以下时，栅极上所施加的电压实质上已无法控制信道的开或关状态，这种因为缩短栅极宽度所衍生的问题就是“短沟道效应”。传统上用来解决短沟道效应的方式包括增加半导体衬底本体的掺杂浓度、减少栅极氧化层厚度与使用浅源/漏极接合。然而，当栅极宽度缩短至50nm以下时，上述方式已渐渐难以抑制短沟道效应，渐渐取而代之的是形成多栅极的晶体管结构，例如双栅极或三栅极的晶体管结构，多栅极的晶体管结构可改善栅极与信道间的电容耦合效果、增加栅极对信道电位的控制能力、抑制短沟道效应与使晶体管尺寸往不断缩小趋势发展。
请同时参照图1A、图1B，图1A为现有技术的双栅极晶体管结构的上视图，图1B为沿图1A中1B-1B剖面线的剖面结构示意图。现有双栅极晶体管是先提供表面具有一绝缘层11的硅衬底10，然后以蚀刻遮罩14定义并形成此半导体鳍状体13，再在半导体鳍状体13侧壁形成栅极介电层12，最后，在栅极介电层12表面形成栅极电极15。此结构是在半导体鳍状体13两对向侧壁处形成两栅极，因此为一双栅极晶体管。
请同时参照图2A、图2B，图2A为现有技术的三栅极晶体管结构的上视图，图2B为沿图2A中2B-2B剖面线的剖面结构示意图。现有三栅极晶体管是先提供在表面具有一绝缘层11的硅衬底10，然后以蚀刻遮罩(未显示于图中)定义并形成此半导体鳍状体13，去除蚀刻遮罩后，再在半导体鳍状体13侧壁形成栅极介电层12，最后，在栅极介电层12表面形成栅极电极15。此结构是在半导体鳍状体13顶部表面与两对向侧壁处形成有三个栅极，因此为一三栅极晶体管。对于晶体管的开或关状态，因为三栅极晶体管比双栅极晶体管多形成一栅极，因此三栅极晶体管比双栅极晶体管有更佳的控制能力，还能抑制短沟道效应，然而，无论是双栅极晶体管还是三栅极晶体管的结构，对于控制晶体管的开或关状态而言，仍有改良空间。
发明内容
为改进现有技术的缺陷，本发明的目的是提供一种双栅极晶体管的结构及其制造方法，此结构对于晶体管的开或关状态具有更佳的控制能力。
本发明的另一目的就是提供一种三栅极晶体管的结构及其制造方法，此结构对于晶体管的开或关状态具有更佳的控制能力。
根据上述目的，本发明一方面提供一种多栅极晶体管的制造方法，此制造方法先形成一半导体层于一绝缘堆栈层上方，绝缘堆栈层包括覆盖于一蚀刻终止层上方的一第一绝缘层，然后图案化半导体层，借以形成一半导体鳍状体，接着形成一底切于半导体鳍状体底部的第一绝缘层，再形成一栅极介电层于半导体鳍状体表面，沉积一栅极材料层于栅极介电层表面，图案化栅极材料层，借以形成一栅极电极而跨接于半导体鳍状体侧壁与顶部表面，最后，形成一源极与一漏极于半导体鳍状体中。
本发明另一方面提供一种多栅极晶体管的结构，此结构包括一垂直半导体鳍状体、一栅极介电层、一栅极电极与一源极与一漏极。半导体鳍状体位于一衬底上方，衬底包括覆盖于一蚀刻终止层上方的一第一绝缘层，第一绝缘层在半导体鳍状体底部形成一底切，栅极介电层位于半导体鳍状体表面，栅极电极位于栅极介电层表面，而源极与漏极分别座落于栅极电极两侧，并位于半导体鳍状体中。
本发明提供的多栅极晶体管的结构，对于晶体管的开或关状态具有更佳的控制能力，还能抑制短沟道效应。
附图简要说明
下面结合附图对本发明的具体实施方式作进一步详细的描述。
附图中，
图1A为现有技术的双栅极晶体管结构的上视图；
图1B为沿图1A中1B-1B剖面线的剖面结构示意图；
图2A为现有技术的三栅极晶体管结构的上视图；
图2B为沿图2A中2B-2B剖面线的剖面结构示意图；
图3为本发明的三栅极晶体管的立体结构示意图；
图4A～4C为本发明制作三栅极晶体管的剖面结构流程示意图；
图5A～5E为本发明另一实施例制作三栅极晶体管的剖面结构流程示意图；
图6为本发明的三栅极晶体管的上视图(未形成导体层)；
图7为本发明另一实施例制作三栅极晶体管的过程中，在半导体鳍状体形成圆滑的顶部顶点的剖面结构示意图；
图8为本发明的三栅极晶体管的立体结构示意图(尚未形成间隙壁与源极、漏极)；
图9为沿图8中D-D剖面线的剖面结构示意图；
图10A为沿图6中B-B剖面线的剖面结构示意图；以及
图10B为沿图6中C-C剖面线的剖面结构示意图。
具体实施方式
由于现有技术的双栅极晶体管(图1B)或三栅极晶体管(图2B)的结构仍有改良空间，因此，本发明提供一种多栅极晶体管的结构，对于晶体管的开或关状态具有更佳的控制能力，还能抑制短沟道效应。
以下以本发明三栅极晶体管为例，说明本发明对于现有技术的双栅极晶体管或三栅极晶体管改良的结构，请参照图3，其为本发明的三栅极晶体管的立体结构示意图，三栅极晶体管的结构包括一垂直半导体鳍状体33、一栅极介电层32、一栅极电极35与一源极361与一漏极362。半导体鳍状体33位于一衬底30上方，衬底30在表面具有一绝缘层31，绝缘层31在半导体鳍状体33底部形成一底切37，栅极介电层32位于半导体鳍状体33表面，栅极电极35位于栅极介电层32表面，而源极361与漏极362分别座落于栅极电极35两侧，并位于半导体鳍状体33中。由于结构上形成底切37，使得此改良的三栅极晶体管，也称为Omega-场效应晶体管(Ω-FET)，近似于”E.Leobandung etal.，“Wire-channel and wrap-around-gate metal-oxide-semiconductor field-effecttransistors with a significant reduction of short channel effects，”J.Vacuum Scienceand Technology B，vol.15，no.6，pp.2791-2794”中所提出的包覆栅极晶体管(Gate-All-Around)的结构，实际上，形成底切时的横蚀量越大造成此Ω-场效应晶体管的结构越近似于包覆栅极晶体管(Gate-All-Around)，因此，对于晶体管的开或关状态具有更佳的控制能力，另外，制造此改良的三栅极晶体管使用了与现有的三栅极晶体管相近的工艺。
请参照图4A～4C，为本发明制作三栅极晶体管的剖面结构流程示意图。首先，如图4A所示，形成一半导体层鳍状体42于一衬底40上方，衬底表面具有一绝缘层41。
接着，图4B中，借由蚀刻形成一底切43于半导体鳍状体42底部的绝缘层41。例如，当绝缘层41的材料为氧化硅时，可以用稀释氢氟酸(水∶浓氢氟酸的量约为25∶1)在摄氏25℃下进行湿蚀刻60秒，以达到约100的下蚀量R。由于湿蚀刻有侧向蚀刻，因此得以在半导体鳍状体42底部的绝缘层41形成底切43。然而，工艺上在控制湿蚀刻时间有一定困难，致使片与片、批与批之间的下蚀量R有所差异。
最后，图4C中，形成一栅极介电层44、一栅极电极45于半导体鳍状体42表面，并形成一源极与一漏极(未显示于图中)于半导体鳍状体42中，至此则完成三栅极晶体管的制作。
如前所述，下蚀量R并不易控制，因此，本发明另外提供一种可容易控制下蚀量R的工艺。请参照图5A～5E，为本发明另一实施例制作三栅极晶体管的剖面结构流程示意图，其为沿图6中A-A剖面线的剖面结构。首先，如图5A所示，提供一衬底50，并形成一半导体层52于一绝缘堆栈层上方，其中半导体层52之材料选自硅或者锗。衬底50表面具有一绝缘堆栈层51，绝缘堆栈层51包括第一绝缘层513、蚀刻终止层512与第二绝缘层511，其中第一绝缘层513覆盖于蚀刻终止层512上方，蚀刻终止层512覆盖于第二绝缘层511上方。第一绝缘层513的材料可以为任何一第一介电材料，例如氧化硅，第一绝缘层513的厚度介于20～1000之间为较佳。第二绝缘层511的材料可以为任何相同于第一介电材料的材料，第二绝缘层511的厚度介于20～1000之间为较佳。蚀刻终止层512的材料可以为任何蚀刻速率低于第一介电材料的一第二介电材料，蚀刻终止层512的厚度介于20～1000之间为较佳。如果第一介电材料为氧化硅而第二介电材料为氮化硅，则可以用稀释氢氟酸湿蚀刻第一介电材料。
图5B中，再以蚀刻遮罩53定义并形成一半导体鳍状体54，蚀刻遮罩53的材料可以为任何作为蚀刻罩幕的材料，例如光致抗蚀剂、氧化硅、氮化硅，蚀刻遮罩53的较佳材料为氧化硅。半导体鳍状体54的材料选自硅或者锗。根据本发明，可以移除蚀刻遮罩53或不移除蚀刻遮罩53，若移除蚀刻遮罩53则形成三栅极晶体管，若不移除蚀刻遮罩53则形成双栅极晶体管。根据本发明，形成半导体鳍状体54时，还可选择性的包括平滑化半导体鳍状体54表面的步骤，平滑化半导体鳍状体54可使得半导体鳍状体54中载子达到良好移动能力，平滑化可以先经由一牺牲式氧化步骤，然后再经一侧壁处理步骤(例如在1000℃的氢气环境中加热)。若蚀刻遮罩53的材料为氧化硅，则可在平滑化之前或之后移除蚀刻遮罩53，之后移除则半导体鳍状体54最后会具有尖角的顶部顶点，之前移除则半导体鳍状体54最后会具有圆滑的顶部顶点56(如图7所示)。若蚀刻遮罩53的材料为光致抗蚀剂，则光致抗蚀剂必须在平滑化前移除，借以避免平滑化过程中的高温造成破坏。
图5C中，移除蚀刻遮罩53。
图5D中，借由蚀刻形成一底切55于半导体鳍状体54底部的第一绝缘层513。其中一种方式，是使用稀释氢氟酸(水∶浓氢氟酸的量约为25∶1)在摄氏25℃下进行湿蚀刻30～600秒，以达到约50～1000的下蚀量R，其中湿蚀刻时间影响横蚀量E。另一种方式，是先进行干蚀刻，再进行湿蚀刻。干蚀刻为一非等向性蚀刻，可使用含氟的等离子体气体进行干蚀刻，而停止于蚀刻终止层512，之后的湿蚀刻过程仅有侧向蚀刻，湿蚀刻时间影响横蚀量E，较佳的横蚀量E介于20～500之间。若在平滑化之前移除蚀刻遮罩53，则半导体鳍状体54最后会具有圆滑的顶部顶点56(如图7所示)。
图5E中，形成一栅极介电层59于半导体鳍状体54表面，可借由热氧化、化学气相沉积或溅镀方式形成此栅极介电层59。一般来说，栅极介电层59位于半导体鳍状体54顶部表面的厚度比位于半导体鳍状体54侧壁的厚度薄，栅极介电层59位于半导体鳍状体54顶部表面的厚度低于20。栅极介电层59的材料可以为传统材料，例如氧化硅或氮氧化硅，其厚度介于3～100之间，较佳者为小于10。栅极介电层59的材料也可以为高介电常数材料(介电常数高于5)，例如氧化镧、氧化铝、氧化铪、氮氧化铪与氧化锆，其厚度介于3～100之间。
接着，沉积一栅极材料层于栅极介电层59表面，栅极材料层的材料可以为多晶硅、多晶硅化锗、回火金属(例如钼、钨)、化合物(例如氮化钛)或其它导电材料。接着，图案化栅极材料层，借以形成一栅极电极60而跨接于半导体鳍状体54侧壁与顶部表面。栅极材料层较佳的材料为多晶硅，栅极介电层59的材料为氮氧化硅，可使用含氯与溴的等离子体气体进行干蚀刻，而停止于栅极介电层59。然后，再移除未被栅极电极60覆盖住的栅极介电层59，至此，所形成的结构(尚未形成间隙壁与源极、漏极)的立体示意图如图8所示。
之后的工艺，请参照图9，其为沿图8中D-D剖面线的剖面结构示意图。再经由离子植入、等离子体含浸离子植入(plasma immersion ion implantation，PIII)或其它传统方式形成轻掺杂区域(lightly-doped drain)61。再以传统方式在栅极电极60侧壁形成间隙壁58，例如先沉积一间隙壁材料层，然后回蚀刻此间隙壁材料层，间隙壁材料层的材料可以为介电材料，例如氮化硅或二氧化硅，较佳的间隙壁材料层的材料为氮化硅与氧化硅的复合层。然后，经由离子植入、等离子体含浸离子植入、气体或固体源扩散或其它传统方式形成一源极621与一漏极622于半导体鳍状体54。任何因离子植入而造成的晶格破坏可在此时再经一加热步骤修复缺陷，至此，如图6所示，其为本发明的三栅极晶体管的上视图(尚未形成导体层)。最后，栅极电极60、源极621与漏极622可再在其表面形成一导体层63，借以降低阻值，导体层63的材料可以为金属硅化物(例如硅化钛、硅化钴、硅化镍)、金属氮化物(例如氮化钛、氮化铊)、金属(例如钨、铜)或重掺杂半导体(例如n+重掺杂硅)。较佳的导体层63的材料为硅化镍，可以经由自我对准金属硅化物(self-aligned silicide，salicide)工艺形成硅化镍。如图10A、图10B所示，其分别为沿图6中B-B与C-C剖面线的剖面结构示意图，所形成的导体层63位于半导体鳍状体54侧壁与顶部表面。至此，则完成三栅极晶体管的制作。
可以理解的是，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明所附的权利要求的保护范围。
Claims (21)
1、一种多栅极晶体管的制造方法，其特征在于，该制造方法至少包括下列步骤：
形成一半导体层于一绝缘堆栈层上方，该绝缘堆栈层包括覆盖于一蚀刻终止层上方的一第一绝缘层；
图案化该半导体层，借以形成一半导体鳍状体；
形成一底切于该半导体鳍状体底部的该第一绝缘层；
形成一栅极介电层于该半导体鳍状体表面；
沉积一栅极材料层于该栅极介电层表面；
图案化该栅极材料层，借以形成一栅极电极而跨接于该半导体鳍状体侧壁与顶部表面；以及
形成一源极与一漏极于该半导体鳍状体中。
2、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，该半导体层的材料选自硅或者锗。
3、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，该第一绝缘层的材料为氧化硅，其厚度介于20～1000之间。
4、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，该蚀刻终止层的材料为氮化硅，其厚度介于20～1000之间。
5、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，形成该半导体鳍状体还包括平滑化该半导体鳍状体表面的步骤，其中平滑化该半导体鳍状体表面，先进行牺牲式氧化，然后再在氢气环境中加热。
6、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，以一湿蚀刻程序形成该底切，该湿蚀刻程序蚀刻该第一绝缘层，而停止于该蚀刻终止层。
7、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，先以一干蚀刻程序，再以一湿蚀刻程序形成该底切，其中该干蚀刻程序蚀刻该第一绝缘层，而停止于该蚀刻终止层，其中以氢氟酸进行该湿蚀刻程序。
8、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，形成该底切于该半导体鳍状体下方，造成介于50～1000之间的下蚀量，而且造成介于20～500之间的横蚀量。
9、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，该栅极介电层的材料选自于氧化硅、氮氧化硅与介电常数高于5的介电常数材料之一，其厚度介于3～100之间。
10、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，该栅极材料层的材料选自于多晶硅或者多晶硅化锗。
11、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，该源极与该漏极包括一轻掺杂区域。
12、根据权利要求1所述的多栅极晶体管的制造方法，其特征在于，该源极与该漏极表面形成有一导体层，该导体层的材料选自金属、金属硅化物与金属氮化物群组之一。
13、一种多栅极晶体管的结构，其特征在于，该结构至少包括：
一垂直半导体鳍状体，位于一衬底上方，该衬底包括覆盖于一蚀刻终止层上方的一第一绝缘层，该第一绝缘层在该半导体鳍状体底部形成一底切；
一栅极介电层，位于该半导体鳍状体表面；
一栅极电极，位于该栅极介电层表面；以及
一源极与一漏极，分别座落于该栅极电极两侧，并位于该半导体鳍状体中。
14、根据权利要求13所述的多栅极晶体管的结构，其特征在于，该半导体鳍状体的材料选自于硅或者锗。
15、根据权利要求13所述的多栅极晶体管的结构，其特征在于，该半导体鳍状体具有圆滑的顶部顶点。
16、根据权利要求13所述的多栅极晶体管的结构，其特征在于，该第一绝缘层的材料为氧化硅，其厚度介于20～1000之间。
17、根据权利要求13所述的多栅极晶体管的结构，其特征在于，该蚀刻终止层的材料为氮化硅，其厚度介于20～1000之间。
18、根据权利要求13所述的多栅极晶体管的结构，其特征在于，该栅极介电层的材料选自于氧化硅、氮氧化硅与介电常数高于5的介电常数材料群组之一，其厚度介于3～100之间。
19、根据权利要求13所述的多栅极晶体管的结构，其特征在于，该栅极电极的材料选自于多晶硅或者多晶硅化锗。
20、根据权利要求13所述的多栅极晶体管的结构，其特征在于，该源极与该漏极包括一轻掺杂区域。
21、根据权利要求13所述的多栅极晶体管的结构，其特征在于，该源极与该漏极表面形成有一导体层，该导体层的材料选自于金属与金属硅化物之一。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/401,087 | 2003-03-26 | ||
| US10/401,087 US6844238B2 (en) | 2003-03-26 | 2003-03-26 | Multiple-gate transistors with improved gate control |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1534745A CN1534745A (zh) | 2004-10-06 |
| CN1251317C true CN1251317C (zh) | 2006-04-12 |
Family
ID=33096812
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN03153008.7A Expired - Lifetime CN1251317C (zh) | 2003-03-26 | 2003-08-01 | 多栅极晶体管的结构及其制造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6844238B2 (zh) |
| CN (1) | CN1251317C (zh) |
| SG (1) | SG115643A1 (zh) |
| TW (1) | TW594990B (zh) |
Families Citing this family (92)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7358121B2 (en) | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
| US7074656B2 (en) * | 2003-04-29 | 2006-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doping of semiconductor fin devices |
| US6909151B2 (en) | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
| US7456476B2 (en) | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
| JP3863516B2 (ja) * | 2003-10-03 | 2006-12-27 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US6855588B1 (en) * | 2003-10-07 | 2005-02-15 | United Microelectronics Corp. | Method of fabricating a double gate MOSFET device |
| DE10348007B4 (de) * | 2003-10-15 | 2008-04-17 | Infineon Technologies Ag | Verfahren zum Strukturieren und Feldeffekttransistoren |
| US6946377B2 (en) * | 2003-10-29 | 2005-09-20 | Texas Instruments Incorporated | Multiple-gate MOSFET device with lithography independent silicon body thickness and methods for fabricating the same |
| DE10361695B3 (de) * | 2003-12-30 | 2005-02-03 | Infineon Technologies Ag | Transistorstruktur mit gekrümmtem Kanal, Speicherzelle und Speicherzellenfeld für DRAMs sowie Verfahren zur Herstellung eines DRAMs |
| US7624192B2 (en) * | 2003-12-30 | 2009-11-24 | Microsoft Corporation | Framework for user interaction with multiple network devices |
| US7105390B2 (en) * | 2003-12-30 | 2006-09-12 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
| US7268058B2 (en) | 2004-01-16 | 2007-09-11 | Intel Corporation | Tri-gate transistors and methods to fabricate same |
| US7154118B2 (en) | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
| US7262084B2 (en) * | 2004-04-15 | 2007-08-28 | International Business Machines Corporation | Methods for manufacturing a finFET using a conventional wafer and apparatus manufactured therefrom |
| US7579280B2 (en) * | 2004-06-01 | 2009-08-25 | Intel Corporation | Method of patterning a film |
| KR100560818B1 (ko) * | 2004-06-02 | 2006-03-13 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
| US7452778B2 (en) * | 2004-06-10 | 2008-11-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor nano-wire devices and methods of fabrication |
| US6960509B1 (en) * | 2004-06-30 | 2005-11-01 | Freescale Semiconductor, Inc. | Method of fabricating three dimensional gate structure using oxygen diffusion |
| US7042009B2 (en) | 2004-06-30 | 2006-05-09 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
| US20090014795A1 (en) * | 2004-07-29 | 2009-01-15 | Risho Koh | Substrate for field effect transistor, field effect transistor and method for production thereof |
| US7348284B2 (en) | 2004-08-10 | 2008-03-25 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
| US6969644B1 (en) * | 2004-08-31 | 2005-11-29 | Texas Instruments Incorporated | Versatile system for triple-gated transistors with engineered corners |
| US7422946B2 (en) | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
| US7332439B2 (en) * | 2004-09-29 | 2008-02-19 | Intel Corporation | Metal gate transistors with epitaxial source and drain regions |
| US7361958B2 (en) | 2004-09-30 | 2008-04-22 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
| US6949768B1 (en) * | 2004-10-18 | 2005-09-27 | International Business Machines Corporation | Planar substrate devices integrated with finfets and method of manufacture |
| US20060086977A1 (en) * | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
| US7151018B1 (en) * | 2004-11-15 | 2006-12-19 | Kla-Tencor Technologies Corporation | Method and apparatus for transistor sidewall salicidation |
| US7193279B2 (en) * | 2005-01-18 | 2007-03-20 | Intel Corporation | Non-planar MOS structure with a strained channel region |
| US7224033B2 (en) * | 2005-02-15 | 2007-05-29 | International Business Machines Corporation | Structure and method for manufacturing strained FINFET |
| US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
| US9685524B2 (en) * | 2005-03-11 | 2017-06-20 | Vishay-Siliconix | Narrow semiconductor trench structure |
| US20060202266A1 (en) * | 2005-03-14 | 2006-09-14 | Marko Radosavljevic | Field effect transistor with metal source/drain regions |
| FR2885733B1 (fr) * | 2005-05-16 | 2008-03-07 | St Microelectronics Crolles 2 | Structure de transistor a trois grilles |
| US7858481B2 (en) | 2005-06-15 | 2010-12-28 | Intel Corporation | Method for fabricating transistor with thinned channel |
| US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
| US7279375B2 (en) | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
| US7402875B2 (en) | 2005-08-17 | 2008-07-22 | Intel Corporation | Lateral undercut of metal gate in SOI device |
| US20070090416A1 (en) | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
| US7479421B2 (en) | 2005-09-28 | 2009-01-20 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
| US20070090408A1 (en) * | 2005-09-29 | 2007-04-26 | Amlan Majumdar | Narrow-body multiple-gate FET with dominant body transistor for high performance |
| US7326976B2 (en) * | 2005-11-15 | 2008-02-05 | International Business Machines Corporation | Corner dominated trigate field effect transistor |
| US7485503B2 (en) | 2005-11-30 | 2009-02-03 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
| TWI489557B (zh) | 2005-12-22 | 2015-06-21 | Vishay Siliconix | 高移動率ｐ-通道溝槽及平面型空乏模式的功率型金屬氧化物半導體場效電晶體 |
| KR100707208B1 (ko) * | 2005-12-24 | 2007-04-13 | 삼성전자주식회사 | Ｇａａ 구조의 핀-펫 및 그 제조 방법 |
| US7396711B2 (en) * | 2005-12-27 | 2008-07-08 | Intel Corporation | Method of fabricating a multi-cornered film |
| KR100718149B1 (ko) * | 2006-02-07 | 2007-05-14 | 삼성전자주식회사 | 게이트-올-어라운드 구조의 반도체 소자 |
| US7439594B2 (en) | 2006-03-16 | 2008-10-21 | Micron Technology, Inc. | Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors |
| US8409954B2 (en) * | 2006-03-21 | 2013-04-02 | Vishay-Silconix | Ultra-low drain-source resistance power MOSFET |
| US7422960B2 (en) | 2006-05-17 | 2008-09-09 | Micron Technology, Inc. | Method of forming gate arrays on a partial SOI substrate |
| US8143646B2 (en) | 2006-08-02 | 2012-03-27 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
| US7537994B2 (en) | 2006-08-28 | 2009-05-26 | Micron Technology, Inc. | Methods of forming semiconductor devices, assemblies and constructions |
| US20080157225A1 (en) * | 2006-12-29 | 2008-07-03 | Suman Datta | SRAM and logic transistors with variable height multi-gate transistor architecture |
| US7691690B2 (en) * | 2007-01-12 | 2010-04-06 | International Business Machines Corporation | Methods for forming dual fully silicided gates over fins of FinFet devices |
| US8286114B2 (en) * | 2007-04-18 | 2012-10-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3-dimensional device design layout |
| US8258035B2 (en) * | 2007-05-04 | 2012-09-04 | Freescale Semiconductor, Inc. | Method to improve source/drain parasitics in vertical devices |
| US8237201B2 (en) | 2007-05-30 | 2012-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layout methods of integrated circuits having unit MOS devices |
| JP4814960B2 (ja) * | 2007-07-27 | 2011-11-16 | パナソニック株式会社 | 半導体装置の製造方法 |
| EP2037492A1 (en) * | 2007-09-11 | 2009-03-18 | S.O.I.Tec Silicon Insulator Technologies | Multiple gate field effect transistor structure and method for fabricating same |
| US7910994B2 (en) * | 2007-10-15 | 2011-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for source/drain contact processing |
| US7795091B2 (en) | 2008-04-30 | 2010-09-14 | Winstead Brian A | Method of forming a split gate memory device and apparatus |
| US7910482B2 (en) * | 2008-05-30 | 2011-03-22 | Freescale Semiconductor, Inc. | Method of forming a finFET and structure |
| US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
| DE102008030864B4 (de) * | 2008-06-30 | 2010-06-17 | Advanced Micro Devices, Inc., Sunnyvale | Halbleiterbauelement als Doppelgate- und Tri-Gatetransistor, die auf einem Vollsubstrat aufgebaut sind und Verfahren zur Herstellung des Transistors |
| KR101113794B1 (ko) | 2008-08-04 | 2012-02-27 | 주식회사 하이닉스반도체 | 반도체 장치 제조 방법 |
| US8912602B2 (en) * | 2009-04-14 | 2014-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs and methods for forming the same |
| CN101877317B (zh) * | 2009-04-29 | 2013-03-27 | 台湾积体电路制造股份有限公司 | 非平坦晶体管及其制造方法 |
| US20100308382A1 (en) * | 2009-06-08 | 2010-12-09 | Globalfoundries Inc. | Semiconductor structures and methods for reducing silicon oxide undercuts in a semiconductor substrate |
| CN102104069B (zh) * | 2009-12-16 | 2012-11-21 | 中国科学院微电子研究所 | 鳍式晶体管结构及其制作方法 |
| CN102117829B (zh) * | 2009-12-30 | 2012-11-21 | 中国科学院微电子研究所 | 鳍式晶体管结构及其制作方法 |
| US8242560B2 (en) * | 2010-01-15 | 2012-08-14 | International Business Machines Corporation | FinFET with thin gate dielectric layer |
| CN102222691A (zh) * | 2010-04-13 | 2011-10-19 | 联合大学 | 高驱动电流三维多重闸极晶体管及其制法 |
| US8637359B2 (en) * | 2011-06-10 | 2014-01-28 | International Business Machines Corporation | Fin-last replacement metal gate FinFET process |
| US8674449B2 (en) | 2011-09-08 | 2014-03-18 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device and method for manufacturing the same |
| CN103000664B (zh) * | 2011-09-08 | 2015-12-16 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
| CN103035517B (zh) * | 2011-09-29 | 2017-07-04 | 联华电子股份有限公司 | 半导体制作工艺 |
| US9412883B2 (en) | 2011-11-22 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for MOS capacitors in replacement gate process |
| US8884370B2 (en) | 2012-04-27 | 2014-11-11 | International Business Machines Corporation | Narrow body field-effect transistor structures with free-standing extension regions |
| US9006829B2 (en) | 2012-08-24 | 2015-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Aligned gate-all-around structure |
| US8716751B2 (en) * | 2012-09-28 | 2014-05-06 | Intel Corporation | Methods of containing defects for non-silicon device engineering |
| JP6094159B2 (ja) * | 2012-11-13 | 2017-03-15 | 三菱電機株式会社 | 半導体装置の製造方法 |
| FR3002813B1 (fr) * | 2013-03-01 | 2016-08-05 | St Microelectronics Sa | Procede de fabrication d'un transistor mos a ailette |
| US9263455B2 (en) | 2013-07-23 | 2016-02-16 | Micron Technology, Inc. | Methods of forming an array of conductive lines and methods of forming an array of recessed access gate lines |
| US9496373B2 (en) * | 2015-04-02 | 2016-11-15 | International Business Machines Corporation | Damage-resistant fin structures and FinFET CMOS |
| EP3295486A4 (en) | 2015-05-08 | 2019-01-16 | Cirrus Logic International Semiconductor Ltd. | HIGH-DENSITY CAPACITORS FORMED FROM THIN VERTICAL SEMICONDUCTOR STRUCTURES SUCH AS FINFET |
| US9748394B2 (en) * | 2015-05-20 | 2017-08-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET having a multi-portioned gate stack |
| US10199503B2 (en) | 2017-04-24 | 2019-02-05 | International Business Machines Corporation | Under-channel gate transistors |
| US10825931B2 (en) * | 2018-02-13 | 2020-11-03 | Nanya Technology Corporation | Semiconductor device with undercutted-gate and method of fabricating the same |
| US11164844B2 (en) * | 2019-09-12 | 2021-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Double etch stop layer to protect semiconductor device layers from wet chemical etch |
| CN112635560B (zh) * | 2019-10-08 | 2023-12-05 | 联华电子股份有限公司 | 鳍状晶体管结构及其制造方法 |
| US11024749B1 (en) * | 2020-06-15 | 2021-06-01 | Taiwan Semiconductor Manufacturing Company Limited | Dual channel transistor device and methods of forming the same |
| US20220352348A1 (en) * | 2021-04-30 | 2022-11-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch selective bottom-up dielectric film |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6521949B2 (en) * | 2001-05-03 | 2003-02-18 | International Business Machines Corporation | SOI transistor with polysilicon seed |
| US6512266B1 (en) * | 2001-07-11 | 2003-01-28 | International Business Machines Corporation | Method of fabricating SiO2 spacers and annealing caps |
| US6596599B1 (en) * | 2001-07-16 | 2003-07-22 | Taiwan Semiconductor Manufacturing Company | Gate stack for high performance sub-micron CMOS devices |
| US6514808B1 (en) * | 2001-11-30 | 2003-02-04 | Motorola, Inc. | Transistor having a high K dielectric and short gate length and method therefor |
| US20030111678A1 (en) * | 2001-12-14 | 2003-06-19 | Luigi Colombo | CVD deposition of M-SION gate dielectrics |
-
2003
- 2003-03-26 US US10/401,087 patent/US6844238B2/en not_active Expired - Lifetime
- 2003-07-01 TW TW092118009A patent/TW594990B/zh not_active IP Right Cessation
- 2003-08-01 CN CN03153008.7A patent/CN1251317C/zh not_active Expired - Lifetime
-
2004
- 2004-03-03 SG SG200401506A patent/SG115643A1/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| TW594990B (en) | 2004-06-21 |
| SG115643A1 (en) | 2005-10-28 |
| US6844238B2 (en) | 2005-01-18 |
| US20040198003A1 (en) | 2004-10-07 |
| CN1534745A (zh) | 2004-10-06 |
| TW200419802A (en) | 2004-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1251317C (zh) | 多栅极晶体管的结构及其制造方法 | |
| CN1264217C (zh) | 多重栅极结构及其制造方法 | |
| CN1253943C (zh) | 具有多重栅极及应变的沟道层的晶体管及其制造方法 | |
| KR100487656B1 (ko) | 반도체 기판과 ″ｌ″형 스페이서 사이에 에어 갭을구비하는 반도체 소자 및 그 제조 방법 | |
| US8193057B2 (en) | MOS transistor for reducing short-channel effects and its production | |
| KR100188823B1 (ko) | 반도체 장치의 제조방법 | |
| CN100530688C (zh) | 多重栅极晶体管与其形成方法 | |
| CN101558499B (zh) | 用于在沟槽栅极fet内形成横向延伸电介质层的结构及方法 | |
| US5256586A (en) | Gate-to-drain overlapped MOS transistor fabrication process | |
| CN101032032A (zh) | 具有变细的下本体部分的非平面器件及制造方法 | |
| CN1728385A (zh) | 沟槽应变抬升源/漏结构及其制造方法 | |
| JP2002184973A (ja) | 半導体装置及びその製造方法 | |
| US5780324A (en) | Method of manufacturing a vertical semiconductor device | |
| CN1713395A (zh) | 能够调整阈值电压的半导体器件及其制造方法 | |
| CN102969345B (zh) | 具有t型鳍部的鳍式场效应管及其形成方法 | |
| US7084458B1 (en) | Semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process | |
| US10692992B2 (en) | Semiconductor device and fabrication method thereof | |
| CN2710166Y (zh) | 多栅极晶体管的结构 | |
| JPH08186260A (ja) | Ｍｏｓトランジスタの製造方法 | |
| CN2692841Y (zh) | 多重栅极结构 | |
| US20220238674A1 (en) | Methods for forming planar metal-oxide-semiconductor field-effect transistors | |
| TW578218B (en) | Multiple-gate structure and method to fabricate the same | |
| CN103000688B (zh) | 鳍式场效应管的结构及形成方法 | |
| US20190164831A1 (en) | Semiconductor device and fabrication method thereof | |
| CN2699480Y (zh) | 具有多重栅极及应变的沟道层的晶体管 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20060412 |