CN1180458C - 半导体器件中形成金属栅的方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
Abstract
一种形成金属栅的方法，它可阻止形成于该金属栅上的栅绝缘膜性能的降级。形成金属栅的方法包括提供一个具有一个或多个用于确定有效区域的沟状的器件隔离膜的硅基体；用热氧化工艺在硅基体表面上形成栅绝缘膜；继续在栅绝缘膜上形成金属阻挡膜和栅的金属膜；为栅的金属膜、金属阻挡膜和栅绝缘膜构图，其中金属阻挡膜和栅的金属膜的沉积通过原子层沉积(ALD)工艺或遥控等离子体化学汽相沉积(CVD)工艺来实施。
Description
技术领域
本发明的方法一般涉及一种半导体器件中形成金属栅的方法。公开的方法尤其涉及一种可阻止栅绝缘膜中栅氧化物完整性(GOI)性能降级的半导体器件中的金属栅的形成方法。
背景技术
氧化硅膜(SiO2)主要一直被用作MOSFET(金属氧化物半导体场效应晶体管)中的栅绝缘膜的材料，多晶硅膜一直被用作栅的材料是本领域熟知的。但是，随着半导体器件的集成度的提高，需要减小栅的线宽和栅绝缘膜的厚度。当氧化硅膜用作栅绝缘膜的材料时，如果栅绝缘膜的厚度太薄，由于直接穿通栅绝缘膜的隧道效应的增强而产生的漏电，使绝缘性能不稳定。
例如，当氧化硅膜被用作目前大量生产的DRAM(动态随机存取存储器)和逻辑器件的栅绝缘膜时，其用于70nm厚的器件时，希望其厚度在DRAM中为30-35，在逻辑器件中为13-15。由于多晶硅栅损耗效应(PDE)所增加的电容器元件增至3-8，但是减少厚度范围在15-30之间的栅氧化物膜占有的电测厚度(Teff)是困难的。
因此，作为一种克服上述问题的方法，人们一直努力用一种介电常数高的、比氧化硅膜的介电常数高的材料作为栅绝缘膜的材料。为了使多晶硅栅损耗效应降至最低，也努力用金属栅代替多晶硅栅。
当为金属栅时，作为金属阻挡膜的TiN或WN膜介于栅的金属膜和栅绝缘膜之间，用作蚀刻掩膜的坚固的掩膜置于栅金属膜上。
但是，根据常规技术在氧化硅栅绝缘膜上形成金属栅时，存在栅绝缘膜下述列各项性能降低的问题。
栅金属膜的沉积通常通过喷溅或化学气相沉积(CVD)来实现。但是，在硅栅绝缘膜上直接通过喷溅或CVD沉积栅的金属膜时，降低了栅绝缘膜的接口性能和绝缘性能。
图1A和1B给出了MOS电容器的电容(C)-电压(V)的曲线，该电容器是在根据常规技术用喷溅法形成的氧化硅栅绝缘膜上直接沉积TiN或WN膜作阻挡膜后，继续沉积钨(W)膜作为栅的金属膜而形成的。
如图所示，包括陆续在氧化硅栅绝缘膜上沉积金属阻挡膜(TiN或WN)和沉积钨膜栅的步骤的实施方式中，未进行随后的退火工艺，不重点考虑与电容-电压性能有关的沉积金属阻挡膜材料(TiN或WN)和喷溅方法(常规的IMP校准)，由于过多的峰值约为1E12/eV-cm2的接口陷阱密度和滞后约为1E12/cm2的氧化物陷阱电荷，从而形成了高数量级的氧化物缺陷电荷。基于此，导致了栅本身绝缘性能的损失和与基体的接口的严重损坏。
同时，该损坏可通过高温退火工艺，如800℃下恢复至一定的程度，但是不能实现对损坏的栅绝缘膜的完全恢复。另外，高温退火工艺有缺点而且成本高，并且必须增加栅绝缘膜的电测厚度(Teff)以恢复一些损失的性能。
图2A至2C表明了TiCl4+NH3在650℃下以热沉积方法沉积的TiN金属栅中的电容(C)-电压(V)曲线图。
如图所示，沉积后MOS晶体管的性能相对好于用喷溅法沉积得到的晶体管的性能。但是，由于在随后的退火工艺后，栅绝缘膜中电测厚度(Teff)和氧化物陷阱电荷的增加，从而产生了栅氧化物完整性(GOI)性能的降级，即增加了滞后现象。尤其是，当制造MOS电容器/晶体管时，可产生严重的栅氧化物完整性(GOI)性能的降级。
发明内容
因此，公开的方法是解决上述问题的发明，公开的方法的一个目的是提供一种形成金属栅的方法，该金属栅可防止栅绝缘膜的GOI性能的降级。
为了达到上述目的，根据公开的方法，形成金属栅的方法包括一个提供硅基体的步骤，该基体具有沟状的器件隔离膜以确定有效的区域；用热氧化工艺在硅基体表面上形成栅绝缘膜；继续在栅绝缘膜上形成金属阻挡膜和栅的金属膜；为栅的金属膜、金属阻挡膜和栅绝缘膜构图，其中金属阻挡膜和栅的金属膜的沉积通过原子层沉积(ALD)工艺和/或遥控等离子体化学汽相沉积工艺来实施。
根据公开的方法，金属阻挡膜和栅的金属膜通过原子层沉积(ALD)工艺或遥控等离子体CVD工艺沉积。从而将在沉积膜的工艺过程中产生的栅绝缘膜的损坏降至最小。
结合下面的描述和附图，将对公开的方法的上述内容和其它的特征作更充分的解释。
附图说明
图1A和1B是表明根据常规技术，用喷溅法在氧化硅膜上直接沉积TiN或WN膜和钨(W)膜的电容(C)-电压(V)曲线图；
图2A至2C表明根据常规技术，TiCl4+NH3在650℃下以热沉积方法沉积的TiN金属栅中电容(C)-电压(V)的曲线图；和
图3A至3C是包括根据本发明的实施方式形成的金属栅的半导体器件的截面图。
具体实施方式
将通过优选的实施方式参考附图对公开的方法进行详细的描述，其中用同样的参考数字表示相同或相似的部件。
图3A至3C是包括根据本发明的一个实施方式形成的金属栅的半导体器件的截面图。
图3A中，提供了硅基体1。在硅基体1的特定区域上形成了沟状的器件隔离膜2以确定有效的区域。此时，器件隔离膜2可用常规的LOCOS(硅的局部氧化)工艺形成。通过热氧化工艺在硅基体1表面上形成的栅绝缘膜3是由氧化硅制成的厚度为10-40的膜。此时，优选热氧化工艺在650℃-900℃的炉中用湿法(H2/O2)或干法(O2)来实施。
同时，可形成除热氧化工艺形成的氧化硅膜外的Al2O3、Ta2O5、TiO2、ZrO2、HfO2、Zr-硅酸盐、Hf-硅酸盐、La2O3中的任何一种或多种高介电常数绝缘膜和三维混合的绝缘膜(ZrAlO，HfAlO、ZrSiO4和HfSiO4)。在沉积高介电常数绝缘膜之前，也可形成超薄(例如3-30)的氧化硅膜。另外，用高介电常数绝缘膜作栅绝缘膜时，高介电常数绝缘膜可在氧气、氮气或惰性气氛下采用10-300秒的快速热工艺，或10-100分钟的熔炉工艺而经受退火工艺，并且可经过一个UV-臭氧工艺。
另外，尽管图中未示出，但是在栅绝缘膜3形成之前，可形成沟状的电容器。此时，介电膜可以包括ON膜、Ta2O5膜、Al2O3膜、BST膜或SBT膜中的一种。
图3B中，在栅绝缘膜3上陆续沉积金属阻挡膜4和金属膜5。优选金属阻挡膜4和栅的金属膜5通过非高温热沉积的工艺来沉积，例如，原子层沉积(ALD)工艺或遥控等离子体化学汽相沉积(CVD)工艺沉积，因为该工艺不受金属渗透或掺杂的影响。
上述方法中，由于ALD工艺允许在150℃-350℃的温度范围内进行循环的配料和清洗，阻止了栅绝缘膜3和基体1之间的接口性能和栅绝缘膜3本身性能的降级。优选在50℃-550℃的温度范围内、在0.05托-3托的压力下用N2、NH3、ND3或其混合物作清洗前体的材料来实施ALD工艺。
由于遥控等离子体CVD工艺实施方式在远处形成等离子体来沉积薄膜，也可得到与ALD工艺相同的效果。在遥控等离子体CVD工艺的实施过程中，优选在2.0GHz-9GHz的频率下，用电子回旋共振(ECR)作等离子源，He、Ar、Kr、Xe或其混合物作等离子体激发气。另外，在遥控等离子体CVD工艺中，将金属源如钛引入室内在晶片周围喷溅，并且在等离子体周围激发N源，从而Ti和N可被引入涂覆于晶片表面。
同时，金属阻挡膜4可由选自由TiN、TiAlN、TaN、MoN、WN和它们的混合物组成的组中的一种化合物组形成。优选金属阻挡膜4的厚度在50-500的范围内。栅的金属膜5也可以是由W、Ta、Al、TiSix、CoSix和NiSix组成的组中的一种形成，其中X是0.1-2.9之间的整数，它也可形成多晶硅、氮化钨膜和钨膜的栈结构。优选栅的金属膜5的厚度是300-1500。坚固的掩膜6可由二氧化硅膜(SiO2)、氮化硅膜(Si3N4)或氮氧化硅膜(SiON)形成。坚固的掩膜6的厚度是300-2000。
上述内容中，当金属阻挡膜4例如TiN通过ALD工艺和/或遥控等离子体CVD工艺沉积时，Ti的来源可以包括TiCl4、TDEAT(四(二乙基氨基)钛)或TDMAT(四(二甲基氨基)钛)，N的来源可以包括N2、NH3或ND3。该实施方式也包括沉积TiAlN作金属阻挡膜的步骤，Ti的来源可以包括TiCl4、TDEAT(四(二乙基氨基)钛)或TDMAT(四(二甲基氨基)钛)，N的来源可以包括N2、NH3或ND3，Al的来源可以包括AlCl3或TMA[Al(CH3)3]。另外，该实施方式包括沉积TaN作金属阻挡膜的步骤，Ta的来源可以包括TaCl4或叔丁醇钽，N的来源可以包括N2、NH3或ND3。该实施方式也可包括沉积MoN作金属阻挡膜的步骤，Mo的来源可以包括MoCl4、MoF6或叔丁醇钼，N的来源可以包括N2、NH3或ND3。另外，该实施方式包括沉积WN作金属阻挡膜的步骤，W的来源可以包括WF6或WCl4，N的来源可以包括N2、NH3或ND3。
图3C中，坚固的掩膜6的构图可以用例如通常的光刻法工艺。然后，利用坚固的掩膜6作蚀刻膜，用蚀刻工艺陆续将栅的金属膜5、阻挡膜4和栅绝缘膜3蚀刻，从而形成了金属栅10。
由于栅的金属膜5包括阻挡金属膜4是通过ALD工艺或遥控等离子体CVD工艺沉积的，因此用公开的方法形成的金属栅10可以阻止氧化硅栅绝缘膜3的GOI性能的降级。
同时，上述的实施方式也解释了用常规的栅形成工艺形成栅的方法，即栅绝缘膜和栅导电膜先沉积后构图的工艺。但是，公开的方法也适用于金银镶花工艺，其中通过形成并且去除牺牲栅确定栅形成区域后，在栅形成区域形成了金属栅。尤其是，如果公开的方法适用于金银镶花工艺的栅形成工艺，可得到更改善的效果。
正如从上述内容可理解的，公开的方法形成金属栅，其中阻挡金属膜和栅的金属膜是通过ALD工艺或遥控等离子体CVD工艺沉积的。从而公开的方法形成可以阻止栅绝缘膜性能的降级。因此，公开的方法不仅可以改善金属栅的性能，而且可以改善器件的性能。另外，由于ALD工艺和遥控等离子体CVD工艺沉积有好的台阶覆盖，工艺本身有优势，并且可以很有利的应用于高速/高密度器件的制造中。
参考特定的实施方式，对与特定的应用有关的公开的方法进行了描述。那些具有本领域的普通技术和可得到公开的方法的教导的人员将意识到在其范围内的其它的修正和应用。
因此，欲用所附的权利要求来覆盖在公开的方法的范围内的任何的和所有的这种应用、修正和实施方式。
Claims (12)
1.一种半导体器件中形成金属栅的方法，它包括的步骤为：
提供一个硅基体，该基体具有一个或多个用于确定有效区域的沟状的器件隔离膜；
用热氧化工艺在所述的硅基体表面上形成栅绝缘膜；
继续在所述的栅绝缘膜上形成金属阻挡膜和栅的金属膜；和
为所述的栅的金属膜、所述的金属阻挡膜和所述的栅绝缘膜构图，
其中所述的金属阻挡膜和所述的栅的金属膜的沉积通过选自由原子层沉积工艺和遥控等离子体化学汽相沉积工艺组成的组中的工艺来实施。
2.根据权利要求1的半导体器件中形成金属栅的方法，其中所述的热氧化工艺在温度范围为650℃-900℃下用湿法(H2/O2)或干法(O2)实施。
3.根据权利要求1的半导体器件中形成金属栅的方法，其中所述的金属阻挡膜选自由TiN、TiAlN、TaN、MoN和WN组成的组中。
4.根据权利要求1的半导体器件中形成金属栅的方法，其中所述的ALD工艺在50℃-550℃的温度范围内、在0.05托-3托的压力下、用选自由N2、NH3和ND3组成的组中的一种化合物作清洗前体的材料来实施。
5.根据权利要求1的半导体器件中形成金属栅的方法，其中遥控等离子体化学气相沉积工艺是在2.0GHz-9GHz的频率范围下，用电子回旋共振作等离子源，选自由He、Ar、Kr和Xe组成的组中的等离子体激发气来实施。
6.根据权利要求3的半导体器件中形成金属栅的方法，其中金属阻挡膜是TiN，其中Ti来源的提供选自由TiCl4、四(二乙基氨基)钛和四(二甲基氨基)钛组成的组中，N来源的提供选自由N2、NH3和ND3组成的组中。
7.根据权利要求3的半导体器件中形成金属栅的方法，其中金属阻挡膜是TiAlN，其中Ti来源的提供选自由TiCl4、四(二乙基氨基)钛和四(二甲基氨基)钛组成的组中；Al来源的提供选自由AlCl3和Al(CH3)3组成的组中；N来源的提供选自由N2、NH3、和ND3组成的组中。
8.根据权利要求3的半导体器件中形成金属栅的方法，其中金属阻挡膜是TaN，其中Ta来源的提供选自由TaCl4和叔丁醇钽组成的组中；N来源的提供选自由N2、NH3和ND3组成的组中。
9.根据权利要求3的半导体器件中形成金属栅的方法，其中金属阻挡膜是MoN，其中Mo来源的提供选自由MoCl4、MoF6和叔丁醇钼组成的组中；N来源的提供选自由N2、NH3和ND3组成的组中。
10.根据权利要求3的半导体器件中形成金属栅的方法，其中金属阻挡膜是WN，其中W来源的提供由WF6和WCl4组成的组中；N来源的提供选自由N2、NH3和ND3组成的组中。
11.根据权利要求1的半导体器件中形成金属栅的方法，其中所述的栅的金属膜选自由W、Ta、Al、TiSiX、CoSiX和NiSiX组成的组中，其中X是0.1-2.9之间的整数。
12.根据权利要求1的半导体器件中形成金属栅的方法，其中所述的栅的金属膜有多晶硅膜、氮化钨膜和钨膜的栈结构。
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| CN102315117B (zh) * | 2010-06-30 | 2013-05-22 | 中国科学院微电子研究所 | 一种Mo基/TaN金属栅叠层结构的刻蚀方法 |
| CN102956450B (zh) * | 2011-08-16 | 2015-03-11 | 中芯国际集成电路制造(北京)有限公司 | 一种制作半导体器件的方法 |
| KR20140003154A (ko) * | 2012-06-29 | 2014-01-09 | 에스케이하이닉스 주식회사 | 반도체 장치 제조 방법 |
| CN102842620A (zh) * | 2012-09-11 | 2012-12-26 | 京东方科技集团股份有限公司 | 薄膜晶体管及其制作方法、阵列基板、显示装置 |
| JP6176776B2 (ja) * | 2013-03-22 | 2017-08-09 | 株式会社日立国際電気 | 半導体装置の製造方法、基板処理装置、基板処理システムおよびプログラム |
| KR20210055148A (ko) * | 2019-11-06 | 2021-05-17 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
| CN113690178A (zh) * | 2021-08-23 | 2021-11-23 | 长江先进存储产业创新中心有限责任公司 | 金属导电结构的制造方法 |
| CN116454132A (zh) * | 2022-01-06 | 2023-07-18 | 长鑫存储技术有限公司 | 半导体结构及其制造方法 |
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|---|---|---|---|---|
| JPH065852A (ja) | 1992-06-23 | 1994-01-14 | Oki Electric Ind Co Ltd | Ｍｏｓｆｅｔ及びその製造方法 |
| JP3336747B2 (ja) * | 1994-06-09 | 2002-10-21 | ソニー株式会社 | 絶縁膜の形成方法、並びに半導体装置の作製方法及び半導体装置 |
| JPH09143699A (ja) | 1995-11-24 | 1997-06-03 | Nissin Electric Co Ltd | 基材処理方法およびその装置 |
| US5923056A (en) * | 1996-10-10 | 1999-07-13 | Lucent Technologies Inc. | Electronic components with doped metal oxide dielectric materials and a process for making electronic components with doped metal oxide dielectric materials |
| US6197683B1 (en) | 1997-09-29 | 2001-03-06 | Samsung Electronics Co., Ltd. | Method of forming metal nitride film by chemical vapor deposition and method of forming metal contact of semiconductor device using the same |
| US5907780A (en) * | 1998-06-17 | 1999-05-25 | Advanced Micro Devices, Inc. | Incorporating silicon atoms into a metal oxide gate dielectric using gas cluster ion beam implantation |
| KR100275738B1 (ko) | 1998-08-07 | 2000-12-15 | 윤종용 | 원자층 증착법을 이용한 박막 제조방법 |
| KR20000015134A (ko) * | 1998-08-27 | 2000-03-15 | 윤종용 | 질화티탄 전극층을 갖는 게이트 전극 및 그제조방법 |
| JP2000091269A (ja) | 1998-09-10 | 2000-03-31 | Fujitsu Ltd | 半導体装置の製造方法 |
| JP3945043B2 (ja) | 1998-10-12 | 2007-07-18 | ソニー株式会社 | 金属窒化物膜の形成方法および電子装置の製造方法 |
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- 2001-12-26 US US10/036,156 patent/US7157359B2/en not_active Expired - Lifetime
- 2001-12-26 JP JP2001393197A patent/JP2002237469A/ja active Pending
- 2001-12-28 CN CNB011447869A patent/CN1180458C/zh not_active Expired - Lifetime
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| JP2002237469A (ja) | 2002-08-23 |
| US7157359B2 (en) | 2007-01-02 |
| CN1363949A (zh) | 2002-08-14 |
| US20020086507A1 (en) | 2002-07-04 |
| TW516131B (en) | 2003-01-01 |
| KR20020056260A (ko) | 2002-07-10 |
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