CN1172357C - 近环绕栅极及制造具有该栅极的硅半导体器件的方法 - Google Patents
近环绕栅极及制造具有该栅极的硅半导体器件的方法 Download PDFInfo
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
- H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
Abstract
本发明揭示一种制造具有近环绕(quasi-surrounding)栅极的绝缘体上有硅(SOI)的半导体器件的方法。根据本发明的方法，可得到一种MOSFET半导体器件，其栅极电极几乎包围整个沟道区域，而达到体积反转(volume-inversion)的效果，可大幅增加该半导体器件的单位电流，亦可控制短沟道效应(SCE)的发生，而减少亚阈值漏电(sub-thresholdleakage)。此外，本发明的方法可以传统方式制造不同栅极长度的器件。
Description
技术领域
本发明涉及一种绝缘体上有硅(SOI)半导体器件的结构及其制造方法，特别涉及一种具有近环绕栅极的硅(SOI)半导体器件的结构及其制造方法。
背景技术
绝缘体上有硅的技术是与在一层覆盖于一绝缘层上的半导体材料中形成晶体管有关，其在集成电路的领域越来越重要。在一薄的SOI层上制作集成电路元件，相对于在一较厚的硅结构中制作相同的IC元件，可得到较低的寄生电容与较大的沟道电流，因而加快MOS整合电路的操作速度。再者，制作于SOI结构的硅膜中的场效电晶体，例如金氧半场效电晶体(MOSFET)，比制作于传统硅基材上的MOSFET具有更多优点，包括对短沟道效应的电阻、较陡峭的亚阈值(subthreshold)斜率、增加的电流驱动、较高的封装密度、减小的寄生电容以及简单的制程步骤等。此外，由于SOI结构有效地减少寄生元件，同时增加结构对接面崩溃的容忍度，因此SOI技术适用于高效能及高密度的集成电路。
绝缘体上有硅的技术与在一层覆盖于一绝缘层上的半导体材料中形成晶体管有关，其在集成电路的领域越来越重要。在一薄的硅层上制作集成电路组件，相对于在一较厚的硅结构中制作相同的IC组件，可得到较低的寄生电容与较大的沟道电流，因而加快MOS整合电路的操作速度。再者，制作于SOI结构的硅膜中的场效晶体管，例如金氧半场效晶体管(MOSFET)，比制作于传统硅基材上的MOSFET具有更多优点，包括对短沟道效应的电阻、较陡峭的亚阈值(subthreshold)斜率、增加的电流驱动、较高的封装密度、减小的寄生电容以及简单的制程步骤等。此外，由于SOI结构有效地减少寄生组件，同时增加结构对接面崩溃的容忍度，因此SOI技术适用于高效能及高密度的集成电路。
上述MOSFET的操作是经由在源极与漏极之间的沟道区域通过电流。该沟道区域的导电性是藉由施加电压于位于沟道表面上方的导电栅极而控制。为了增加MOSFET的性能，许多研究皆朝向改良SOI MOSFET的驱动电流速度发展，以谋求半导体器件的稳定性，同时减低电力消耗。
目前一般MOS晶体管的驱动电流是如图1所示的表面反转层(surface-inversion layer)14。其中，当一电压施加于栅极13时，形成于沟道尾端的源极11与漏极12之间的表面反转层14是做为驱动电流的路径。然而，在该表面反转层仅能提供有限的电流的情形下，必须制造出能够预防短沟道效应、漏极导致表面电位降低(drain-induced barrierlowering；DIBL)以及次门槛斜率的降低的SOI MOSFET。
发明内容
有鉴于此，本发明的目的在于提供一种近环绕栅极，以及制作具有该近环绕栅极结构的绝缘体上有硅的半导体器件的方法，其中该环绕栅极结构是体积反转(volume-inversion)，所谓体积反转是指不仅在半导体的表面的表层沟道(surface channel)有反转，在半导体层容积内以及半导体层两侧皆有反转。藉由该环绕栅极结构，可大幅增加沟道电流，进而提升半导体组件的操作速度，并能达到预防短沟道效应、漏极感应阻障降低以及次门槛斜率的降低的效果。
此外，本发明的新颖的近环绕栅极结构SOI半导体器件可使用现有的SOI芯片以及制程。而本发明的具有近环绕栅极结构的MOSFEET可结合传统MOS制程与已广为接受的SOI技术而制造的。因此本发明的具有近环绕栅极的半导体器件可以现有的整体(bulk)或SOI MOSFET技术，而不需额外或复杂的制程。
根据本发明的制造具有近环绕栅极结构的半导体结构的方法，其包括下列步骤：(a)在一半导体基底上经由第一绝缘层形成一半导体层；(b)在该半导体层上形成第一氧化层；(c)在该第一氧化层上形成第一牺牲氮化物层；(d)以微影技术将该第一牺牲氮化物层、第一氧化层、以及该半导体层图案化而形成岛状或长条状；(e)在该岛状或长条状的半导体层周围形成第二氧化层；(f)剥离该第一牺牲氮化物层；(g)沉积第二牺牲氮化物层；(h)以该第二牺牲氮化物层为掩模，以一既定距离蚀刻至该第1绝缘层，并蚀刻该第二氧化层；(I)在该半导体层周围形成绝缘材料；(j)。以该第二牺牲氮化物层为掩模，而沉积多晶硅；(k)移除该第2牺牲氮化物层而形成一栅极；以及(l)以该栅极为掩模在该半导体层植入与该半导体基底相反导电性的掺杂离子而形成源/漏极区。
本发明提供一种近环绕的栅极结构，该结构主要具有第一绝缘层；位于该第一绝缘层上的亚微米厚度(submicron-thick)的半导体层，其中该半导体层具有通常是内部的主体沟道区域(bulk channel region)；环绕该半导体层的栅极绝缘层，以及几乎整个围绕该栅极绝缘层的栅极，其中该栅极是嵌入于该第一绝缘层。
本发明提供另一种近环绕的栅极结构，该结构主要具有第一绝缘层；位于该第一绝缘层上的亚微米厚度的半导体层，其中该半导体层具有通常是内部的主体沟道区域；环绕该半导体层的栅极绝缘层，以及围绕该栅极绝缘层的栅极，其中该栅极是位于该第一绝缘层的表面上。
根据本发明的制造具有近环绕栅极结构的半导体结构的方法，该方法可以一个SOI结构或一个半导体基底开始，于该半导体基底上经由第一绝缘层形成半导体层，再依序形成第一氧化层以及第一牺牲氮化物层。接着，藉由微影技术将上述半导体层、第一氧化层以及第一牺牲氮化物层形成岛状或长条状。
接着，在该半导体层周围形成第二氧化层而使该半导体层的角落圆滑，藉此可改善栅极绝缘崩溃特性(gate insulator breakdowncharacteristics)，并可避免经由栅极绝缘的电场强化沟道(field-enhanced tunneling through the gate dielectric)。上述形成氧化层的步骤可以一般方法进行，例如沉积或者热氧化。
然后，剥离该第一牺牲氮化层，再形成一第二牺牲氮化层并图案化，以该第二牺牲氮化物层为掩模以既定距离蚀刻第一绝缘层，该既定距离的较佳范围为10-100nm。然而，该既定距离并无特别限制，亦可为零，也就是说仅蚀刻至第一绝缘层表面为止，如此最后就能形成另一种近环绕栅极结构。此时，上述用来圆滑半导体层角落的氧化层亦被蚀刻移除。同样的，本发明的剥离或蚀刻方法并无特别限制，可使用一般剥离/蚀刻方法。
接着，在该半导体周围形成绝缘材料层，该绝缘材料为选自二氧化硅、氮化硅、氧氮化硅以及高介电常数(dielectric constant；K)的绝缘材料等。然后沉积栅极材料，例如多晶硅。该栅极材料并不限于多晶硅，任何传统制程中所使用的栅极材料皆可。其次，可使用一平坦化技术，例如但不限于化学机械研磨(CMP)或有机材料沉积或是反应离子蚀刻(RIE)，来平坦化栅极材料表面。
此时，因为整个器件的微小尺寸，从该栅极的电场线将结束于该器件的后部，因而可做为一个实质上的后栅极(back gate)。接着再移除第二牺牲氮化层。
最后，以一般制作MOSFET的方法形成源/漏极区而成。
在本发明的近环绕栅极结构中，该半导体层的厚度较佳为＜200nm。
本发明的近环绕栅极是形成于一SOI结构上，较佳是在一埋藏有氧化层的整体(bulk)半导体基底上。根据本发明所得的MOSFET可避免短沟道效应并可提供比习知MOSFET更佳的驱动电流。
附图说明
以下，就图式说明本发明的具有近环绕闸极结构的SOI MOSFET器件的实施例。
图1显示传统的表面反转的SOI MOSFET；
图2显示本发明实施例的近环绕栅极的结构；
图3显示根据本发明实施例的另一近环绕栅极结构；
图4至图10显示本发明的实施例中，制作具有近环绕栅极结构的SOIMOSFET的剖面图。
图号说明：
半导体基底-45；
绝缘层-21、31、41；
半导体层-22、32、42；
栅极绝缘层-23、33；
栅极-24、34；
第一氧化层-43；
第二氧化层-43α；
第一牺牲氮化层-44；
第二牺牲氮化层-71、72；
既定距离-73；
绝缘材料-81；
多晶硅-91。
具体实施方式
请参阅图4至图10，其显示根据本发明的制作具有近环绕栅极结构的SOI MOSFET半导体器件的方法制作N沟道器件的实施例，不过只要在植入对应的离子时，适当地改变掺杂的极性或导电性，相同的原理也可用于制作P沟道器件。
首先，请参阅图4与图5，在一例如是P型的半导体基底45上经由第一绝缘层41(SiO2)形成半导体层42，在该半导体层42上再依序形成第一氧化层43以及第一牺牲氮化层44(Si2N4)。之后以微影技术将该半导体层42、该第一氧化层43及该第一牺牲氮化层44图案化而使其变成长条状。
接着，请参阅图6，在该半导体层42周围形成第二氧化层43α，使得该半导体层42的角落圆滑。然后请参阅图7，先剥离该第一牺牲氮化层44，之后形成第二牺牲氮化层71、72，并将其图案化。接着，使用图案化后的该第二牺牲氮化层71、72为掩模，以既定距离73蚀刻至该第一绝缘层41中，该既定距离73可以为0，但最好是10-110nm。此时，第二氧化层43α亦被蚀刻移除，而使该半导体层42的角落圆滑。
其次，请参阅图8，在该半导体层42周围以一绝缘材料氧化硅形成绝缘材料81。之后请参阅图9，再沉积多晶硅91而做为栅极材料，并以CMP(化学机械研磨法)将多晶硅91表面平坦化。
请参照图10，此时，使用适当的蚀刻技术将第二牺牲氮化层71、72移除，再以当作是栅极电极的多晶硅91为掩模，于半导体层42中形成源/漏极区，其形成方法例如是采用离子植入的技术，还有使用的掺杂离子可以是p型或n型的离子，其中p型离子例如是硼，n型离子例如是磷或砷。也就是说，植入该半导体层42的掺杂离子的电性必须是相反于该半导体基底45的电性。
根据上述制造方法，就能够制造出本发明的近环绕的栅极结构。图2是显示本发明的一种近环绕的栅极结构，该结构主要具有第一绝缘层21；位于该第一绝缘层21上的亚微米厚度(submicron-thick)的半导体层22，其中该半导体层22具有通常是内部的主体沟道区域(bulk channel region)；环绕该半导体层22的栅极绝缘层23，以及几乎整个围绕该栅极绝缘层23的栅极24，其中该栅极24是嵌入于该第一绝缘层21。
这里要说明的是，若将图6中的该既定距离73设定为0的话，就能够形成如图3所显示的本发明的另一种近环绕的栅极结构。该结构主要具有第一绝缘层31；位于该第一绝缘层31上的亚微米厚度的半导体层32，其中该半导体层32具有通常是内部的主体沟道区域；环绕该半导体层32的栅极绝缘层33，以及围绕该栅极绝缘层33的栅极34，其中该栅极34是位于该第一绝缘层31的表面上。图2所示的本发明的近环绕栅极结构，其中栅极电极23几乎整个围绕沟道区域，而该沟道区域明显地大于在半导体表面具有表面反转的熟知晶体管，因此本发明的半导体器件可提供的驱动电流的确大幅增加。藉由本发明的近环绕栅极结构，可避免从栅极电极发出的电场现在沟道区域下方终止，而减少短沟道效应。
虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，可作适当的更改，因此本发明的保护范围以权利要求所界定的保护范围为准。
Claims (5)
1.一种制作具有近环绕栅极的硅半导体器件的方法，该方法包括下列步骤：
(a).在一半导体基底上经由第一绝缘层形成一半导体层；
(b).在该半导体层上形成第一氧化层；
(c).在该第一氧化层上形成第一牺牲氮化物层；
(d).以微影技术将该第一牺牲氮化物层、第一氧化层、以及该半导体层图案化而形成岛状或长条状；
(e).在该岛状或长条状的半导体层周围形成第二氧化层；
(f).剥离该第一牺牲氮化物层；
(g).沉积第二牺牲氮化物层；
(h).以该第二牺牲氮化物层为掩模，以一既定距离蚀刻至该第一绝缘层，并蚀刻该第二氧化层；
(I).在该半导体层周围形成绝缘材料；
(j).以该第二牺牲氮化物层为掩模，而沉积多晶硅；
(k).移除该第二牺牲氮化物层而形成一栅极；以及
(l).以该栅极为掩模在该半导体层植入与该半导体基底相反导电性的掺杂离子而形成源/漏极区。
2.根据权利要求1所述的方法，其中该第一绝缘层是SiO2层。
3.根据权利要求1所述的方法，其中该既定距离是0或10-110nm。
4.根据权利要求1所述的方法，其中步骤(1)还包括以离子植入法形成源/漏极延伸区。
5.一种近环绕的栅极结构，其包括：
第一绝缘层；
半导体层，位于该第一绝缘层上，且该半导体层图案化为一岛状或长条状；
栅极绝缘层，围绕该岛状或长条状的半导体层；以及
栅极，包围该栅极绝缘层并延伸至该第一绝缘层。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/761,889 US6359311B1 (en) | 2001-01-17 | 2001-01-17 | Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same |
| US09/761,889 | 2001-01-17 |
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| CN1172357C true CN1172357C (zh) | 2004-10-20 |
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| US (1) | US6359311B1 (zh) |
| CN (1) | CN1172357C (zh) |
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