CN1103497C - 使用局部选择氧化在绝缘体上形成的体硅和应变硅 - Google Patents

使用局部选择氧化在绝缘体上形成的体硅和应变硅 Download PDF

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CN1103497C
CN1103497C CN98121348A CN98121348A CN1103497C CN 1103497 C CN1103497 C CN 1103497C CN 98121348 A CN98121348 A CN 98121348A CN 98121348 A CN98121348 A CN 98121348A CN 1103497 C CN1103497 C CN 1103497C
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杰克·奥恩·楚
哈里德·泽尔丁·伊斯梅尔
基姆·杨·李
约翰·阿尔布里奇特·奥特
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Abstract

一种形成单晶半导体层下掩埋氧化区的方法，包括形成氧化速率与具有较快氧化速率的下层不同的外延层和通过掩模内的开口氧化这些层的步骤。可以形成多个氧化物隔离的FET。本发明减少了源/漏寄生电容和短沟道效应，同时通过选择性氧化半导体层隔离FET并消除了FET的浮体效应。

Description

使用局部选择氧化在绝缘体上形成 的体硅和应变硅
技术领域
本发明涉及在绝缘体上或与之邻接形成体或应变的Si/SiGe层区域，特别涉及局部选择氧化SiGe形成用于器件应用的半导体区下的绝缘区，器件的应用例如互补金属氧化物半导体(CMOS)场效应晶体管(FET)、调制掺杂场效应晶体管(MODFET)、动态随机存取存储器(DRAM)、混合的DRAM和CMOS、静态随机存取存储器(SRAM)、BiCMOS、rf等。
背景技术
在硅半导体技术中，获得绝缘衬底的唯一方式是借助绝缘体上的硅(SOI)、蓝宝石上硅(SOS)、或者腐蚀或重新粘接以获得SOI。在CMOS和高速FET中使用绝缘衬底的主要优点是减少了寄生结电容和短沟道效应，由此增加了器件的速度性能。所有以上方法的一个主要问题是绝缘体覆盖了整个晶片，因此覆盖了包括下面的欧姆接触和FET沟道的整个器件区。整个晶片上的掩埋氧化物导致公知的‘浮体’问题，因为半导体衬底相对于沟道浮动。该问题负面地影响了阈值电压控制和电路工作。以上解决方案的另一问题是它们比常规的体硅衬底昂贵得多。此外，没有简单的方式获得具有较高电子和空穴传输特性的绝缘体上的应变硅。
发明内容
本发明的目的在于以低成本提供没有“浮体”缺陷的掩埋氧化物形成方法。
本发明的另一目的是提供具有高电子和空穴传输特性的绝缘体上应变硅结构。
根据本发明，在单晶半导体层的区域下形成掩埋氧化区的方法包括以下步骤：选择单晶硅衬底，在具有第一氧化速率的衬底上表面上形成不变或渐变的SiGe的第一外延层。该层可以是应变的或弛豫(relaxed)的SiGe或晶格匹配的SiGeC。然后在具有小于第一氧化速率的第二氧化速率的第一层上形成含硅的第二外延层，在第二层上形成掩模，构图掩模以在掩模内形成开口，通过掩模开口氧化第二层和第一层，由此形成具有代替部分或所有第二层下的第一层的部分的氧化区。
本发明还提供形成FET，它的沟道位于第一层剩余部分之上的第二层内。
通过使用本发明，可消除绝缘体覆盖整个晶片所导致的“浮体”缺陷，可有效抑制加工成本，并且本发明的绝缘体上应变硅结构能够获得较高的电子和空穴传输性能。
当结合附图研究本发明下面的详细说明时，本发明的这些和其它特点、目的和优点将变得显而易见。
附图说明
图1和2为示出实施本发明步骤的叠层结构的剖面图。
图3为示出本发明的一个实施例氧化步骤后沿图2的线3-3截取的剖面图。
图4为在不同的温度和环境硅的氧化速率与硼浓度的曲线图。
图5为图3示出的实施例的所制备样品的TEM；以及
图6为本发明第二实施例的截面图，示出多个FET。
图7为去除氧化步骤期间形成的氧化物的附加步骤的层结构截面图。
图8为示出氧化的附加步骤的剖面图。
具体实施方式
参考图1，显示的叠层结构12的截面图示出了初始工艺步骤。首先，选择单晶半导体衬底14，可以为Si、SiGe等。接下来，在衬底14的上表面15上形成不变或渐变的Si1-xGex或(Si1-xGex)aC1-a的外延层16。为说明生长含硅膜的UHV-CVD方法，参考B.S.Meyerson的US专利No.5,298,452，于1994年3月29日发表，题目为“Method and Apparatusfor Low Temperature，Low Pressure Chemical Vapor Deposition ofEpitaxial Silicon Layers”，在这里引入做参考。外延层16具有的Ge的X含量在0.15到0.25范围内。外延层16具有在特定温度和环境的热氧化第一速率。环境可以包括氧气、水蒸气和/或HCl。即使在层14和16具有不同的晶格常数的位置，也需要外延生长不变或渐变组分的外延层16，并选择具有第一热氧化速率。将外延层16的厚度调节到低于或高于临界厚度以分别提供应变的或弛豫的层。为了说明SiGe的弛豫层的形成，参考F.K.LeGoues和B.S.Meyerson的US专利No.5,659,187，于1997年8月19日发表，题目为“Low Defect Density/Arbitrary Lattice ConstantHeteroepitaxial Layers”，在这里引入做参考。
接下来Si或Si1-YGeY的外延层20形成在外延层16的上表面17上。外延层20具有不变或渐变的Ge含量Y，其中Y小于X，并且可以为零。选择层20的组分以便层20具有小于层16的氧化速率的第二氧化速率，并具有需要的电特性。
接下来，将掩模24形成在层20的上表面21上。掩模24可以是氮化硅或如慢氧化或抗氧化材料的其它材料或已为氧化物的材料的覆盖层。氮化硅为优选材料，因为相对于氧化物即二氧化硅可以被选择性地除去。构图掩模24形成如图2所示的开口26。开口26可以沿路径或图形延伸以形成图2所示的掩模图形29或多个掩模图形30。掩模图形30可以形成为矩形、方形和/或圆形。通过开口26的图形也可以形成其它形状。掩模图形30可以为尺寸为1μm×1μm以下的多个矩形和/或方形。可以选择掩模图形和尺寸以便接纳完全由氧化物环绕的Si或SiGe的单独区域上的一个器件，SiGe的剩余部分与衬底14接触或者SiGe完全不与衬底14接触。
接下来，叠层结构12放置在氧化环境中，在某温度下通过开口26氧化外延层16和20，因此氧化了掩模图形30的周边。根据SiGe中Ge的三维组分的分布，层16和20中硼的三维掺杂的分布和氧化时间，形成氧化物33和34如图3所示，氧化物33和34终止于中止层16’内或延伸穿过层16’并终止在衬底14内。氧化环境可以为水蒸气、氧气和/或盐酸中的湿热氧化，温度范围从700℃～950℃，优选在700℃到800℃的范围。例如在750℃，Si的氧化速率在0.5～1nm/min的范围。具有7％Ge的SiGe氧化速率约3.5nm/min。具有16％Ge的SiGe氧化速率约5.2nm/min。具有53.5％Ge的SiGe氧化速率约44nm/min。具有76.6％Ge的SiGe氧化速率约66nm/min。有关SiGe的氧化速率与温度的函数关系以及用于快速热干和湿氧化(RTO)的组分的函数关系的更多数据，可以参考U.Konig和J.Hersener的出版物，题目为“Needs of Low Thermal Budget Processing inSiGe Technology”，Solid State Phenomena，卷47-48(1996)17-32页，由瑞士的Scitec Publications出版。
图3为通过图2所示的开口26氧化掩模29的边缘周围的外延层16和20后沿图2的线3-3的剖面图。如图3所示，除了掩模图形29以下，外延层20完全由氧化区33和34消耗。开口26下的外延层16几乎或全部消耗，并在层20’下层16内横向延伸。形成的氧化物为SirGesO2，其中r和s为0到2范围内的值，取决于层16内Ge含量与厚度的函数关系和氧化条件。
氧化物33和34在层16内层20’下延伸，其中层16’的氧化速率大于层20’的氧化速率，层20’的氧化速率由SiGe中Ge的渐变和硼的掺杂分布(如果存在的话)控制。可以掺杂硼达到1021原子/cc以增强SiGe的氧化。锗的量提供了氧化速率的相应增加。硼的量提供了如图4所示的氧化速率的相应增加。在图4中，纵坐标代表氧化速率(埃/min)，横坐标代表硼浓度(cm-3)。曲线41显示出在700℃氧气中1个大气压力下硅氧化速率与硼浓度的函数关系。曲线42显示出在600℃氧气和水蒸气中10个大气压力也称做高压氧化(HIPOX)下硅氧化速率与硼浓度的函数关系。曲线43显示出在700℃氧气和水蒸气中10个大气压力下硅氧化速率与硼浓度的函数关系。HIPOX可以发生在含氧的环境中在1到20个大气压力范围内的压力，通常为12个大气压力。Ge和B的存在提供了氧化速率的累积增加。由此层16内SiGe中Ge组分的三维分布和层14、16和20中硼浓度的三维分布提供了作为时间函数的氧化物33和34的周边表面或前缘35和36的预定分布。箭头37和38示出了在掩模图形29下延伸的氧化物33和34的各自长度l1和l2。相对于掩模图形29层20’也被氧化，但由于较低的氧化速率在掩模图形29下延伸少得多。对于Si和SiGe层的氧化，所得氧化材料的厚度如图3所示增加(没有按比例)。
通过继续与时间成函数关系的一个或多个温度的氧化步骤，可以确定或控制l1和l2，在层16和20的生长平面内对于不变组分l1和l2相等。同样可以确定或控制箭头39示出的间距d。间距d允许层20’通过层16’与衬底14欧姆接触，以控制在层20’内形成的场效应晶体管本体上的电压，由此可以防止由堆积的电荷造成的浮体效应。一般来说，间距d小于FET的栅长度。当层20’与衬底14电隔离间距d为零的情况下，氧化物33和34可以结合在一起。
图5为图3实施例的制备样品的透射电子显微镜(TEM)图。图5的显示与图3中基本上对应。在图5中，l1和l2约0.17μm。间距d约0.15μm。掩模图形29的宽度为0.5μm。在图5中，使用了图3中器件的相同参考数字，并相对于图3引入了相同的材料。
图6为FET52和53的剖面图。在图6中，与图3所示的相同结构元件使用了相同的参考数字。去除可以为氮化硅的掩模图形29(未显示)。如二氧化硅的栅介质56可以形成在分别用于晶体管52和53的层20’上。多晶硅层可以形成在栅介质56上并构图形成分别用于晶体管52和53的栅电极57。使用栅电极57，可以通过离子注入形成源区60和漏区61，形成延伸到氧化物32、33和34上表面的欧姆接触注入。在形成自对准欧姆接触注入之前，在栅电极57的侧壁上形成栅侧壁间隔层(未显示)。由于延伸到氧化物32、33和34的欧姆接触，与层16’的寄生结电容减少，是由于除了不存在p-n结，与Si相比氧化物的介质常数低三倍。对于0.13μm的沟道宽度，源区60和漏区61的寄生结电容小于0.02fF/μm2。通过定出源区60和漏区61下氧化物32、33和34的位置，随着漏偏压增加，可以防止耗尽区延伸进入沟道内，短沟道效应减少。FET52可以为n型并且FET53可以为p型形成CMOS电路。通过在离子注入期间划分出保留用于相反掺杂剂的其它FET，每个FET源和漏可以用合适的掺杂剂掺杂。CMOS电路在本领域已公知，其中一个FET的漏区通过引线66连接到另一个FET的源区形成输出。栅电极通过引线67连接起来形成输入。地和电源电压通过引线68和69连接到各FET的剩余源和漏。
图7为除了氧化物33和34除去之外与图3所示的结构类似的层叠结构70的剖面图。通过如用缓冲的HF腐蚀除去氧化物33和34。
除去氧化物33和34之后，露出的层14、16’和20’暴露到氧化环境，重新开始层16’的氧化，并根据氧化速率氧化较小程度的层14和20’。氧化物33和34起阻止或降低层16’氧化的作用。由此除去氧化物33和34，加速了层16’的氧化。
图8为衬底14和层16’和20’进一步氧化为所示的氧化区77和78后层叠结构74的剖面图。
去除氧化物和在氧化环境中氧化层叠结构的步骤重复多次。形成需要的结构后，可以使用如硅氧化物的介质填充在除去氧化物形成的空隙中。可以使用化学机械工艺形成平面的上表面用于进一步的处理以形成有用的半导体器件。
在图7和8中，与图3的器件对应的结构使用了相同的参考数字。
虽然已介绍和示出了在单晶半导体层的区域下形成掩埋氧化区的工艺，该半导体层与衬底和亚微米沟道长度的FET结构的欧姆接触应变或弛豫，用于器件和电路应用例如CMOS、MODFET、DRAM、SRAM、rf、BiCMOS和混合的DRAM和CMOS，在不脱离仅由附带的权利要求书的范围限定的本发明的广阔范围，本领域的技术人员显然可以做出修改和变形。

Claims (44)

1.一种在单晶半导体层的区域下形成掩埋氧化区的方法，包括步骤：
选择单晶硅衬底，
在所述衬底的上表面上形成由Si1-xGex或(Si(1-x)Gex)aC1-a构成的第一外延层，所述第一外延层具有第一氧化速率，
在所述第一外延层上形成含硅的第二外延层，所述第二外延层具有小于所述第一氧化速率的第二氧化速率，
在所述第二外延层上形成掩模，
构图所述掩模以在所述掩模内形成掩模开口，以及
通过所述掩模开口氧化所述第二外延层和所述第一外延层，由此在所述第一和第二外延层内形成氧化区，且所述氧化区的一部分代替了所述第二外延层下的那部分所述第一外延层。
2.根据权利要求1的方法，特征在于所述氧化步骤继续一段时间形成所述氧化区，且所述氧化区的所述部分在所述第二外延层下延伸预定距离。
3.根据权利要求2的方法，特征在于还包括使两个掩模开口分开定位的步骤，以在所述第二外延层下提供由预定距离隔开的所述氧化区的两个各自的部分。
4.根据权利要求1的方法，特征在于所述掩模开口中的一个沿路径延伸形成掩模图形。
5.根据权利要求4的方法，特征在于所述掩模图形选自由矩形、方形和圆形组成的组中。
6.根据权利要求1的方法，特征在于所述掩模开口使所述掩模形成为分别对应于有源MOS器件尺寸的多个矩形。
7.根据权利要求6的方法，特征在于所述掩模形成的所述多个矩形为1μm×1μm以下。
8.根据权利要求6的方法，特征在于所述氧化步骤继续一段时间以在所述未氧化的第一外延层的所述各矩形的中心内留下有限的面积。
9.根据权利要求8的方法，特征在于还包括在所述第二外延层内形成源和漏区以限定出所述第一外延层的所述有限面积上两者之间的沟道以避免FET的浮体效应的步骤。
10.根据权利要求9的方法，特征在于还包括在所述沟道上形成栅介质和栅电极以便形成所述FET的步骤。
11.根据权利要求8的方法，特征在于还包括在所述氧化区上所述源和漏区内形成欧姆接触离子注入由此减少寄生结电容的步骤。
12.根据权利要求1的方法，特征在于所述氧化步骤包括在700℃到800℃温度范围内的湿热氧化。
13.根据权利要求1的方法，特征在于所述氧化步骤包括在650℃到800℃温度范围内的高压氧化(HIPOX)。
14.根据权利要求1的方法，特征在于还包括除去由所述氧化步骤形成的部分所述氧化物的步骤。
15.根据权利要求14的方法，特征在于还包括基本上除去由所述氧化步骤形成的全部所述氧化物的步骤。
16.根据权利要求14的方法，特征在于还包括所述除去步骤后继续所述氧化步骤的步骤。
17.根据权利要求16的方法，特征在于还包括重复多次所述除去和氧化步骤的步骤。
18.根据权利要求1的方法，特征在于所述形成掩模的步骤包括形成氮化硅层的步骤。
19.根据权利要求1的方法，特征在于形成所述第一外延层的所述步骤包括形成渐变组分的层。
20.根据权利要求19的方法，特征在于形成所述第一外延层的所述步骤包括形成具有晶格参数大于所述第二层的晶格参数的上表面的层，以提供所述第二层内的抗拉应变。
21.根据权利要求1的方法，特征在于形成所述第一外延层的所述步骤包括生长所述第一外延层直到其晶格常数弛豫到大于要形成的所述第二外延层的晶格常数的步骤，由此在抗拉应变下形成所述第二外延层时具有高电子和空穴迁移率。
22.根据权利要求1的方法，特征在于所述氧化步骤继续一段时间形成所述氧化区向下延伸到所述衬底内。
23.根据权利要求1的方法，特征在于还包括用硼掺杂所述第一外延层的区域以促进氧化速率的步骤。
24.根据权利要求1的方法，特征在于所述第一外延层Ge的组分渐变以促进氧化速率。
25.一种电子器件形成于其中的结构，包括：
单晶硅衬底，
第一外延层，位于所述衬底的上表面上，由Si1-xGex或(Si(1-x)Gex)aC1-a构成，
所述第一外延层上含硅的第二单晶层，以及
第一和第二氧化区相互分开，每个所述第一和第二氧化区在所述第二单晶层下所述第一外延层内延伸。
26.根据权利要求25的结构，特征在于所述第一和第二氧化区形成在所述第一外延层和所述第二单晶层内。
27.根据权利要求25的结构，特征在于所述第一和第二氧化区在所述第一外延层内分隔开0.01到0.5μm的范围。
28.根据权利要求25的结构，特征在于所述第一和第二氧化区包围部分所述第二单晶层。
29.根据权利要求28的结构，特征在于所述第二单晶层的所述包围部分在它的上表面形成选自矩形、方形和圆形组成的组中的形状。
30.根据权利要求29的结构，特征在于还包括多个所述第二单晶层的所述包围部分，每个所述第一层的所述包围部分小于1μm×1μm。
31.根据权利要求28的结构，特征在于所述第一和第二氧化区之间的所述第一外延层在所述第二单晶层的所述包围部分下面并与之接触。
32.根据权利要求25的结构，特征在于所述第一外延层包括Ge的组分渐变层。
33.根据权利要求25的结构，特征在于所述第一外延层包括硼掺杂。
34.根据权利要求25的结构，特征在于由于所述第一外延层的上表面的晶格参数，所述第二单晶层处于应力变形。
35.根据权利要求25的结构，特征在于所述第一和第二氧化区延伸穿过所述第一外延层进入所述衬底。
36.根据权利要求25的结构，特征在于还包括所述第二单晶层内分隔开的源和漏区，分别向下延伸到所述第一和第二氧化区的上表面，限定出所述第二单晶层内的沟道。
37.根据权利要求36的结构，特征在于还包括所述沟道上的介质和所述介质上的栅电极以形成场效应晶体管。
38.根据权利要求37的结构，特征在于还包括与所述源和漏的欧姆接触，延伸到所述第一和第二氧化区的上表面。
39.根据权利要求37的结构，特征在于所述沟道处于应力变形。
40.根据权利要求37的结构，特征在于所述第一外延层具有对应于所述第二单晶层内所述沟道晶格应变的Ge的渐变组分。
41.根据权利要求37的结构，特征在于所述第一外延层弛豫。
42.根据权利要求37的结构，特征在于所述第二单晶层与所述第一外延层相当。
43.根据权利要求37的结构，特征在于还包括分别为n型和p型的多个所述场效应晶体管。
44.根据权利要求43的结构，特征在于还包括形成互补金属氧化物半导体(CMOS)电路的互连布线。
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