CN104465351A - Method for improving metal silicide - Google Patents
Method for improving metal silicide Download PDFInfo
- Publication number
- CN104465351A CN104465351A CN201410710161.XA CN201410710161A CN104465351A CN 104465351 A CN104465351 A CN 104465351A CN 201410710161 A CN201410710161 A CN 201410710161A CN 104465351 A CN104465351 A CN 104465351A
- Authority
- CN
- China
- Prior art keywords
- fluorine
- layer
- doped silica
- substrate
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 81
- 239000002184 metal Substances 0.000 title claims abstract description 81
- 238000000034 method Methods 0.000 title claims abstract description 57
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 33
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 96
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 41
- 239000010703 silicon Substances 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 29
- 239000011737 fluorine Substances 0.000 claims abstract description 28
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 28
- 238000000137 annealing Methods 0.000 claims abstract description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 10
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 43
- 238000010438 heat treatment Methods 0.000 claims description 16
- 238000012545 processing Methods 0.000 claims description 15
- 239000002905 metal composite material Substances 0.000 claims description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 8
- 239000003921 oil Substances 0.000 claims description 8
- 230000002940 repellent Effects 0.000 claims description 8
- 239000005871 repellent Substances 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 5
- 239000010941 cobalt Substances 0.000 claims description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 5
- 239000000428 dust Substances 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 230000000717 retained effect Effects 0.000 claims description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 69
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 abstract description 27
- 239000004065 semiconductor Substances 0.000 abstract description 10
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910021334 nickel silicide Inorganic materials 0.000 abstract description 5
- 238000012421 spiking Methods 0.000 abstract description 4
- 238000005457 optimization Methods 0.000 abstract description 3
- 239000011241 protective layer Substances 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract 1
- 238000000151 deposition Methods 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005518 electrochemistry Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention relates to the field of optimization of semiconductor devices, in particular to a method for improving metal silicide. After the grid electrode of a silicon substrate is formed, a layer of fluorine-doping silicon oxide (FSG) is deposited, then silicon nitride is deposited, and a side wall is formed through dry etching. After the device is formed, silicon nitride is deposited as an SAB mask, and silicon nitride covering the place with metal silicide needing to be formed is selectively removed through exposure, developing and etching. A metal layer and protective layer silicon nitride are deposited, and secondary annealing is carried out to form nickel silicide. Fluorine in the side wall is diffused to substrate silicon through subsequent annealing, the fluorine content in the substrate silicon is increased, and the possibility of occurrence of Ni piping and spiking is lowered.
Description
Technical field
The present invention relates to semiconductor device piece optimization field, particularly relate to a kind of method improving metal silicide.
Background technology
In integrated circuit and silicon device technique, silicaization is generally all carried out under the hot conditions of about 1000 DEG C, and under these conditions, silicon chip often there will be the problems such as dopant redistribution, hot induced defects and warpage.Therefore, bringing serious hindrance to reducing further of integrated circuit (IC)-components size, in order to adapt to the needs of large scale integrated circuit, reducing the impact of these factors, silicon chip need adopt cryogenic conditions to be oxidized.But the low temperature oxidation technology of routine, when temperature is less than or equal to 800 DEG C, oxidation rate is too slow, can not apply.Therefore, a kind of sample plasma mingling fluorine and oxidation metlhod once reported by electrochemistry magazine, can improve the oxidation rate of silicon chip in this way under cryogenic, and then it but introduces such as high-energy radiation damage defect, and the quality of oxide layer can not be satisfactory.In addition, the remote plasma precleaning (NF of Applied Materials's invention
3+ NH
3remote plasma pre-clean), utilizing remote plasma precleaning while the natural oxidizing layer removing S/D surface, the Oil repellent in base silicon can be increased, compared to DHF wet clean, remote plasma precleaning is adopted can effectively to improve Ni piping and spiking.
Chinese patent (CN 1033545A) describes one and mixes fluorine, cryogenic silicon oxidation method, adopting fluid, fluorine-containing reagent for mixing fluorine source, carrying by carrying gas, oxygen dilution, conventional thermal oxidation stove is utilized to realize mixing fluorine, low temperature 800 DEG C or lower than 800 DEG C of silica.
Above-mentioned patent does not make referrals to and deposit fluorine-doped silica layer on semiconductor junction component, is made the technical characteristic of the basad diffusion of the fluorine in fluorine-doped silica layer by annealing process.
Summary of the invention
For the problems referred to above, the present invention relates to a kind of method improving metal silicide, it is characterized in that, comprise the following steps:
Step S1, provide one to be preset with substrate that metal silicide prepares district, forms grid structure on described substrate;
Step S2, deposition fluorine-doped silica layer covers the surface of described silicon substrate and the exposure of described grid structure, prepares the upper surface that silicon nitride layer covers described fluorine-doped silica layer;
Step S3, continues hot first annealing process, to diffuse in described substrate by the fluorine in described fluorine-doped silica layer;
Step S4, remove the described fluorine-doped silica layer of part and silicon nitride layer, all to be exposed by the upper surface being arranged in substrate and described grid structure that described metal silicide prepares district, and the fluorine-doped silica layer retained on gate structure sidewall and silicon nitride layer are as side wall;
Step S5, prepares metal composite layer, and continues the second Technology for Heating Processing, form metal silicide layer to prepare in district in this metal silicide on the substrate surface that the described metal silicide exposed prepares district
Above-mentioned method, is characterized in that, described substrate is silicon substrate.
Above-mentioned method, is characterized in that, described metal composite layer comprises a metal level and is positioned at the nitrided metal layer on described metal level.
Above-mentioned method, is characterized in that, described metal level is the wherein at least one being selected from titanium, cobalt, nickel or platinum.
Above-mentioned method, is characterized in that, described first heat treatment and described second heat treatment are annealing process.
Above-mentioned method, is characterized in that, silicon oxide layer and the described silicon nitride layer of mixing fluorine described in the method removal of employing dry etching form described side wall.
Above-mentioned method, is characterized in that, described in mix the silicon oxide layer of fluorine thickness be 20-100 dust.
Above-mentioned method, is characterized in that, described in the Oil repellent mixed in the silicon oxide layer of fluorine be less than 5%.
Above-mentioned method, is characterized in that, described method also comprises,
First deposit one deck silicon oxide layer, then deposition mixes silicon oxide layer and the silicon nitride layer of fluorine successively.
Above-mentioned method, is characterized in that, described in the Oil repellent mixed in the silicon oxide layer of fluorine be less than 10%.
In sum, owing to have employed technique scheme, the method that a kind of metal silicide that the present invention proposes improves, after the grid of a silicon substrate is formed, deposition one deck mixes the silica of fluorine, then deposited silicon nitride, and forms side wall by dry etching.Depositing metal layers and protective layer silicon nitride, carry out double annealing and form nickel-silicon compound.Fluorine in side wall, by spreading in the basad silicon of follow-up annealing, increases the Oil repellent in base silicon, reduces the possibility that Ni piping and spiking occurs.
Accompanying drawing explanation
Fig. 1-Fig. 5 is the structural representation that the present invention forms metal silicide on semiconductor junction component.
Embodiment
In semiconductor technology, metal-oxide semiconductor, electric crystal are made up of three electrodes such as grid, source electrode and drain electrodes, and wherein MOS is the main body forming grid structure.
Early stage MOS is made up of three-layer-materials such as metal level, silicon dioxide and silicon base.But, because most metal is poor for the adhesive ability of silicon dioxide, so the polysilicon having a better adhesive ability for silicon dioxide just proposes with substituted metal layer.
But, but use the problem that polysilicon resistance value is too high to exist, even if polysilicon is through overdoping, its resistance value is still too high, and the metal level of inapplicable replacement MOS, so just need metal silicide to be located on polysilicon.
For the problems referred to above, namely the present invention designs a kind of optimization method of metal silicide, base silicon deposits one deck and mixes the silicon oxide layer of fluorine as fluorine source, makes to spread in the basad silicon of fluorine by follow-up pyroprocess, increase the Oil repellent of base silicon, thus improve semiconductor structure device.
Describe in detail below in conjunction with preferred embodiment and accompanying drawing
Specific embodiment 1
The present invention relates to a kind of method improving existing nickel silicide, comprising following steps:
As shown in Figure 1, step S1, be preset with on silicon substrate 1 that metal silicide prepares district one and form a grid structure, the grid 3 that this grid structure comprises a grid oxic horizon 2 and is positioned at above this grid oxic horizon 2, grid 3 can metal gate, also can be polysilicon gate, the needs according to practical devices be selected;
As shown in Figure 2, step S2, on the surface of remaining silicon substrate 1, the side of grid 3 upper surface and grid structure deposits one deck fluorine-doped silica layer 4, the thickness preferably 20-100 dust of this fluorine-doped silica layer 4, wherein the content of fluorine is preferably less than 5%, then at surface deposition one silicon nitride layer 5 of this fluorine-doped silica layer 4;
Step S3, carries out the first Technology for Heating Processing, and this Technology for Heating Processing is an annealing process, to diffuse in silicon substrate by the fluorine in fluorine-doped silica layer;
As shown in Figure 3, step S4, the surface adopting the method for dry etching to remove the upper surface of silicon nitride layer 5 and fluorine-doped silica floor 4 to grid 3 and metal silicide to prepare district's silicon substrate 1, remaining silicon nitride layer 5 and fluorine-doped silica layer 4 are as the side wall of this grid structure;
As shown in Figure 4, step S5, the device formed after the above procedure deposits a metal composite layer, the nitrided metal layer 7 that this metal composite layer comprises a metal level 6 and is positioned on metal level 6, namely this metal level 6 cover grid 3 upper surface, side wall surface and side wall both sides silicon substrate 1 surface, and the wherein at least one of the material of this metal level 6 such as titanium, cobalt, nickel or platinum, nitrided metal layer is titanium nitride preferably;
As shown in Figure 5, step S6, proceed the second Technology for Heating Processing processing procedure, preferably with the annealing process of a temperature at about 800 DEG C, then remove nitrided metal layer 7 and metal level 6, make the silicon substrate of side wall both sides form metal silicide 8, and metal level 6 part remaining on side wall and gate surface has neither part nor lot in reaction, maintain the original state, form the semiconductor device with metal silication structure.
Specific embodiment 2
As shown in Figures 1 to 5, the present invention relates to a kind of method improving existing nickel silicide, comprising following steps:
As shown in Figure 1, step S1, be preset with on silicon substrate 1 that metal silicide prepares district one and form a grid structure, the grid 3 that this grid structure comprises a grid oxic horizon 2 and is positioned at above this grid oxic horizon 2, grid 3 can metal gate, also can be polysilicon gate, the needs according to practical devices be selected;
Step S2, on the surface of remaining silicon substrate 1, the side of grid 3 upper surface and grid structure deposits one deck silicon oxide layer (not shown);
As shown in Figure 2, step S3, deposit one deck fluorine-doped silica layer 4 at silica upper surface and form silica composite bed, the thickness preferably 20-100 dust of this fluorine-doped silica layer 4, when forming this silica composite bed, wherein in fluorine-doped silica layer, the content of fluorine is preferably less than 10%, then at surface deposition one silicon nitride layer 5 of this fluorine-doped silica layer 4;
Step S4, carries out the first Technology for Heating Processing, and this Technology for Heating Processing is an annealing process, to diffuse in silicon substrate by the fluorine in fluorine-doped silica layer;
As shown in Figure 3, step S5, the surface adopting the upper surface of the method for dry etching removal silicon nitride layer 5 and fluorine-doped silica floor 4 to grid 3 and metal silicide to prepare district's silicon substrate 1 forms the side wall of this grid structure;
As shown in Figure 4, step S6, the device formed after the above procedure deposits a metal composite layer, the nitrided metal layer 7 that this metal composite layer comprises a metal level 6 and is positioned on metal level 6, namely this metal level 6 cover grid 3 upper surface, side wall surface and side wall both sides silicon substrate 1 surface, and the wherein at least one of the material of this metal level 6 such as titanium, cobalt, nickel or platinum, nitrided metal layer is titanium nitride preferably;
As shown in Figure 5, step S7, proceed the second Technology for Heating Processing processing procedure, preferably with the annealing process of a temperature at about 800 DEG C, then remove nitrided metal layer 7 and metal level 6, make the silicon substrate of side wall both sides form metal silicide 8, and metal level 6 part remaining on side wall and gate surface has neither part nor lot in reaction, maintain the original state, form the semiconductor device with metal silication structure.
Specific embodiment 3
The present invention relates to a kind of method improving existing nickel silicide, comprising following steps:
Step S1, be preset with on silicon substrate that metal silicide prepares district one and form some grid structures, these grid structures comprise a grid oxic horizon and are positioned at the grid above these grid oxic horizons, grid can be metal gate, also can be polysilicon gate, the needs according to practical devices be selected;
Step S2, on the surface of remaining silicon substrate, the side of gate upper surface and grid structure deposits one deck fluorine-doped silica layer, the thickness preferably 20-100 dust of this fluorine-doped silica layer, wherein the content of fluorine is preferably less than 5%, then at surface deposition one silicon nitride layer of this fluorine-doped silica layer;
Step S3, carries out the first Technology for Heating Processing, and this Technology for Heating Processing is an annealing process, to diffuse in silicon substrate by the fluorine in fluorine-doped silica layer;
Step S4, adopt the method for dry etching to remove surface that silicon nitride layer and fluorine-doped silica floor to the upper surface of grid and metal silicide prepare district's silicon substrate forms the side wall of these grid structures;
Step S5, the device formed after the above procedure deposits one deck silicon nitride, and when needing in part of devices to form metal silicide region, optionally exposure is etched away the silicon nitride layer of these device areas;
Step S6, the device formed after the above procedure deposits a metal composite layer, this metal composite layer comprises a metal level and is positioned at the nitrided metal layer on metal level, namely this metal level 6 cover grid upper surface, side wall surface and side wall both sides silicon substrate 1 surface, and the wherein at least one of the material of this metal level such as titanium, cobalt, nickel or platinum, nitrided metal layer is titanium nitride preferably;
Step S7, proceed the second Technology for Heating Processing processing procedure, preferably with the annealing process of a temperature at about 800 DEG C, then nitrided metal layer and metal level is removed, the silicon substrate of side wall both sides is made to form metal silicide, and the metal layer part remaining on side wall and gate surface has neither part nor lot in reaction, maintain the original state, form the semiconductor device with metal silication structure.
The method that a kind of metal silicide that the present invention proposes improves, after the grid of a silicon substrate is formed, deposition one deck mixes the silica (FSG) of fluorine, then deposited silicon nitride, and forms side wall by dry etching.After device is formed, deposited silicon nitride, as SAB mask, needs to form the place of metal silicide, removes through exposure imaging Etch selectivity the silicon nitride covered on it.Depositing metal layers and protective layer silicon nitride, carry out double annealing and form nickel silicide.Fluorine in side wall, by spreading in the basad silicon of follow-up annealing, increases the Oil repellent in base silicon, reduces the possibility that Ni piping and spiking occurs.
By illustrating and accompanying drawing, giving the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (10)
1. improve a method for metal silicide, it is characterized in that, comprise the following steps:
Step S1, provide one to be preset with substrate that metal silicide prepares district, forms grid structure on described substrate;
Step S2, deposition fluorine-doped silica layer covers the surface of described silicon substrate and the exposure of described grid structure, prepares the upper surface that silicon nitride layer covers described fluorine-doped silica layer;
Step S3, carries out the first Technology for Heating Processing, to diffuse in described substrate by the fluorine in described fluorine-doped silica layer;
Step S4, remove the described fluorine-doped silica layer of part and silicon nitride layer, all to be exposed by the upper surface being arranged in substrate and described grid structure that described metal silicide prepares district, and the fluorine-doped silica layer retained on gate structure sidewall and silicon nitride layer are as side wall;
Step S5, prepares metal composite layer, and continues the second Technology for Heating Processing, form metal silicide layer to prepare in district in this metal silicide on the substrate surface that the described metal silicide exposed prepares district.
2. method according to claim 1, is characterized in that, described substrate is silicon substrate.
3. method according to claim 1, is characterized in that, described metal composite layer comprises a metal level and is positioned at the nitrided metal layer on described metal level.
4. method according to claim 3, is characterized in that, described metal level is the wherein at least one being selected from titanium, cobalt, nickel or platinum.
5. method according to claim 1, is characterized in that, described first heat treatment and described second heat treatment are annealing process.
6. method according to claim 1, is characterized in that, the method for employing dry etching removes described fluorine-doped silica layer and described silicon nitride layer forms described side wall.
7. method according to claim 1, is characterized in that, the thickness of described fluorine-doped silica layer is 20-100 dust.
8. method according to claim 1, is characterized in that, the Oil repellent in described fluorine-doped silica layer is less than 5%.
9. method according to claim 1, is characterized in that, described method also comprises, and first deposits one deck silicon oxide layer, then deposits fluorine-doped silica layer and silicon nitride layer successively.
10. method according to claim 9, is characterized in that, the Oil repellent in described fluorine-doped silica layer is less than 10%.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410710161.XA CN104465351B (en) | 2014-11-28 | 2014-11-28 | A kind of method for improving metal silicide |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410710161.XA CN104465351B (en) | 2014-11-28 | 2014-11-28 | A kind of method for improving metal silicide |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104465351A true CN104465351A (en) | 2015-03-25 |
| CN104465351B CN104465351B (en) | 2017-12-05 |
Family
ID=52911222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410710161.XA Active CN104465351B (en) | 2014-11-28 | 2014-11-28 | A kind of method for improving metal silicide |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104465351B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111681961A (en) * | 2020-07-24 | 2020-09-18 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
| CN116344364A (en) * | 2023-05-31 | 2023-06-27 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device and semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6153485A (en) * | 1998-11-09 | 2000-11-28 | Chartered Semiconductor Manufacturing Ltd. | Salicide formation on narrow poly lines by pulling back of spacer |
| CN1979786A (en) * | 2005-11-29 | 2007-06-13 | 联华电子股份有限公司 | Method for making strain silicon transistor |
| CN102832112A (en) * | 2011-06-17 | 2012-12-19 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal silicide |
| CN102856179A (en) * | 2011-06-29 | 2013-01-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
-
2014
- 2014-11-28 CN CN201410710161.XA patent/CN104465351B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6153485A (en) * | 1998-11-09 | 2000-11-28 | Chartered Semiconductor Manufacturing Ltd. | Salicide formation on narrow poly lines by pulling back of spacer |
| CN1979786A (en) * | 2005-11-29 | 2007-06-13 | 联华电子股份有限公司 | Method for making strain silicon transistor |
| CN102832112A (en) * | 2011-06-17 | 2012-12-19 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal silicide |
| CN102856179A (en) * | 2011-06-29 | 2013-01-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111681961A (en) * | 2020-07-24 | 2020-09-18 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
| CN111681961B (en) * | 2020-07-24 | 2024-02-02 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
| CN116344364A (en) * | 2023-05-31 | 2023-06-27 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device and semiconductor device |
| CN116344364B (en) * | 2023-05-31 | 2023-08-22 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104465351B (en) | 2017-12-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104347418B (en) | The forming method of MOS transistor | |
| TWI642108B (en) | Method for manufacturing semiconductor device | |
| WO2003047000A1 (en) | Semiconductor device and production method therefor | |
| CN101626031A (en) | Gate electrodes of hvmos devices having non-uniform doping concentrations | |
| US7449403B2 (en) | Method for manufacturing semiconductor device | |
| JP2007317760A (en) | Semiconductor device, and its manufacturing method | |
| TWI434397B (en) | Multilayer gettering structure for semiconductor devices and method | |
| CN104465351A (en) | Method for improving metal silicide | |
| TW548729B (en) | Selective metal oxide removal | |
| CN102832112A (en) | Method for forming metal silicide | |
| CN104505342A (en) | Method for improving metal silicides | |
| CN103839791A (en) | Preparation method for trench gate of trench type MOS device | |
| Jiang et al. | Field isolation for GaN MOSFETs on AlGaN/GaN heterostructure with boron ion implantation | |
| CN102479713B (en) | MOSFET manufacture method and MOSFET | |
| CN103311110B (en) | The forming method of semiconductor structure, the forming method of transistor | |
| JP2005142549A (en) | Manufacturing method for semiconductor device | |
| JP2016201405A (en) | Silicon carbide semiconductor device manufacturing method | |
| CN102881590B (en) | Forming method for repair layer and metal oxide semiconductor transistor structure | |
| US8796123B2 (en) | Method of manufacturing silicon carbide semiconductor device | |
| CN102194684B (en) | Grid dielectric layer manufacturing method | |
| CN106158644B (en) | The gate structure of semiconductor devices and the method for preventing it from generating cavity | |
| CN116666236B (en) | Surface passivation method of semiconductor material | |
| KR101035661B1 (en) | Method for fabricating thin film transistor and thin film transistor by thereof | |
| JPS63150963A (en) | Semiconductor device | |
| TW498457B (en) | Method to prevent undercut phenomenon of spacer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |