CN104347408A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- CN104347408A CN104347408A CN201310327038.5A CN201310327038A CN104347408A CN 104347408 A CN104347408 A CN 104347408A CN 201310327038 A CN201310327038 A CN 201310327038A CN 104347408 A CN104347408 A CN 104347408A
- Authority
- CN
- China
- Prior art keywords
- resilient coating
- quantum
- fin type
- grid
- well materials
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000000463 material Substances 0.000 claims abstract description 113
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 230000004888 barrier function Effects 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000011248 coating agent Substances 0.000 claims description 63
- 238000000576 coating method Methods 0.000 claims description 63
- 239000011435 rock Substances 0.000 claims description 30
- 239000012212 insulator Substances 0.000 claims description 25
- 238000009413 insulation Methods 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 229910002704 AlGaN Inorganic materials 0.000 claims 2
- 230000000694 effects Effects 0.000 abstract description 3
- 230000017525 heat dissipation Effects 0.000 abstract description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 11
- 229910017083 AlN Inorganic materials 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 229910002601 GaN Inorganic materials 0.000 description 6
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004969 ion scattering spectroscopy Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/122—Single quantum well structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
- H01L29/151—Compositional structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7789—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
Abstract
The invention discloses a method for manufacturing a semiconductor device and a semiconductor device. The method for manufacturing the semiconductor device comprises the following steps: providing a substrate structure, wherein the substrate structure comprises a substrate and a fin-type buffer layer formed on the surface of the substrate; forming a quantum well material layer on the surface of the fin-type buffer layer, and forming a barrier material layer on the quantum well material layer, wherein electron gas can be well generated in the quantum well material layer, thereby ensuring the high mobility of the semiconductor device while improving the short-channel effect. In addition, according to the manufacturing method of the semiconductor device, heat dissipation of the semiconductor device can be improved, so that the performance and stability of the device can be improved.
Description
Technical field
The present invention relates to semiconductor device and manufacture method thereof.
Background technology
(High Electron Mobility Transistor is called for short: HEMT) typically can comprise modulation doping heterojunction and corresponding source-drain structure High Electron Mobility Transistor.Owing to being present in two-dimensional electron gas (Two Dimensional Electron Gas, the abbreviation: 2-DEG) substantially by the impact of ionization foreign ion scattering, its mobility is very high, and therefore HEMT device receives many concerns recently in heterojunction.
Along with the reduction of device size, (Quantum Well is called for short: (Ultra Thin Body is called for short: UTB) to alleviate or to avoid the short-channel effect of transistor ultra-thin body QW) to propose to use such as quantum well in HEMT device.Usually, silicon device uses the amorphous state dielectric of such as silicon dioxide to generate the UTB layer of silicon on insulant.But these materials are heat-insulating, cause the heat dissipation poor performance of device.In addition, existing on-plane surface quantum well transistor is easy to occur that electric charge overflows, thus have impact on device performance.
Summary of the invention
The present inventor finds to have problems in above-mentioned prior art, and therefore proposes new technical scheme to alleviate at least partly or to solve at least part of the problems referred to above for the problems referred to above.
According to an aspect of the present invention, a kind of method manufacturing semiconductor device is provided, comprises: substrat structure is provided, the fin type resilient coating that described substrat structure comprises substrate and formed on the surface of a substrate; The surface of described fin type resilient coating forms quantum-well materials layer; And, quantum-well materials layer is formed barrier material layer; Wherein said quantum-well materials layer is suitable for forming electron gas wherein.
In one embodiment, described substrate surface is also formed with the insulation division laterally adjacent with described fin type resilient coating; Further, the described step forming quantum-well materials layer on the surface of described fin type resilient coating comprises: on the surface do not covered by described insulation division of described fin type resilient coating, form quantum-well materials layer.
In one embodiment, barrier material layer forms cap rock, forms grid structure afterwards, described grid structure comprises at least gate insulator in a part for described cap rock, the grid on gate insulator and the sept for described grid.
In one embodiment, barrier material layer forms cap rock, form grid structure afterwards, described grid structure is included in gate insulator, the grid on gate insulator and the sept for described grid in a part for described cap rock and a part for insulation division.
In one embodiment, said method also comprises: be that mask etches with grid structure, until a part for fin type resilient coating is etched removal; Fin type resilient coating by etching grown over portions semi-conducting material to form source region and drain region.
In one embodiment, the step of substrat structure is provided to comprise: to form resilient coating over the substrate; Patterning is carried out to resilient coating, to form described fin type resilient coating.
In one embodiment, the thickness range of fin type resilient coating can be about 1-2 μm; The thickness range of quantum-well materials layer can be about 10-50nm; And/or the thickness range of barrier material layer can be about 1-5nm.The thickness range of cap rock can be about 1-3nm.
In one embodiment, the formation of described quantum-well materials layer, the formation of described barrier material layer and/or the formation of described cap rock comprise selective epitaxial growth.
In one embodiment, the material of fin type resilient coating is AlN; Quantum-well materials is GaN; And the material of barrier material layer is AlN.In one embodiment, quantum-well materials can be one of following: InGaN, AlGaN, Ge, III-IV or II-VI group semi-conducting material.In one embodiment, described substrate is silicon substrate.
According to a further aspect in the invention, a kind of semiconductor device is provided, comprises: substrate; Fin type resilient coating on described substrate surface; Quantum-well materials layer on described fin type buffer-layer surface; Barrier material layer on quantum-well materials layer; Wherein said quantum-well materials layer is suitable for forming electron gas wherein.
In one embodiment, said apparatus also comprises: the insulation division laterally adjacent with described fin type resilient coating on described substrate surface; And described quantum-well materials layer is formed on the surface do not covered by described insulation division of described fin type resilient coating.
In one embodiment, said apparatus also comprises: the cap rock on barrier material layer; And grid structure, wherein said grid structure comprises at least gate insulator in a part for described cap rock, the grid on gate insulator and the sept for described grid.
In one embodiment, said apparatus also comprises: the cap rock on barrier material layer; And grid structure, wherein said grid structure is included in gate insulator, the grid on gate insulator and the sept for described grid in a part for described cap rock and a part for insulation division.
In one embodiment, said apparatus be also included in fin type resilient coating by source region that etching part is formed and drain region.
By referring to the detailed description of accompanying drawing to exemplary embodiment of the present invention, further feature of the present invention and advantage thereof will become clear.
Accompanying drawing explanation
What form a part for specification drawings describes embodiments of the invention, and together with the description for explaining principle of the present invention.
According to detailed description with reference to the accompanying drawings, clearly the present invention can be understood, in the accompanying drawings:
Fig. 1 is the schematic flow diagram of the method manufacturing semiconductor device according to an embodiment of the invention; And
Fig. 2-Figure 11 schematically shows some stages of the manufacture process of semiconductor device according to an embodiment of the invention.
Embodiment
Various exemplary embodiment of the present invention is described in detail now with reference to accompanying drawing.Should be understood that unless specifically stated otherwise, otherwise positioned opposite, the numerical expression of the parts of setting forth in these embodiments and step and numerical value should not be understood to limitation of the scope of the invention.
In addition, should be appreciated that for convenience of description, the size of all parts shown in accompanying drawing is uninevitable draws according to the proportionate relationship of reality.
Only illustrative to the description of exemplary embodiment below, never as any restriction to the present invention and application or use.
May not discuss in detail for the known technology of person of ordinary skill in the relevant, method and apparatus, but in these technology applicable, method and apparatus situation, these technology, method and apparatus should be regarded as the part of this specification.
In all examples with discussing shown here, any occurrence all should be construed as merely exemplary, instead of as restriction.Therefore, other example of exemplary embodiment can have different values.
It should be noted that in similar label and letter accompanying drawing below and represent similar terms, therefore, once be defined in an a certain Xiang Yi accompanying drawing, then will not need to be further discussed it in the description of the drawings subsequently.
Fig. 1 is the schematic flow diagram of the method manufacturing semiconductor device according to an embodiment of the invention.As shown in Figure 1, in step 101, provide substrat structure, the fin type resilient coating that described substrat structure comprises substrate and formed on the surface of a substrate.In one embodiment, the above-mentioned step of substrat structure that provides can comprise: form resilient coating over the substrate; And, patterning is carried out to resilient coating, to form described fin type resilient coating.In certain embodiments, above-mentioned substrate can be such as silicon substrate, but should be understood that the present invention is not limited to this.
In certain embodiments, the material of fin type resilient coating can be preferably aluminium nitride (AlN).The thermal conductivity of aluminium nitride is about 3.4W/cm-K, and two orders of magnitude and the thermal conductivity of silicon dioxide declines by comparison, are approximately 0.014W/cm-K.Therefore by the material using aluminium nitride as fin type resilient coating, the heat that the semiconductor device that can be conducive to dissipating such as HEMT produces, thus improve performance and the stability of semiconductor device.When the material adopting aluminium nitride as fin type resilient coating, described substrate is preferably (111) silicon substrate, and also, first type surface is the silicon substrate of (111) crystal face.In some other embodiment, described substrate can be such as Sapphire Substrate, or other suitable substrate.
Then, in step 102, the surface of described fin type resilient coating forms quantum-well materials layer.Here, quantum-well materials can be gallium nitride (GaN), (GaN) that such as N-shaped mixes.This quantum-well materials layer can be formed by such as selective epitaxial growth.Wherein said quantum-well materials layer is suitable for forming electron gas wherein.
Then, in step 103, quantum-well materials layer forms barrier material layer.The material of barrier material layer can be aluminium nitride (AlN).This barrier material layer also can be formed by such as selective epitaxial growth.This barrier material layer, quantum-well materials layer and resilient coating can form quantum well structure, and wherein barrier material layer and resilient coating form potential barrier, and quantum-well materials layer forms potential well.
By the method for the manufacture semiconductor device shown in Fig. 1, define the semiconductor device with nonplanar (such as, fin type) quantum well structure.Utilize according to quantum well structure of the present invention, can realize, while the short-channel effect alleviating semiconductor device (such as, HEMT device), ensure that high carrier mobility.In addition, according to semiconductor device of the present invention, significantly improve the heat dissipation of device, thus improve performance and the thermal stability of device.
Afterwards, grid structure can be formed further.In some preferred embodiments, optional cap rock can be formed on barrier material layer, as shown in the step 104 in Fig. 1, be beneficial to subsequent step (such as, the formation of high-k dielectrics) and provide the protection of quantum well structure in order to avoid by the impact of subsequent step.Described cap rock can be formed by such as selective epitaxial growth.Afterwards, form grid structure (, being referred to as first grid structure here) further, wherein first grid structure comprises at least gate insulator in a part for described cap rock, the grid on gate insulator and the sept for described grid.Method as known in the art, processing step, material etc. can be utilized to form grid structure, no longer describe in detail at this.
In addition, in other embodiments, the described surface of described substrate can also be formed with the insulation division laterally adjacent with described fin type resilient coating.In this embodiment, the above-mentioned step forming quantum-well materials layer on the surface of described fin type resilient coating comprises: on the surface do not covered by described insulation division of described fin type resilient coating, form quantum-well materials layer.That is, in this embodiment, quantum-well materials layer is formed in and states on the surface do not covered by described insulation division of fin type resilient coating.Therefore, with the embodiment of above-mentioned formation first grid structure unlike, in the present embodiment, the grid structure (, being referred to as second grid structure here) formed further after barrier material layer forms cap rock can be included in gate insulator, the grid on gate insulator and the sept for described grid in a part for described cap rock and a part for insulation division.
However, it should be understood that the present invention is not limited to shown embodiment here.Exemplarily, quantum-well materials also can be one of following: InGaN (InGaN), aluminum gallium nitride (AlGaN), germanium Ge and III-IV or II-VI group semi-conducting material.Further, those of ordinary skill in the art easily can select the suitable cushioning layer material that coordinates with above-mentioned quantum-well materials and barrier material, form the semiconductor structure of the present invention's instruction.
In certain embodiments, the thickness range of fin type resilient coating can be about 1-20 μm, is preferably 1-2 μm, such as, is about 1.5 μm.The thickness range of quantum-well materials layer can be about 10-50nm, such as, be 20nm, 30nm, 40nm etc.The thickness range of barrier material layer can be about 1-5nm, such as, be about 4nm.The thickness range of cap rock can be about 1-3nm, such as, be 2nm.Here should be understood that these numerical value or number range are only exemplary, but not limitation of the present invention.
In certain embodiments, can, after forming above-mentioned grid structure, be that mask etches, until a part for fin type resilient coating is etched removal with grid structure.Then, fin type resilient coating by etching grown over portions semi-conducting material (such as, the GaN of N+ doping) to form source region and drain region.
Fig. 2-Figure 11 schematically shows some stages of the manufacture process of semiconductor device according to an embodiment of the invention.
First, as shown in Figure 2, by such as MOCVD(Metal-organic Chemical Vapor Deposition, metallo-organic compound chemical gaseous phase deposition), ALD(Atomic layer deposition, ald), MBE(Molecular Beam Epitaxy, molecular beam epitaxy) etc. technique, on substrate 1 formed resilient coating 2.In this embodiment, the material of resilient coating 2 is aluminium nitride AlN, and the material of substrate 1 is silicon.The first type surface crystal orientation of silicon substrate 1 is <111> crystal orientation.
Then, as shown in Figure 3 a and Figure 3 b shows, patterning is carried out to resilient coating 2, such as, by photoetching and dry ecthing, form fin type resilient coating 3 on substrate 1.Wherein, Fig. 3 a shows the profile of the longitudinal direction (also namely, the direction of the raceway groove formed afterwards) perpendicular to fin, and Fig. 3 b shows the profile of the longitudinal direction (channel direction) along fin.
Next, as shown in figures 4 a and 4b, the surface of substrate 1 forms the insulation division 4 laterally adjacent with fin type resilient coating 3.In a concrete example, insulation division 4 is silicon dioxide layer, and its thickness can be about 50-500nm.Similarly, Fig. 4 a is the profile perpendicular to channel direction, and Fig. 4 b is the profile along channel direction.As has been explained, in certain embodiments, this insulating barrier may be not necessarily.
Afterwards, as shown in figure 5 a and 5b, the surface of fin type resilient coating 3 is formed quantum-well materials layer 5, quantum-well materials layer 5 is formed barrier material layer 6, barrier material layer 6 is formed cap rock 7.Similarly, Fig. 5 a is the profile perpendicular to channel direction, and Fig. 5 b is the profile along channel direction.In this embodiment, quantum-well materials is gallium nitride GaN; Barrier material is aluminium nitride AlN.Foregoing, quantum-well materials layer 5, barrier material layer 6 and/or cap rock 7 can be formed by selective epitaxial growth.
In addition, in this embodiment, the thickness range of fin type resilient coating 3 is about 1-2 μm, and the thickness range of quantum-well materials layer 5 is about 10-50nm, and the thickness range of barrier material layer 6 is about 1-5nm, and the thickness range of cap rock 7 is about 1-3nm.
Next, as shown in figures 6 a and 6b, gate insulator 8 is formed.Wherein gate insulator 8 cover insulation division 4 at least partially with cap rock 7 at least partially.Similarly, Fig. 6 a is the profile perpendicular to channel direction, and Fig. 6 b is the profile along channel direction.In a concrete example, the material of gate insulator 8 can be high-k dielectric, and the thickness of gate insulator 8 can be about 1-5nm.
Subsequently, as shown in figs. 7 a and 7b, by techniques such as such as PVD, MOCVD, ALD, MBE, deposition of gate material 9 on gate insulator 8.Fig. 7 a is the profile perpendicular to channel direction, and Fig. 7 b is the profile along channel direction.Here grid material can be metal material, such as Ni-Au or Cr-Au.
Next, as shown in Figure 8, by carrying out patterning to grid material 9, to form grid 10.Fig. 8 is the profile along channel direction.But should be understood that the present invention is not limited to this.Such as, in an other concrete example, grid material can be polysilicon, and grid 10 can be polysilicon gate or pseudo-grid.The pseudo-grid of this polysilicon can be substituted with metal gates in a further step.
After formation of the gate, formed and be used for grid both sides formation sept 11, then with grid and sept for mask (here alternatively with whole grid structure for mask) etches, until a part for fin type resilient coating is etched removal, as shown in Figure 9, wherein Fig. 9 is the profile along channel direction.Should be understood that in accompanying drawing, illustrated each parts are only schematic, do not represent the accurate shape of actual device.
Afterwards, as shown in Figure 10, at fin type resilient coating by etching some growth semi-conducting material, thus form source region and drain region.Figure 10 is the profile along channel direction.
Finally, as shown in figure 11, corresponding source/drain 13 can be formed on source/drain regions.Figure 11 is the profile along channel direction.
It should be noted that, Fig. 8-Figure 11 is the profile along channel direction.
Should be understood that the present invention is not limited to execution mode described above.Such as, in an other concrete example, grid material can be polysilicon, and grid 10 can be the pseudo-grid of polysilicon gate or polysilicon.The person skilled in the art will easily understand, the pseudo-grid of this polysilicon can be replaced by with metal gates in a further step, such as, can remove the pseudo-grid of polysilicon after grown source region and drain region, then form metal gates.
Therefore, present invention also offers a kind of semiconductor device, comprising: substrate; Fin type resilient coating on described substrate surface; Quantum-well materials layer on described fin type buffer-layer surface; And, the barrier material layer on quantum-well materials layer; Wherein said quantum-well materials layer is suitable for forming electron gas wherein.
Said apparatus can also comprise: the insulation division laterally adjacent with described fin type resilient coating on described substrate surface; And described quantum-well materials layer is formed on the surface do not covered by described insulation division of described fin type resilient coating.
Said apparatus can also comprise: the cap rock on barrier material layer; And at the grid structure gone up at least partially of cap rock.
So far, described in detail according to semiconductor device of the present invention and manufacture method thereof.In order to avoid covering design of the present invention, do not describe details more known in the field, those skilled in the art, according to description above, can understand how to implement technical scheme disclosed herein completely.In addition, each embodiment that the disclosure is instructed can independent assortment.
It should be appreciated by those skilled in the art, multiple amendment can be carried out to embodiment described above and not depart from the spirit and scope of the present invention as claims limit.
Claims (20)
1. manufacture a method for semiconductor device, it is characterized in that, comprising:
There is provided substrat structure, the fin type resilient coating that described substrat structure comprises substrate and formed on the surface of a substrate;
The surface of described fin type resilient coating forms quantum-well materials layer; And
Quantum-well materials layer is formed barrier material layer;
Wherein said quantum-well materials layer is suitable for forming electron gas wherein.
2. the method for claim 1, is characterized in that,
Described substrate surface is also formed with the insulation division laterally adjacent with described fin type resilient coating; Further,
The described step forming quantum-well materials layer on the surface of described fin type resilient coating comprises:
The surface do not covered by described insulation division of described fin type resilient coating forms quantum-well materials layer.
3. method according to claim 1, is characterized in that, also comprises:
Barrier material layer forms cap rock; And
Form grid structure, described grid structure comprises at least gate insulator in a part for described cap rock, the grid on gate insulator and the sept for described grid.
4. method according to claim 2, is characterized in that, also comprises:
Barrier material layer forms cap rock; And
Form grid structure, described grid structure is included in gate insulator, the grid on gate insulator and the sept for described grid in a part for described cap rock and a part for insulation division.
5. the method according to claim 3 or 4, is characterized in that, also comprises:
Be that mask etches, until a part for fin type resilient coating is etched removal with grid structure;
Fin type resilient coating by etching grown over portions semi-conducting material to form source region and drain region.
6. method according to claim 1, is characterized in that,
The step of substrat structure is provided to comprise:
Form resilient coating over the substrate;
Patterning is carried out to resilient coating, to form described fin type resilient coating.
7. method according to claim 1, is characterized in that,
The thickness range of fin type resilient coating is 1-2 μm;
The thickness range of quantum-well materials layer is 10-50nm; And/or
The thickness range of barrier material layer is 1-5nm.
8. method according to claim 1, is characterized in that,
The formation of described quantum-well materials layer and/or the formation of described barrier material layer comprise selective epitaxial growth.
9. method according to claim 1, is characterized in that,
The material of fin type resilient coating is AlN;
Quantum-well materials is GaN; And
The material of barrier material layer is AlN.
10. method according to claim 1, is characterized in that,
Quantum-well materials is one of following: InGaN, AlGaN, Ge, III-IV or II-VI group semi-conducting material.
11. methods according to claim 9, is characterized in that,
Described substrate is silicon substrate.
12. 1 kinds of semiconductor devices, is characterized in that, comprising:
Substrate;
Fin type resilient coating on described substrate surface;
Quantum-well materials layer on described fin type buffer-layer surface; And
Barrier material layer on quantum-well materials layer;
Wherein said quantum-well materials layer is suitable for forming electron gas wherein.
13. semiconductor devices as claimed in claim 12, is characterized in that, also comprise:
The insulation division laterally adjacent with described fin type resilient coating on described substrate surface; And
Described quantum-well materials layer is formed on the surface do not covered by described insulation division of described fin type resilient coating.
14. semiconductor devices according to claim 12, is characterized in that, also comprise:
Cap rock on barrier material layer; And
Grid structure, wherein said grid structure comprises at least gate insulator in a part for described cap rock, the grid on gate insulator and the sept for described grid.
15. semiconductor devices according to claim 12, is characterized in that, also comprise:
Cap rock on barrier material layer; And
Grid structure, wherein said grid structure is included in gate insulator, the grid on gate insulator and the sept for described grid in a part for described cap rock and a part for insulation division.
16. semiconductor devices according to claims 14 or 15, is characterized in that, also comprise:
At fin type resilient coating by source region that etching part is formed and drain region.
17. semiconductor devices according to claim 12, is characterized in that,
The thickness range of fin type resilient coating is 1-2 μm;
The thickness range of quantum-well materials layer is 10-50nm; And/or
The thickness range of barrier material layer is 1-5nm.
18. semiconductor devices according to claim 12, is characterized in that,
The material of fin type resilient coating is AlN;
The material of quantum-well materials layer is GaN; And
The material of barrier material layer is AlN.
19. semiconductor devices according to claim 12, is characterized in that,
Quantum-well materials is one of following: InGaN, AlGaN, Ge, III-IV or II-VI group semi-conducting material.
20. semiconductor devices according to claim 18, is characterized in that,
Described substrate is silicon substrate.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310327038.5A CN104347408B (en) | 2013-07-31 | 2013-07-31 | Semiconductor device and its manufacture method |
| US14/281,007 US9269772B2 (en) | 2013-07-31 | 2014-05-19 | Semiconductor device and fabrication method thereof |
| US15/012,297 US9437709B2 (en) | 2013-07-13 | 2016-02-01 | Semiconductor device and fabrication method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310327038.5A CN104347408B (en) | 2013-07-31 | 2013-07-31 | Semiconductor device and its manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104347408A true CN104347408A (en) | 2015-02-11 |
| CN104347408B CN104347408B (en) | 2017-12-26 |
Family
ID=52426809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310327038.5A Active CN104347408B (en) | 2013-07-13 | 2013-07-31 | Semiconductor device and its manufacture method |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US9269772B2 (en) |
| CN (1) | CN104347408B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448977A (en) * | 2015-12-31 | 2016-03-30 | 深圳市华讯方舟微电子科技有限公司 | High electron mobility transistor and fabrication method thereof |
| CN109411574A (en) * | 2017-08-16 | 2019-03-01 | 格芯公司 | Uniform semiconductor nanowires and nanometer sheet light emitting diode |
| CN110021662A (en) * | 2018-01-08 | 2019-07-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9048303B1 (en) * | 2014-01-30 | 2015-06-02 | Infineon Technologies Austria Ag | Group III-nitride-based enhancement mode transistor |
| US9337279B2 (en) | 2014-03-03 | 2016-05-10 | Infineon Technologies Austria Ag | Group III-nitride-based enhancement mode transistor |
| DE102015114177A1 (en) * | 2015-08-26 | 2017-03-02 | Infineon Technologies Ag | Semiconductor device, silicon wafer and method for producing a silicon wafer |
| JP6891448B2 (en) * | 2016-10-21 | 2021-06-18 | 富士電機株式会社 | Semiconductor devices and methods for manufacturing semiconductor devices |
| EP3732728A4 (en) * | 2017-12-29 | 2021-08-11 | INTEL Corporation | Iii-v transistors with resistive gate contacts |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050017377A1 (en) * | 2003-07-21 | 2005-01-27 | International Business Machines Corporation | FET channel having a strained lattice structure along multiple surfaces |
| US20090085027A1 (en) * | 2007-09-29 | 2009-04-02 | Intel Corporation | Three dimensional strained quantum wells and three dimensional strained surface channels by ge confinement method |
| CN101853882A (en) * | 2009-04-01 | 2010-10-06 | 台湾积体电路制造股份有限公司 | High-mobility multiple-gate transistor with improved on-to-off current ratio |
| CN102656699A (en) * | 2009-12-23 | 2012-09-05 | 英特尔公司 | Non-planar germanium quantum well devices |
| CN103915336A (en) * | 2013-01-08 | 2014-07-09 | 中芯国际集成电路制造(上海)有限公司 | Three-dimensional quantum well transistor and forming method thereof |
| CN103943498A (en) * | 2013-01-22 | 2014-07-23 | 中芯国际集成电路制造(上海)有限公司 | Three-dimensional quantum well transistor and formation method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7928426B2 (en) * | 2007-03-27 | 2011-04-19 | Intel Corporation | Forming a non-planar transistor having a quantum well channel |
| US8575653B2 (en) | 2010-09-24 | 2013-11-05 | Intel Corporation | Non-planar quantum well device having interfacial layer and method of forming same |
-
2013
- 2013-07-31 CN CN201310327038.5A patent/CN104347408B/en active Active
-
2014
- 2014-05-19 US US14/281,007 patent/US9269772B2/en active Active
-
2016
- 2016-02-01 US US15/012,297 patent/US9437709B2/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050017377A1 (en) * | 2003-07-21 | 2005-01-27 | International Business Machines Corporation | FET channel having a strained lattice structure along multiple surfaces |
| US20090085027A1 (en) * | 2007-09-29 | 2009-04-02 | Intel Corporation | Three dimensional strained quantum wells and three dimensional strained surface channels by ge confinement method |
| CN101853882A (en) * | 2009-04-01 | 2010-10-06 | 台湾积体电路制造股份有限公司 | High-mobility multiple-gate transistor with improved on-to-off current ratio |
| CN102656699A (en) * | 2009-12-23 | 2012-09-05 | 英特尔公司 | Non-planar germanium quantum well devices |
| CN103915336A (en) * | 2013-01-08 | 2014-07-09 | 中芯国际集成电路制造(上海)有限公司 | Three-dimensional quantum well transistor and forming method thereof |
| CN103943498A (en) * | 2013-01-22 | 2014-07-23 | 中芯国际集成电路制造(上海)有限公司 | Three-dimensional quantum well transistor and formation method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448977A (en) * | 2015-12-31 | 2016-03-30 | 深圳市华讯方舟微电子科技有限公司 | High electron mobility transistor and fabrication method thereof |
| CN109411574A (en) * | 2017-08-16 | 2019-03-01 | 格芯公司 | Uniform semiconductor nanowires and nanometer sheet light emitting diode |
| CN109411574B (en) * | 2017-08-16 | 2023-03-10 | 格芯美国公司 | Uniform semiconductor nanowire and nanosheet light emitting diodes |
| CN110021662A (en) * | 2018-01-08 | 2019-07-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN110021662B (en) * | 2018-01-08 | 2021-02-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| US20150034906A1 (en) | 2015-02-05 |
| US9437709B2 (en) | 2016-09-06 |
| CN104347408B (en) | 2017-12-26 |
| US20160149014A1 (en) | 2016-05-26 |
| US9269772B2 (en) | 2016-02-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10991819B2 (en) | High electron mobility transistors | |
| CN104347408B (en) | Semiconductor device and its manufacture method | |
| CN103943498B (en) | Three-dimensional quantum well transistor and forming method thereof | |
| CN103367440B (en) | For the fin structure of FinFET | |
| US20150053928A1 (en) | Silicon and silicon germanium nanowire formation | |
| CN104835843B (en) | Field effect transistor with heterostructure-channel | |
| JP2010278435A (en) | Gradient ternary or quaternary multiple-gate transistor | |
| US9679975B2 (en) | Semiconductor devices including field effect transistors and methods of forming the same | |
| WO2018004660A1 (en) | Gate stack design for gan e-mode transistor performance | |
| KR102132147B1 (en) | Semiconductor device and method of fabrucating the same | |
| TWI605552B (en) | Semiconductor device, semiconductor substrate and method of forming the same | |
| US20170222034A1 (en) | METHOD FOR FORMATION OF VERTICAL CYLINDRICAL GaN QUANTUM WELL TRANSISTOR | |
| CN105932041A (en) | N-face GaN-based fin high electron mobility transistor and manufacturing method | |
| KR20140037992A (en) | High electron mobility transistor and manufacturing method of the same | |
| CN104347407B (en) | Semiconductor device and its manufacture method | |
| CN105006485A (en) | FET based on topology semimetal, and HEMT based on topology semimetal and preparation method thereof | |
| CN105552125A (en) | Semiconductor structure and manufacturing method thereof | |
| TWI713642B (en) | Fin-type field effect transistor and manufacturing method thereof | |
| US10629475B2 (en) | Semiconductor device with two-part insulation structure within non-active region | |
| CN103915336B (en) | Three-dimensional quantum well transistor and forming method thereof | |
| TWI647823B (en) | Complementary transistor element structure and manufacturing method thereof | |
| US10559683B2 (en) | Apparatus and methods to create a buffer to reduce leakage in microelectronic transistors | |
| TW201816944A (en) | Method for manufacturing complementary metal-oxide-semiconductor device | |
| TW201926710A (en) | Tunneling field-effect transistor | |
| CN112786699B (en) | High electron mobility transistor and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |