CN103928348A - Separation method for double grids - Google Patents
Separation method for double grids Download PDFInfo
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- CN103928348A CN103928348A CN201410174398.0A CN201410174398A CN103928348A CN 103928348 A CN103928348 A CN 103928348A CN 201410174398 A CN201410174398 A CN 201410174398A CN 103928348 A CN103928348 A CN 103928348A
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- hard mask
- layer
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- fin
- mask layer
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- 238000000926 separation method Methods 0.000 title claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 19
- 230000005669 field effect Effects 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 73
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 239000011265 semifinished product Substances 0.000 claims description 19
- 230000008021 deposition Effects 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 230000036961 partial effect Effects 0.000 claims description 3
- 239000011241 protective layer Substances 0.000 claims description 2
- 230000009467 reduction Effects 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 15
- 230000002829 reductive effect Effects 0.000 abstract description 2
- 238000004062 sedimentation Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 16
- 238000005516 engineering process Methods 0.000 description 9
- 230000008859 change Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
Abstract
The invention discloses a separation method for double grids. The separation method comprises the steps that a hard mask layer is arranged at the top end of each fin of a fin field-effect transistor; the hard mask layers arranged at the top ends of the fins are removed partly or completely in a selective mode, and a grid layer is formed through sedimentation of grid materials; a photoresistance layer is formed on the upper surface of the grid layer, and grids corresponding to the fins with the hard mask layers reserved are exposed; the grids corresponding to the fins with the hard mask layers are partly etched away through the etching process, the etching process is stopped at the hard mask layers arranged on the top ends of the fins with the hard mask layers reserved, and therefore the heights of the corresponding grids are reduced and the corresponding grids are exposed; remaining portions of the photoresistance layer on the grid layer are removed. According to the separation method for the double grids, the hard mask layers and the photoresistance layer are additionally arranged in an early structure, as a result, etching accuracy can be controlled accurately, the structure is protected against damage, and difficulty of self alignment can be lowered.
Description
Technical field
The invention belongs to technical field of semiconductors, specifically, relate to a kind of two grid separation method.
Background technology
Fin formula field-effect transistor (FinField-effecttransistor is called for short FinFET) is a kind of new CMOS (Complementary Metal Oxide Semiconductor) (CMOS) transistor.It is the improvement of the Fet (transistor-field-effect transistor, Field-effecttransistor, FET) to traditional standard.Fin formula field-effect transistor FinFET can regulate the threshold voltage of device as required, further reduces static energy consumption (static powerconsumption).
At present, fin formula field-effect transistor FinFET comprises three end FinFET (3terminal FinFet is called for short 3T-FinFet), four end FinFET (4terminal FinFet is called for short 4T-FinFet).Fig. 1 is the brief configuration schematic diagram of 3T-FinFet in prior art; As shown in Figure 1, it comprises a source S 101, a drain D 102, and a grid G 103, amounts to three terminations.In prior art, the schematic equivalent circuit of 3T-FinFet as shown in Figure 2.Fig. 3 is the brief configuration schematic diagram of 4T-FinFet in prior art; As shown in Figure 3, it comprises a source S 201, a drain D 202, and grid G 1203, another one grid G 2204, amounts to 4 terminations.In prior art, the schematic equivalent circuit of 4T-FinFet as shown in Figure 4.
Wherein, for 4T-FinFet, in order to obtain two grids, prior art provides two kinds of technical solution schemes: first kind of way is to utilize cmp (chemical mechanical polishing, be called for short CMP) grid on fin Fin300 top is ground away, it grinds the structural representation of front and back, as shown in Figure 5 and Figure 6; The second way is to increase by one light shield 400, and the grid etch on fin Fin300 top is fallen, and the structural representation before and after etching as shown in Figure 7 and Figure 8.
But while utilizing above-mentioned technique to form two grids, if there are gapped words between grid and source/drain region, when device is worked, raceway groove just can not conducting, therefore, needs to be provided with certain overlapping cover part between grid and source/drain region.But, if this lap is excessive, the parasitic capacitance between grid-source and between grid-leakage is increased, cause the high frequency characteristics of device to degenerate.So, in order to make the device can conducting, and don't cause the high frequency characteristics of device deteriorated, little with regard to what require lap between grid-source or between grid-leakage to try one's best, reach high-precision aligning, i.e. autoregistration.
But inventor finds in realizing process of the present invention, due to etching or grinding, easily causes the damage of structure, be further difficult to accurately guarantee overlapping cover part between grid and source/drain region, therefore, cause autoregistration degree to be difficult to control.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of two grid separation method and formula field-effect transistor semi-finished product structure, in order to solve in prior art due to etching or to grind the damage that easily causes structure, causes autoregistration degree to be difficult to control.
In order to solve the problems of the technologies described above, the invention provides a kind of two grid separation method, it comprises:
Each fin top at fin formula field-effect transistor arranges a hard mask layer;
Partly or entirely get rid of selectively the hard mask layer that fin top arranges, and deposition of gate material forms grid layer;
At described grid layer upper surface, form a photoresist layer, and exposed grid corresponding to fin that still retains hard mask layer;
By etching technics partial etching, fall not get rid of the grid corresponding to fin of hard mask layer, the hard mask layer that stops at the fin top setting that still retains hard mask layer makes corresponding gate height reduction exposed;
Remove the remaining photoresist layer on described grid layer.
In order to solve the problems of the technologies described above, the invention provides a kind of fin formula field-effect transistor semi-finished product structure, it comprises:
Grid layer;
Hard mask layer, is positioned at the fin top of fin formula field-effect transistor;
Photoresist layer, is positioned at described grid layer upper surface.
Preferably, in one embodiment of this invention, the material of described protective layer is SiN or SiON.
Preferably, in one embodiment of this invention, the material of described photoresist layer is oxide material.
Preferably, in one embodiment of this invention, the thickness of described hard mask layer is not more than 10nm.
Compare with existing scheme, when separated grid, owing to having increased hard mask layer and photoresist layer in previous structure, can control accurately the accuracy of etching, avoid the damage to structure, thereby can reduce self aligned difficulty.
Accompanying drawing explanation
Fig. 1 be in prior art 3T ?the brief configuration schematic diagram of FinFet;
Fig. 2 be in prior art 3T ?the schematic equivalent circuit of FinFet;
Fig. 3 be in prior art 4T ?the brief configuration schematic diagram of FinFet;
Fig. 4 be in prior art 4T ?the schematic equivalent circuit of FinFet;
Fig. 5 and Fig. 6 are the structural representation that in prior art, transistor grinds front and back;
Fig. 7 and Fig. 8 are the structural representation before and after transistor etching in prior art;
Fig. 9 is the two grid separation method schematic flow sheet of the embodiment of the present invention one;
Figure 10 is the transistor semi-finished product structure schematic diagram after step S901 processes;
Figure 11 is the transistor semi-finished product structure schematic diagram after step S902 processes;
Figure 12 is the transistor semi-finished product structure schematic diagram after step S903 processes;
Figure 13 is the transistor semi-finished product structure schematic diagram after step S904 processes;
Figure 14 is the transistor semi-finished product structure schematic diagram after step S905 processes;
Figure 15 is the transistor semi-finished product structure schematic diagram after step S906 processes.
Embodiment
Below will coordinate graphic and embodiment to describe embodiments of the present invention in detail, and by this present invention's implementation procedure how application technology means solve technical problem and reach technology effect can be fully understood and be implemented according to this.
Fig. 9 is the two grid separation method schematic flow sheet of the embodiment of the present invention one; As shown in Figure 9, the concrete technical scheme in the present embodiment can comprise:
Step S901, on each fin top of fin formula field-effect transistor, one hard mask layer is set;
Figure 10 is the transistor semi-finished product structure schematic diagram after step S901 processes; As shown in figure 10, fin 1001 can be formed at a buried oxide layer 1000 upper surface of (buried oxide is called for short BOX).Hard mask layer 1002 is positioned at the top of fin 1001.In other words with the wafer of buried oxide layer BOX it goes without doing shallow trench isolation from (shallow trench isolation is called for short STI).It is example that the present embodiment only be take just buried oxide layer BOX, also can use body Silicon Wafer.
Step S902, partly or entirely get rid of the hard mask layer that fin top arranges selectively, and deposition of gate material forms grid layer;
In the present embodiment, by photoetching and etching, got rid of the hard mask layer that wherein a fin top arranges, and retained the hard mask layer that an other fin top arranges.
In the present embodiment, the concrete technology parameter of photoetching and etching can require to arrange flexibly by concrete technology.
Figure 11 is the transistor semi-finished product structure schematic diagram after step S902 processes; As shown in figure 11, in two fins 1001, the hard mask layer 1002 that fin 1001 tops arrange is removed, and has retained the hard mask layer 1002 that other fin 1001 tops arrange.
Step S903, deposition of gate material form grid layer;
In the present embodiment, after step S902, deposition of gate material forms grid layer.
In the present embodiment, grid material can be polysilicon, and concrete technique and parameter those of ordinary skills can arrange flexibly according to technological requirement.
Figure 12 is the transistor semi-finished product structure schematic diagram after step S903 processes; As shown in figure 12, on Figure 11 architecture basics, increased grid layer 1003.
Step S904, at described grid layer upper surface, form a photoresist layer, and exposed grid corresponding to fin that still retains hard mask layer;
In the present embodiment, the technical role that photoresist layer is passable: protect a part of grid, form the different grid structure of height by etching another part grid.
Specifically can form photoresist layer by the mode of deposition, can its concrete technology parameter be set flexibly according to technological requirement.
Figure 13 is the transistor semi-finished product structure schematic diagram after step S904 processes; As shown in figure 13, described grid layer 1003 upper surfaces form a photoresist layer 1004.
Step S905, by etching technics partial etching, fall not get rid of the grid corresponding to fin of hard mask layer, stop at and still retain the hard mask layer that the fin top of hard mask layer arranges; .
In the present embodiment, corresponding gate height is reduced also exposed.
In the present embodiment, the technological parameter of etching can be set flexibly according to technological requirement.
Figure 14 is the transistor semi-finished product structure schematic diagram after step S905 processes; As shown in figure 14, without the grid part grid material of fin 1001 correspondences of hard mask layer 1002, be removed, meanwhile, still retain the hard mask layer 1002 that fin 1001 tops of hard mask layer 1002 arrange and keep down, as the reference of etching stopping.
Step S906, remove the remaining photoresist layer on described grid layer.
In the present embodiment, can pass through wet method or dry etching, get rid of remaining photoresist layer, its concrete technological parameter can be: with O2plasma, etch away photoresistance.
Figure 15 is the transistor semi-finished product structure schematic diagram after step S906 processes; As shown in figure 15, all photoresist layers 1005 are removed, and form two different grids of height, thereby finally make transistorized two grids separately come.
It should be noted that, in the above-described embodiments, the material of described hard mask layer can but be not limited to SiN or SiON.The material of described photoresist layer can but be not limited to oxide material.The thickness of described hard mask layer can be not more than 10nm.
Above-mentioned explanation illustrates and has described some preferred embodiments of the present invention, but as previously mentioned, be to be understood that the present invention is not limited to disclosed form herein, should not regard the eliminating to other embodiment as, and can be used for various other combinations, modification and environment, and can, in invention contemplated scope described herein, by technology or the knowledge of above-mentioned instruction or association area, change.And the change that those skilled in the art carry out and variation do not depart from the spirit and scope of the present invention, all should be in the protection range of claims of the present invention.
Claims (8)
1. a two grid separation method, is characterized in that, comprising:
Each fin top at fin formula field-effect transistor arranges a hard mask layer;
Partly or entirely get rid of selectively the hard mask layer that fin top arranges, and deposition of gate material forms grid layer;
At described grid layer upper surface, form a photoresist layer, and exposed grid corresponding to fin that still retains hard mask layer;
By etching technics partial etching, fall not get rid of the grid corresponding to fin of hard mask layer, the hard mask layer that stops at the fin top setting that still retains hard mask layer makes corresponding gate height reduction exposed;
Remove the remaining photoresist layer on described grid layer.
2. method according to claim 1, is characterized in that, the material of described hard mask layer is SiN or SiON.
3. method according to claim 1, is characterized in that, the material of described photoresist layer is oxide material.
4. a fin formula field-effect transistor semi-finished product structure, is characterized in that, comprising:
Grid layer;
Hard mask layer, is positioned at the fin top of fin formula field-effect transistor;
Photoresist layer, is positioned at described grid layer upper surface.
5. semi-finished product structure according to claim 4, is characterized in that, the material of described protective layer is SiN or SiON.
6. semi-finished product structure according to claim 4, is characterized in that, the material of described photoresist layer is oxide material.
7. semi-finished product structure according to claim 4, is characterized in that, the material of described photoresist layer is oxide material.
8. semi-finished product structure according to claim 4, is characterized in that, the thickness of described hard mask layer is not more than 10nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410174398.0A CN103928348B (en) | 2014-04-28 | 2014-04-28 | Separation method for double grids |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410174398.0A CN103928348B (en) | 2014-04-28 | 2014-04-28 | Separation method for double grids |
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| Publication Number | Publication Date |
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| CN103928348A true CN103928348A (en) | 2014-07-16 |
| CN103928348B CN103928348B (en) | 2017-01-25 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104409357A (en) * | 2014-11-28 | 2015-03-11 | 上海华力微电子有限公司 | Method for forming fin type field effect transistor |
| CN104716046A (en) * | 2015-03-16 | 2015-06-17 | 上海华力微电子有限公司 | Method for manufacturing fin field effect transistor (FET) |
| CN105632936A (en) * | 2016-03-22 | 2016-06-01 | 上海华力微电子有限公司 | Fabrication method for dual-gate fin field effect transistor |
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| US7148526B1 (en) * | 2003-01-23 | 2006-12-12 | Advanced Micro Devices, Inc. | Germanium MOSFET devices and methods for making same |
| CN101027772A (en) * | 2004-09-29 | 2007-08-29 | 英特尔公司 | Independently accessed double-gate and tri-gate transistors in same process flow |
| US7902014B2 (en) * | 2005-09-28 | 2011-03-08 | Intel Corporation | CMOS devices with a single work function gate electrode and method of fabrication |
| CN102122645A (en) * | 2010-01-08 | 2011-07-13 | 中芯国际集成电路制造(上海)有限公司 | Integrated circuit structure, manufacturing method and using method thereof |
| US8426283B1 (en) * | 2011-11-10 | 2013-04-23 | United Microelectronics Corp. | Method of fabricating a double-gate transistor and a tri-gate transistor on a common substrate |
-
2014
- 2014-04-28 CN CN201410174398.0A patent/CN103928348B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7148526B1 (en) * | 2003-01-23 | 2006-12-12 | Advanced Micro Devices, Inc. | Germanium MOSFET devices and methods for making same |
| CN101027772A (en) * | 2004-09-29 | 2007-08-29 | 英特尔公司 | Independently accessed double-gate and tri-gate transistors in same process flow |
| US7902014B2 (en) * | 2005-09-28 | 2011-03-08 | Intel Corporation | CMOS devices with a single work function gate electrode and method of fabrication |
| CN102122645A (en) * | 2010-01-08 | 2011-07-13 | 中芯国际集成电路制造(上海)有限公司 | Integrated circuit structure, manufacturing method and using method thereof |
| US8426283B1 (en) * | 2011-11-10 | 2013-04-23 | United Microelectronics Corp. | Method of fabricating a double-gate transistor and a tri-gate transistor on a common substrate |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104409357A (en) * | 2014-11-28 | 2015-03-11 | 上海华力微电子有限公司 | Method for forming fin type field effect transistor |
| CN104409357B (en) * | 2014-11-28 | 2017-03-29 | 上海华力微电子有限公司 | The method for forming fin formula field effect transistor |
| CN104716046A (en) * | 2015-03-16 | 2015-06-17 | 上海华力微电子有限公司 | Method for manufacturing fin field effect transistor (FET) |
| CN105632936A (en) * | 2016-03-22 | 2016-06-01 | 上海华力微电子有限公司 | Fabrication method for dual-gate fin field effect transistor |
| CN105632936B (en) * | 2016-03-22 | 2018-10-16 | 上海华力微电子有限公司 | A kind of preparation method of bigrid fin formula field effect transistor |
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| Publication number | Publication date |
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| CN103928348B (en) | 2017-01-25 |
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