CN103871950A - Shallow trench isolation structure and manufacturing method thereof - Google Patents

Shallow trench isolation structure and manufacturing method thereof Download PDF

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Publication number
CN103871950A
CN103871950A CN201210546447.XA CN201210546447A CN103871950A CN 103871950 A CN103871950 A CN 103871950A CN 201210546447 A CN201210546447 A CN 201210546447A CN 103871950 A CN103871950 A CN 103871950A
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hard mask
mask layer
groove
semiconductor substrate
oxide layer
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Chinese (zh)
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宋化龙
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

The invention provides a shallow trench isolation structure and a manufacturing method thereof. The method comprises the following steps: (a) providing a semiconductor substrate; (b) forming a buffer oxide layer and a hard mask layer on the semiconductor substrate; (c) etching the hard mask layer, the buffer oxide layer and the semiconductor substrate to form a trench; (d) forming lining oxide layers on the inner wall and the bottom surface of the trench by adopting thermal oxidization; (e) filling the trench with a dielectric material, and flattening the dielectric material by using a chemical mechanical polishing process till a part of the hard mask layer is exposed; (f) stripping the hard mask layer and the buffer oxide layer, wherein the method further comprises a first ion injection step after the step (c) or a second ion injection step after the step (e). According to the method provided by the invention, the inverse narrow width effect can be suppressed effectively.

Description

A kind of fleet plough groove isolation structure and preparation method thereof
Technical field
The present invention relates to semiconductor applications, in particular to a kind of fleet plough groove isolation structure and preparation method thereof.
Background technology
Complete circuit is to be coupled together by specific electric path by the device separating, and in integrated circuit fabrication process, device isolation must be opened, and isolates bad meeting and causes electric leakage, latch-up etc.Therefore, isolation technology is a key technology during integrated circuit is manufactured.Existing isolation technology generally includes localized oxidation of silicon technique (LOCOS) and shallow ditch groove separation process (STI).LOCOS technological operation is simple, and it is widely applied in micron and submicrometer processing, but LOCOS technique has a series of shortcomings, for example, limit oxidation meeting formation beak (bird ' s break), make a silicon dioxide invade an active area, cause active area effective area to reduce; Field is infused in high-temperature oxidation process and occurs to distribute again, causes the narrow width effect (na rrow width effect) of active device; Live width is less, and an oxygen is thinner; Surface configuration unevenness., there are some improved LOCOS techniques in these counter productives of bringing in order to reduce LOCOS technique.But along with device develops to deep-submicron, still there is beak problem and an oxygen attenuate effect in improved LOCOS technique, has therefore occurred STI technique.
STI technique has overcome the limitation of LOCOS technique, its have excellent isolation performance, superpower latch protection ability, smooth surface configuration, to groove do not corrode and with chemico-mechanical polishing (CMP) technical compatibility.Therefore,, in 0.25 μ m and following technique, all use STI isolation technology.The flow process of STI technique mainly comprises etching, filling and the cmp planarization of groove.
Use in the semiconductor device of STI technique and can run into anti-narrow width effect (inverse narrow width effect, INWE), the threshold voltage that main manifestations is device reduces and reduces with device channel width.The reason that causes I NWE is that sharp-pointed groove drift angle makes grid electric field become concentrated, causes slot wedge to produce one with the parallel low threshold value path of active device.Along with reducing of device size, INWE has become the key factor of restriction device performance.In addition, after p trap injects, due to the boron of active area after Technology for Heating Processing in can diffuse into STI isolated area, therefore, compared with PMOS transistor, nmos pass transistor has worse INWE.
For addressing the above problem, the present invention proposes fleet plough groove isolation structure of a kind of INWE of inhibition and preparation method thereof.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The manufacture method that the invention provides a kind of fleet plough groove isolation structure, comprising: Semiconductor substrate (a) is provided; (b) in described Semiconductor substrate, form buffer oxide layer and hard mask layer; (c) hard mask layer, described buffer oxide layer and described Semiconductor substrate described in etching, to form groove; (d) adopt thermal oxidation to form lining oxide layer in inwall and the bottom surface of described groove; (e) fill described groove with dielectric material, use dielectric material described in CMP (Chemical Mechanical Polishing) process planarization, until expose a part for described hard mask layer; (f) peel off described hard mask layer and described buffer oxide layer, wherein, described method is also included in the first Implantation step afterwards of step (c) or in step (e) the second Implantation step afterwards.
As preferably, described the first Implantation step comprises: use bottom antireflective coating to fill described groove; Cure described bottom antireflective coating; Bottom antireflective coating described in etch-back part; Carry out ion implantation technology; Peel off described bottom antireflective coating.
As preferably, described the second Implantation step comprises: dielectric material described in etch-back part; Carry out ion implantation technology.
As preferably, the ion that described ion implantation technology is injected is carbon, nitrogen or germanium.
As preferably, the ion that described ion implantation technology is injected is germanium.
As preferably, described ion implantation technology is comprehensive Implantation (blanket implant).
As preferably, described hard mask layer is silicon nitride.
As preferably, also comprise afterwards described in wet etching that in step (c) the described buffer oxide layer of groove opening both sides and a part of sidewall of described hard mask layer are to expose the step of corner, described groove top.
As preferably, be also included in afterwards in step (f) step that forms gate oxide level on the active area between described fleet plough groove isolation structure.
As preferably, described gate oxide level adopts the method for the described Semiconductor substrate of oxidation to form.
As preferably, described dielectric material is silica.
According to a further aspect in the invention, also provide a kind of fleet plough groove isolation structure, described fleet plough groove isolation structure adopts any method as above to make.
The present invention, by comprehensive ion implantation technology, inject ion to form silicon doping, and the doping content of drift angle is greater than the doping content of sidewall at trenched side-wall and drift angle place.Because the silicon of doping is faster than unadulterated silicon oxidation rate, therefore, the silicon that the silicon of groove drift angle oxidation consumption consumes than sidewall oxidation in follow-up oxidation technology is many, thereby makes groove drift angle become round and smooth.In addition, the boron that the silicon doping of sidewall can suppress in Semiconductor substrate spreads in groove dielectric material, and then avoids boron to exhaust and the phenomenon such as resistance increase, threshold voltage and operating current drift of causing.Therefore, fleet plough groove isolation structure proposing according to the present invention and preparation method thereof, can suppress the impact of INWE.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Fig. 1 a-1b shows the flow chart of making according to an embodiment of the invention fleet plough groove isolation structure;
Fig. 2 a-2h shows the cutaway view of the device that in the technological process of making according to an embodiment of the invention fleet plough groove isolation structure, each step obtains;
Fig. 3 a-3b shows the flow chart of making in accordance with another embodiment of the present invention fleet plough groove isolation structure;
Fig. 4 a-4b shows the cutaway view of the device that the second Implantation step in the technological process of making in accordance with another embodiment of the present invention fleet plough groove isolation structure obtains;
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, will detailed step be proposed in following description, so that the manufacture method of the formation fleet plough groove isolation structure that explaination the present invention proposes.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, entirety, step, operation, element and/or assembly, exists or additional one or more other features, entirety, step, operation, element, assembly and/or their combination but do not get rid of.
Fig. 1 a-1b shows the flow chart of making according to an embodiment of the invention fleet plough groove isolation structure, and Fig. 2 a-2h shows the cutaway view of the device that in the technological process of making according to an embodiment of the invention fleet plough groove isolation structure, each step obtains.Describe manufacture method of the present invention in detail below in conjunction with Fig. 1 a-1b and Fig. 2 a-2h.
Execution step 101, provides Semiconductor substrate.Semiconductor substrate 201 as shown in Figure 2 a.Semiconductor substrate 201 can be at least one in following mentioned material: stacked SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.Preferably, Semiconductor substrate 201 can be silicon substrate.Although several examples of having described the material that can form Semiconductor substrate 201 at this, any material that can be used as Semiconductor substrate all falls into the spirit and scope of the present invention.In addition, Semiconductor substrate 201 can be divided active area, and/or can also be formed with dopant well (not shown) etc. in Semiconductor substrate 201.
Execution step 102 forms buffer oxide layer and hard mask layer in described Semiconductor substrate.Continue with reference to Fig. 2 a, in Semiconductor substrate 201, form buffer oxide layer 202 and hard mask layer 203.Buffer oxide layer 202 can utilize thermal oxide growth method to form, and buffer oxide layer 202 can be the silicon oxide layers of 20 dusts to 50 dusts for thickness.This layer of compact structure therefore can use as protective layer in subsequent etching technique.On buffer oxide layer 202, form hard mask layer 203, the material of hard mask layer 203 can be the composite bed that nitride or other have laminated construction, is preferably silicon nitride.The thickness of hard mask layer 203 can be 800 dust to 2500 dusts.On hard mask layer 203, can form the figuratum photoresist layer (not shown) of tool, the figuratum photoresist layer of this tool can be the photoresist forming by spin coating proceeding, then forms through techniques such as exposure, development, cleanings.The pattern that photoresist layer has is used for being formed for forming the raceway groove of fleet plough groove isolation structure.In addition,, in order to strengthen the absorptivity of photoresist layer, can before spin coating photoresist, form bottom antireflective coating etc.
Execution step 103, hard mask layer, described buffer oxide layer and described Semiconductor substrate described in etching, to form groove.As shown in Figure 2 b, successively hard mask layer 203, buffer oxide layer 202 and Semiconductor substrate 201 are carried out to etching, to form groove 204 in Semiconductor substrate 201.The selected etching gas of each etch step can be selected according to the material layer being etched.Because above-mentioned etching technics is by known in the art, therefore no longer describe in detail herein.Due to the restriction of technique at present, form the cross sectional shape of groove 204 by said method for substantially trapezoidal.
Execution step 104, carries out the first Implantation step.The detailed process of described the first Implantation step 104 is shown in Fig. 1 b.
With reference to figure 1b, execution step 108, is used bottom antireflective coating to fill described groove.As shown in Figure 2 c, use bottom antireflective coating 205 to fill described groove 204.Then, execution step 109, cures described bottom antireflective coating 205.Then, execution step 110, bottom antireflective coating 205 described in etch-back part.Then, execution step 111, carries out ion implantation technology 207, as shown in Figure 2 d.Preferably, the ion that described ion implantation technology is injected is carbon, nitrogen or germanium.Preferably, described ion implantation technology is comprehensive Implantation.Because the ion injecting is in bottom antireflective coating 205 diffusions, therefore form silicon doping at the sidewall of described groove 204, the silicon of doping can stop the boron in Semiconductor substrate 201 to spread in the dielectric material being filled in subsequently in groove 204.After step 111, perform step 112, peel off described bottom antireflective coating 205, as shown in Figure 2 e.
With reference to figure 1a, continue execution step 105, adopt thermal oxidation to form lining oxide layer in inwall and the bottom surface of described groove.As shown in Fig. 2 f, the thickness of described lining oxide skin(coating) 208 can be 50-150 dust.Lining oxide skin(coating) can improve the interfacial characteristics of Semiconductor substrate 201 and the STI dielectric material of filling subsequently.
Execution step 106, fills described groove with dielectric material, uses dielectric material described in CMP (Chemical Mechanical Polishing) process planarization, until expose a part for described hard mask layer.With reference to figure 2f, fill described groove 204 with dielectric material 209.Technique and material that trench fill adopts are well known to those skilled in the art, and do not repeat them here.As shown in Figure 2 g, use dielectric material 209 described in CMP (Chemical Mechanical Polishing) process planarization, until expose a part for hard mask layer 203.
Execution step 107, peels off described hard mask layer and described buffer oxide layer.As shown in Fig. 2 h, peel off described hard mask layer 203 and described buffer oxide layer 202, to form final fleet plough groove isolation structure.
As preferably, after step 103, also comprise described in wet etching that the described buffer oxide layer of groove opening both sides and a part of sidewall of described hard mask layer are to expose the step of corner, described groove top.As shown in Figure 2 c, the surface configuration of described groove drift angle 206 is sharp-pointed, the leakage current that this is unfavorable for the control of device grids oxide layer attenuate effect and INWE and causes device, and in the subsequent oxidation technique providing in the embodiment of the present invention, groove drift angle 206, by sphering, can effectively suppress INWE.
Fig. 3 a-3b shows the flow chart of making in accordance with another embodiment of the present invention fleet plough groove isolation structure.Embodiment shown in embodiment shown in Fig. 3 a-3b and Fig. 1 a-1b is basic identical, includes following steps: provide Semiconductor substrate (referring to Fig. 2 a); In described Semiconductor substrate, form buffer oxide layer and hard mask layer (referring to Fig. 2 a); Hard mask layer, described buffer oxide layer and described Semiconductor substrate described in etching, to form groove (referring to Fig. 2 b); Inwall and bottom surface at described groove adopt thermal oxidation to form lining oxide layer (referring to Fig. 2 f); Fill described groove with dielectric material, use dielectric material described in CMP (Chemical Mechanical Polishing) process planarization, until expose a part (referring to Fig. 2 f-2g) for described hard mask layer; Peel off described hard mask layer and described buffer oxide layer (referring to Fig. 2 h).Both differences are: the first Implantation step 104 is different from the second Implantation step 306 residing position in the technological process of making fleet plough groove isolation structure, and the first Implantation step 104 is different from the detailed process of the second Implantation step 306.For simplicity, for the step identical with above-described embodiment (embodiment shown in Fig. 2 a-2b and 2f-2h), by omit specific descriptions, those skilled in the art also can understand the concrete operations mode of identical step in conjunction with description above referring to Fig. 2 a-2b and 2f-2h.Therefore, below only different steps is described in detail.
Fig. 3 a-3b shows the flow chart of making in accordance with another embodiment of the present invention fleet plough groove isolation structure.With reference to figure 3a, filling described groove with dielectric material, use dielectric material described in CMP (Chemical Mechanical Polishing) process planarization, until perform step 306, the second Implantation steps after exposing the part of described hard mask layer.The detailed process of the second Implantation step 306 as shown in Figure 3 b.Fig. 4 a-4b is the cutaway view of making in accordance with another embodiment of the present invention the device that the second ion step in the technological process of fleet plough groove isolation structure obtains.
Execution step 308, dielectric material 401 described in etch-back part, as shown in Fig. 4 a.Then, execution step 309, carries out ion implantation technology 402.Preferably, the ion that described ion implantation technology is injected is germanium.Adopt germanium ion can reach better injection effect in the second Implantation step.Preferably, described ion implantation technology is comprehensive Implantation.
As preferably, after step 307, be also included in the step that forms gate oxide level on the active area between described fleet plough groove isolation structure.Preferably, described gate oxide level adopts the method for the described Semiconductor substrate of oxidation to form.Described oxidation can adopt oxidation technology well-known to those skilled in the art, and such as furnace oxidation, rapid thermal annealing oxidation (RTO), original position steam oxidation (ISSG) etc. form the gate oxide level of silica material.The thickness of gate oxide level is that about 5 dusts are to about 70 dusts.Owing to having carried out before comprehensive Implantation, the concentration of injecting ion is greater than sidewall concentration in the concentration at groove drift angle place, and therefore, in the oxidizing process of formation gate oxide, the oxidation rate of groove drift angle is faster than sidewall, makes groove drift angle become round and smooth.
The present invention also provides a kind of fleet plough groove isolation structure, and this fleet plough groove isolation structure adopts any method as above to make.
The method of the making fleet plough groove isolation structure providing according to the embodiment of the present invention, inject ion to form silicon doping, and the doping content of drift angle is greater than the doping content of sidewall at trenched side-wall and drift angle place.Because the silicon of doping is faster than unadulterated silicon oxidation rate, therefore, in follow-up oxidation technology, make groove drift angle become round and smooth.In addition, the boron that the silicon doping of sidewall can suppress in Semiconductor substrate spreads in groove dielectric material.Therefore, fleet plough groove isolation structure proposing according to the present invention and preparation method thereof, can suppress the impact of INWE.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.

Claims (12)

1. a manufacture method for fleet plough groove isolation structure, comprising:
(a) provide Semiconductor substrate;
(b) in described Semiconductor substrate, form buffer oxide layer and hard mask layer;
(c) hard mask layer, described buffer oxide layer and described Semiconductor substrate described in etching, to form groove;
(d) adopt thermal oxidation to form lining oxide layer in inwall and the bottom surface of described groove;
(e) fill described groove with dielectric material, use dielectric material described in CMP (Chemical Mechanical Polishing) process planarization, until expose a part for described hard mask layer; And
(f) peel off described hard mask layer and described buffer oxide layer,
It is characterized in that, described method is also included in the first Implantation step afterwards of step (c) or in step (e) the second Implantation step afterwards.
2. method according to claim 1, is characterized in that, described the first Implantation step comprises:
Use bottom antireflective coating to fill described groove;
Cure described bottom antireflective coating;
Bottom antireflective coating described in etch-back part;
Carry out ion implantation technology;
Peel off described bottom antireflective coating.
3. method according to claim 1, is characterized in that, described the second Implantation step comprises:
Dielectric material described in etch-back part;
Carry out ion implantation technology.
4. method according to claim 2, is characterized in that, the ion that described ion implantation technology is injected is carbon, nitrogen or germanium.
5. method according to claim 3, is characterized in that, the ion that described ion implantation technology is injected is germanium.
6. according to the method in claim 2 or 3, it is characterized in that, described ion implantation technology is comprehensive Implantation.
7. method according to claim 1, is characterized in that, described hard mask layer is silicon nitride.
8. method according to claim 1, is characterized in that, also comprises afterwards described in wet etching that in step (c) the described buffer oxide layer of groove opening both sides and a part of sidewall of described hard mask layer are to expose the step of corner, described groove top.
9. method according to claim 3, is also included in step (f) step that forms gate oxide level on the active area between described fleet plough groove isolation structure afterwards.
10. method according to claim 9, described gate oxide level adopts the method for the described Semiconductor substrate of oxidation to form.
11. methods according to claim 1, described dielectric material is silica.
12. 1 kinds of fleet plough groove isolation structures, is characterized in that, described fleet plough groove isolation structure adopts and makes according to any method in claim 1-11.
CN201210546447.XA 2012-12-14 2012-12-14 Shallow trench isolation structure and manufacturing method thereof Pending CN103871950A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105206520A (en) * 2014-06-25 2015-12-30 中芯国际集成电路制造(上海)有限公司 Manufacture method of floating gates
WO2020098738A1 (en) * 2018-11-16 2020-05-22 Changxin Memory Technologies, Inc. Semiconductor device and fabricating method thereof
CN117423659A (en) * 2023-12-19 2024-01-19 合肥晶合集成电路股份有限公司 Semiconductor structure and manufacturing method thereof
CN117747536A (en) * 2024-02-21 2024-03-22 合肥晶合集成电路股份有限公司 Method for manufacturing semiconductor device

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US20050037594A1 (en) * 2003-08-15 2005-02-17 Wu Chao-Chueh [method of doping sidewall of isolation trench]
US20060051926A1 (en) * 2004-09-07 2006-03-09 Chul Jeong Methods of forming semiconductor devices having a trench with beveled corners
US20100219501A1 (en) * 2006-03-07 2010-09-02 Micron Technology, Inc. Trench isolation implantation
CN102122630A (en) * 2010-01-08 2011-07-13 中芯国际集成电路制造(上海)有限公司 Fabrication method of shallow trench isolation (STI) structure

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040005764A1 (en) * 2002-07-05 2004-01-08 Taiwan Semiconductor Manufacturing Co., Ltd. Ion implant method for topographic feature corner rounding
US20050037594A1 (en) * 2003-08-15 2005-02-17 Wu Chao-Chueh [method of doping sidewall of isolation trench]
US20060051926A1 (en) * 2004-09-07 2006-03-09 Chul Jeong Methods of forming semiconductor devices having a trench with beveled corners
US20100219501A1 (en) * 2006-03-07 2010-09-02 Micron Technology, Inc. Trench isolation implantation
CN102122630A (en) * 2010-01-08 2011-07-13 中芯国际集成电路制造(上海)有限公司 Fabrication method of shallow trench isolation (STI) structure

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105206520A (en) * 2014-06-25 2015-12-30 中芯国际集成电路制造(上海)有限公司 Manufacture method of floating gates
CN105206520B (en) * 2014-06-25 2018-02-02 中芯国际集成电路制造(上海)有限公司 A kind of preparation method of floating boom
WO2020098738A1 (en) * 2018-11-16 2020-05-22 Changxin Memory Technologies, Inc. Semiconductor device and fabricating method thereof
CN117423659A (en) * 2023-12-19 2024-01-19 合肥晶合集成电路股份有限公司 Semiconductor structure and manufacturing method thereof
CN117423659B (en) * 2023-12-19 2024-04-12 合肥晶合集成电路股份有限公司 Semiconductor structure and manufacturing method thereof
CN117747536A (en) * 2024-02-21 2024-03-22 合肥晶合集成电路股份有限公司 Method for manufacturing semiconductor device

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