CN103871857A - Forming method of semiconductor device - Google Patents
Forming method of semiconductor device Download PDFInfo
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- CN103871857A CN103871857A CN201210553295.6A CN201210553295A CN103871857A CN 103871857 A CN103871857 A CN 103871857A CN 201210553295 A CN201210553295 A CN 201210553295A CN 103871857 A CN103871857 A CN 103871857A
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- 238000000034 method Methods 0.000 title claims abstract description 65
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 239000010410 layer Substances 0.000 claims abstract description 101
- 239000011229 interlayer Substances 0.000 claims abstract description 39
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000004020 conductor Substances 0.000 claims abstract description 23
- 238000001312 dry etching Methods 0.000 claims description 16
- 229920000642 polymer Polymers 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- 229910004166 TaN Inorganic materials 0.000 claims description 4
- 229910004200 TaSiN Inorganic materials 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 description 28
- 239000002184 metal Substances 0.000 description 28
- 238000005516 engineering process Methods 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical group CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 230000008054 signal transmission Effects 0.000 description 4
- 150000005846 sugar alcohols Polymers 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000003518 caustics Substances 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Abstract
The invention provides a forming method of a semiconductor device. The method comprises the following steps that a semiconductor substrate is provided, a first pseudo grid electrode and a second pseudo grid electrode which are mutually separated are formed on the semiconductor substrate in the grid line direction, an interlayer dielectric layer is formed on the semiconductor substrate; after the formation of the interlayer dielectric layer, the first pseudo grid electrode is removed, a first pseudo grid groove is formed, and a first grid electrode is formed in the first pseudo grid groove; after the first grid electrode is formed, the second pseudo grid electrode is removed, a second pseudo grid groove is formed, and a second grid electrode is formed in the second pseudo grid groove; partial or all interlayer dielectric layer formed between the first grid electrode and the second grid electrode is removed, and a groove for connecting the first grid electrode and the second grid electrode is formed; conducting materials are filled in the groove, and the first grid electrode and the second grid electrode are electrically connected. The technical scheme is adopted, the method has the advantages that a transistor with the first grid electrode and a transistor with the second grid electrode can realize more stable and more sensitive cooperated work, and the performance of the semiconductor device is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of semiconductor device.
Background technology
In the prior art, " rear grid (gate last) " technique is a main technique that forms metal gates.The feature of this technology is to form metal gates after silicon chip is leaked/source region Implantation operation and high-temperature annealing step subsequently complete again.
In the prior art, exist the rear grid technique of application to make the integrated circuit of PMOS transistor AND gate nmos pass transistor collaborative work.Wherein, PMOS transistor, nmos pass transistor metal gates adjacent in some integrated circuits are in contact with one another in grid line direction (vertical source electrode and drain electrode line direction), realize the mutual electrical connection of two metal gates by the contact of two adjacent metal grids.In rear grid technique, between the transistorized metal gates of PMOS and the metal gates of adjacent NMOS, contact quality, be one of key factor affecting performance of semiconductor device.Form in the prior art PMOS transistor metal gates and nmos pass transistor metal gates method is: with reference to Fig. 1, Semiconductor substrate 10 is provided, in Semiconductor substrate 10, is formed with the first metal gates 11, pseudo-grid 12, the interlayer dielectric layer 13 adjacent with the first metal gates 11.With reference to Fig. 2, form patterned photoresist layer 14, expose pseudo-grid 12.Continue with reference to Fig. 3, take patterned photoresist layer 14 as mask, dry etching is removed pseudo-grid 12, forms pseudo-gate groove 121, and afterwards, wet etching is removed the polymer of pseudo-gate groove 121 sidewalls and bottom.Finally, with reference to Fig. 4, remove patterned photoresist layer 14, in pseudo-gate groove 121, form the second metal gates 15.Wherein, the transistorized metal gates of the corresponding PMOS of the first metal gates 11, the metal gates of the second metal gates 15 corresponding nmos pass transistors, or contrary.
But the performance of the semiconductor device in grid line direction with two metal gates that are in contact with one another that the rear grid technique of use prior art is made is not good.
More knowledge about rear grid technique, please refer to the Chinese patent literature disclosed, the patent No. is CN102044421A on May 4th, 2011.
Summary of the invention
The problem that the present invention solves is that the performance of the semiconductor device that forms of the rear grid technique of prior art is not good.
For addressing the above problem, the invention provides a kind of formation method of new semiconductor device, comprising:
Semiconductor substrate is provided, along grid line direction, in described Semiconductor substrate, is formed with the first dummy grid spaced apart from each other and the second dummy grid;
In described Semiconductor substrate, form interlayer dielectric layer;
Form after described interlayer dielectric layer, remove described the first dummy grid, form the first pseudo-gate groove, in the first pseudo-gate groove, form first grid;
Form after described first grid, remove described the second dummy grid, form the second pseudo-gate groove, in the second pseudo-gate groove, form second grid;
Remove the part or all of interlayer dielectric layer between described first grid and second grid, form the groove that connects first grid and second grid;
Filled conductive material in described groove, by first grid and second grid electrical connection.
Optionally, form the method for the first dummy grid and the second dummy grid, comprising:
In Semiconductor substrate, form dummy gate layer;
Graphical described dummy gate layer, forms dummy grid;
Described dummy grid is divided into the first dummy grid spaced apart from each other, the second dummy grid.
Optionally, form the method for the groove that connects first grid and second grid, comprising:
On described interlayer dielectric layer, first grid and second grid, form patterned mask layer, define the position of groove to be formed;
Take described patterned mask layer as mask, etched portions or all interlayer dielectric layer, form the groove that connects first grid and second grid;
Remove patterned mask layer.
Optionally, forming after the first dummy grid and the second dummy grid, before forming interlayer dielectric layer, also comprising:
In the Semiconductor substrate of the first dummy grid both sides, carry out Implantation, form the first source region and the first drain region;
In the Semiconductor substrate of the second dummy grid both sides, carry out Implantation, form the second source region and the second drain region, wherein, the first source region is different from the type in the second source region and the second drain region with the first drain region.
Optionally, the ion injecting in the first source region and the first drain region is N-type ion, and the ion injecting in the second source region and the second drain region is P type ion.
Optionally, remove the method for the first dummy grid, comprising:
Form patterned mask layer, the position of definition the first dummy grid;
Take described patterned mask layer as mask, use dry etching to remove the first dummy grid;
Use wet etching to remove the polymer forming in described dry etching;
Remove patterned mask layer.
Optionally, remove the method for the second dummy grid, comprising:
Form patterned mask layer, the position of definition the second dummy grid;
Take patterned mask layer as mask, use dry etching to remove the second dummy grid;
Use wet etching to remove the polymer forming in described dry etching;
Remove patterned mask layer.
Optionally, before forming patterned mask layer, form titanium nitride layer, cover interlayer dielectric layer, first grid, the second dummy grid.
Optionally, use dry etching to remove the first dummy grid or the second dummy grid, the etching gas of use comprises O
2.
Optionally, the etching gas of use also comprises NF
3, HBr or CF
4in one or more.
Optionally, while removing the part or all of interlayer dielectric layer formation groove between described first grid and second grid, also remove the sidewall that described first grid, second grid and groove are adjacent.
Optionally, described conductive materials is tungsten.
Optionally, the material of described the first dummy grid and the second dummy grid comprises polysilicon, silicon nitride or amorphous carbon.
Optionally, the material of described first grid and second grid comprises: one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi.
Compared with prior art, the present invention has the following advantages:
The present invention utilizes rear grid technique to be formed in the process of interconnective first grid and second grid in grid line direction, first forms the first dummy grid spaced apart from each other and the second dummy grid.Afterwards, on substrate, form interlayer dielectric layer.Then, remove the first dummy grid and the second dummy grid, form first grid and second grid.Forming after first grid and second grid, remove the part or all of interlayer dielectric layer between first grid and second grid, form groove.Then, filled conductive material in groove, by first grid and second grid electrical connection.Conductive materials in groove directly couples together first grid and second grid, and first grid and second grid are realized accessible close contact.Like this, signal transmission between first grid and second grid is stable, responsive, and the transistor AND gate that makes to have first grid has the transistor of second grid can realize more stable, collaborative work more sensitively, has promoted the performance of semiconductor device.In addition, in advance the first dummy grid and the second dummy grid are separated, not only create conditions for follow-up formation groove, also make, removing in the process of the first dummy grid or the second dummy grid, can not impact adjacent dummy grid or grid.As, in the second dummy grid process of removal, especially wet etching is removed in residual polyalcohol process, and corrosive agent can not produce corrosion to first grid, guarantees that first grid is complete, has also stablized transistorized performance.
Accompanying drawing explanation
Fig. 1～Fig. 4 is the cross-sectional view of method in grid line direction that the rear grid technique of prior art forms semiconductor device;
Fig. 5 is the method flow schematic diagram of the formation semiconductor device of the specific embodiment of the invention;
Fig. 6 a, Fig. 6 b～Figure 11 a, 11b are the method structural representations of the formation semiconductor device of the specific embodiment of the invention.
Embodiment
The problem that inventor exists for the rear grid technique of prior art, is studied, and finds: using dry etching to remove in dummy grid, can generate polymer, be attached to bottom and the sidewall of pseudo-gate groove.For example, in dry etch process, conventionally in etching reaction chamber, pass into oxygen, partial oxidation can with polysilicon or etching reaction chamber in other materials react, generate oxide, oxide can be considered a kind of composition of polymer.Although, follow-up use wet etching is removed polymer, but in prior art, normally used corrosive agent is 1-METHYLPYRROLIDONE (NMP, N-methyl-2-pyrrolidone) solvent or EKC solvent (a kind of alkaline solution being provided by EKC Technology Inc of Du Pont), the ability of the corrosion of described solvent a little less than, most polymer can not be removed.This can produce following problem: with reference to Fig. 3, be attached on the first metal gates 11 at the not removed polymer of side-walls of pseudo-gate groove 121.Like this, in the interface of the first metal gates 11 and the second metal gates 15, assemble and have residual polymer, the electrical connection between the first metal gates 11 and the second metal gates 15 is produced to negative influence, make the transmission of signal between adjacent transistor unstable, reduce the performance of semiconductor device.If the residual polyalcohol in the interface of the first metal gates 11 and the second metal gates 15 is thicker, can make between adjacent transistor cannot transmission of signal, and semiconductor device cannot be worked, and has a strong impact on the performance of semiconductor device.
Inventor, for the problems referred to above, through creative work, obtains a kind of formation method of new semiconductor device.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.A lot of details are set forth in the following description so that fully understand the present invention.But the present invention can implement to be much different from other modes described here, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that, and therefore the present invention is not subject to the restriction of following public specific embodiment.
The method structural representation of the formation semiconductor device that Fig. 6 a, Fig. 6 b～Figure 11 a, Figure 11 b are the specific embodiment of the invention, wherein, the structure top view of the formation semiconductor device method that Fig. 6 a～Figure 11 a is the specific embodiment of the invention, the formation semiconductor device method that Fig. 6 b～Figure 11 b is the specific embodiment of the invention is along the cross-sectional view of grid line direction.
With reference to Fig. 6 a, Fig. 6 b, and in conjunction with reference to Fig. 5, perform step S51, Semiconductor substrate 300 is provided, along grid line direction (vertical source electrode is to drain directions), in Semiconductor substrate 300, form the first dummy grid 311 spaced apart from each other and the second dummy grid 321.That is to say, between the first dummy grid 311 and the second dummy grid 321, have space in grid line direction, relative as the surface of the surface of the first dummy grid 311 of space sidewall, the second dummy grid 321.
In specific embodiment, the material of described Semiconductor substrate 300 can be monocrystalline silicon, monocrystalline germanium or single-crystal silicon Germanium; Also can be silicon-on-insulator (SOI); Or can also comprise other material, III-V compounds of group such as such as GaAs.In described Semiconductor substrate 300, be formed with device architecture (not shown), the isolation structures such as such as isolation trench structure are for the isolation between adjacent transistor.
In specific embodiment, in Semiconductor substrate 300, form the method for the first dummy grid 311 spaced apart from each other and the second dummy grid 321, comprise: in Semiconductor substrate 300, form dummy gate layer (not shown), the material of described dummy gate layer can be selected polysilicon, amorphous carbon or silicon nitride, and the method that forms dummy gate layer can be chemical vapour deposition (CVD); Graphical described dummy gate layer, forms dummy grid; Described dummy grid is divided into the first dummy grid 311 spaced apart from each other and the second dummy grid 321.Wherein, the method that described dummy grid is divided into the first dummy grid 311 spaced apart from each other and the second dummy grid 321 is: form patterned photoresist layer, define the dummy grid part between the first dummy grid 311 and the second dummy grid 321 to be formed; Take described patterned photoresist layer as mask, etching dummy grid to semiconductor substrate surface stops; Remove patterned photoresist layer, form the first dummy grid 311 spaced apart from each other and the second dummy grid 321.
Execution step S51, separates the first dummy grid 311 and the second dummy grid 321, and can make follow-up removal the second dummy grid 321 time, the polymer that uses dry etching to produce, can not be attached on adjacent first grid.And, again the opening between first grid and second grid is filled in rear extended meeting, adjacent transistor is connected.
With reference to Fig. 7 a and Fig. 7 b, in conjunction with reference to Fig. 5, perform step S52, in Semiconductor substrate 300, form interlayer dielectric layer 302.If be not all formed with hard mask layer on the first dummy grid 311 and the second dummy grid 321, the upper surface of the upper surface of interlayer dielectric layer 302 and the first dummy grid 311, the second dummy grid 321 maintains an equal level; If be all formed with hard mask layer on the first dummy grid 311 and the second dummy grid 321, the upper surface of interlayer dielectric layer 302 and the upper surface of hard mask layer maintain an equal level.Because Fig. 7 a is top view, Semiconductor substrate is not visible, therefore not shown.
In specific embodiment, the common selective oxidation silicon of the material of interlayer dielectric layer 302, also has other can material selection certainly, can select according to actual needs.The step that forms interlayer dielectric layer 302, is generally first to deposit, then carries out planarization, for example chemico-mechanical polishing or time quarter.
In concrete production, forming after the first dummy grid and the second dummy grid, before forming interlayer dielectric layer, in the Semiconductor substrate of the first dummy grid both sides, carry out Implantation, form the first source region and the firstth drain region; Afterwards, in the Semiconductor substrate of the second dummy grid both sides, carry out Implantation, form the second source region and the second drain region.Wherein, the first source region and the first drain region, different from the ionic type injecting in the second source region and the second drain region.If the ion injecting in the first source region and the first drain region is N-type ion, the first source region and the first drain region are as source electrode and the drain electrode of P transistor npn npn, correspondingly, the ion injecting in the second source region and the second drain region is P type ion, and the second source region and the second drain region are as the transistorized source electrode of N-type and drain electrode.Otherwise if the ion injecting in the first source region and the first drain region is P type ion, the ion injecting in the second source region and the second drain region is N-type ion.
With reference to Fig. 8 a, Fig. 8 b, and in conjunction with reference to Fig. 5, perform step S53, form after interlayer dielectric layer 302, remove the first dummy grid 311, form the first pseudo-gate groove (not shown), in the first pseudo-gate groove, form first grid 311'.According to the selection of the electric conducting material of filling in the first pseudo-gate groove, if electric conducting material is metal, first grid 311' is metal gates.In the present embodiment, form first grid 311' in the first pseudo-gate groove before, form high K dielectric layer in the bottom of the first pseudo-gate groove, as gate dielectric layer, on gate dielectric layer, form afterwards first grid 311'.Concrete technology is known technology, repeats no more.
In specific embodiment, form the method for the first pseudo-gate groove, comprising: (1) forms patterned mask layer, the position of definition the first pseudo-gate groove, hides the second dummy grid 321.Wherein, patterned mask layer is selected photoresist conventionally.(2) take patterned mask as mask layer, use dry etching to remove the first dummy grid 311, in interlayer dielectric layer 302, form the first pseudo-gate groove (not shown).In dry etch process, the gas passing in etching reaction chamber is O
2, but be not limited to O
2, also can comprise NF
3, HBr or CF
4in one or more.In the present embodiment, the gas passing into is O
2, O
2can replenish in etching the first dummy grid 311 processes the oxygen loss in the first pseudo-gate groove sidewall (being inter-level dielectric layer segment).(3) use wet etching to remove the polymer producing in above-mentioned dry etching process, described polymer residue is in sidewall and the bottom of the first pseudo-gate groove.(4) remove patterned mask layer.
In specific embodiment, form after the first pseudo-gate groove, filled conductive material in the first pseudo-gate groove, forms first grid 311'.The electric conducting material using can be metal, comprising: one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi.The technology that concrete technology is well known to those skilled in the art, does not repeat them here.
With reference to Fig. 9 a, Fig. 9 b, and in conjunction with Fig. 5, execution step S54, forms after first grid 311', removes the second dummy grid 321, forms the second pseudo-gate groove (not shown), in the second pseudo-gate groove, forms second grid 321'.In the present embodiment, form second grid 321' in the second pseudo-gate groove before, form high K dielectric layer in the bottom of the second pseudo-gate groove, as gate dielectric layer, afterwards, on high K dielectric layer, form second grid 321'.
In specific embodiment, the step that forms the second pseudo-gate groove is identical with the step of aforementioned formation the first pseudo-gate groove, comprises photoetching, dry etching, wet etching treatment step.Optionally, in photoetching process, before forming patterned mask layer, form titanium nitride layer, cover first grid, the second dummy grid and interlayer dielectric layer.Afterwards, on titanium nitride layer, form patterned mask layer, generally select photoresist layer.Titanium nitride layer can play the effect of protection first grid, avoids forming patterned mask layer, in the process of especially patterned photoresist layer, to the electric conducting material of first grid, as metal causes damage.In this step, other concrete technology conditions please refer to the explanation of execution step S53.
In specific embodiment, the material of second grid 321' comprises one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi.
With reference to Figure 10 a, Figure 10 b, and in conjunction with reference to Fig. 5, perform step S55, remove the part or all of interlayer dielectric layer between first grid 311' and second grid 321', form the groove 303 that connects first grid 311' and second grid 321'.Groove 303 is used to form the interconnection line between first grid 311' and second grid 321', so form first grid 311 ' with being electrically connected of second grid 321'.
In specific embodiment, first on interlayer dielectric layer 302 and first grid 311', second grid 321', form patterned mask layer, define the position of groove to be formed 303; Then,, take patterned mask layer as mask, etching interlayer dielectric layer 302, forms groove 303; Finally, remove patterned mask layer.The degree of depth to groove 303 and width, be not limited to the inter-level dielectric layer segment by between first grid 311' and second grid 321' shown in Figure 10 a, Figure 10 b and entirely remove.In other embodiments, as long as first grid 311' and second grid 321' are coupled together, be all feasible.For example, remove first grid 311 ' with second grid 321' between partial depth, on grid length direction the interlayer dielectric layer of partial width, and in grid line direction by first grid 311' and second grid 321' connection.Other need only the definition that first grid is connected with second grid according to the invention, just within protection scope of the present invention.
In specific embodiment, can also be in formation groove 303 processes, in the time of the part or all of interlayer dielectric layer 302 of removing between first grid 311' and second grid 321', also remove described first grid, sidewall that second grid is adjacent with groove 303, the residual polyalcohol of groove 303 sidewalls is removed substantially.Like this, the residual polyalcohol of first grid 311' and second grid 321' sidewall can be removed substantially completely.The conductive materials forming in follow-up groove can form accessible contact with first grid 311', second grid 321'.
With reference to Figure 10 a, Figure 10 b and 11a, Figure 11 b, and in conjunction with reference to Fig. 5, perform step S56, filled conductive material 304 in groove 303, by first grid 311' and second grid 321' electrical connection.
In specific embodiment, the method of filled conductive material in groove 303, comprise: depositing electrically conductive material, cover interlayer dielectric layer 302, first grid 311' and second grid 321', and filling groove 303, the method for depositing electrically conductive material can be used physical vapour deposition (PVD), chemical vapour deposition (CVD) or sputtering technology; Removal exceeds the conductive materials on interlayer dielectric layer 302 surfaces, the conductive materials 304 in residue groove 303.In the present embodiment, the conductive materials of filling in groove 303 is tungsten (W), but is not limited to tungsten, is also feasible to other conductive materials.Described removal exceeds the conductive materials on interlayer dielectric layer 302 surfaces, uses chemico-mechanical polishing or returns carving technology.
Carry out after this step, the conductive materials 304 in groove 303 is by first grid 311 ' directly couple together with second grid 321', first grid 311 ' realize accessible close contact with second grid 321'.Like this, signal transmission between first grid 311' and second grid 321' is stable, responsive, the transistor AND gate that makes to have first grid 311' has the transistor of second grid 321' can realize more stable, collaborative work more sensitively, has promoted the performance of semiconductor device.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (14)
1. a formation method for semiconductor device, is characterized in that, comprising:
Semiconductor substrate is provided, along grid line direction, in described Semiconductor substrate, is formed with the first dummy grid spaced apart from each other and the second dummy grid;
In described Semiconductor substrate, form interlayer dielectric layer;
Form after described interlayer dielectric layer, remove described the first dummy grid, form the first pseudo-gate groove, in the first pseudo-gate groove, form first grid;
Form after described first grid, remove described the second dummy grid, form the second pseudo-gate groove, in the second pseudo-gate groove, form second grid;
Remove the part or all of interlayer dielectric layer between described first grid and second grid, form the groove that connects first grid and second grid;
Filled conductive material in described groove, by first grid and second grid electrical connection.
2. formation method as claimed in claim 1, is characterized in that, forms the method for the first dummy grid and the second dummy grid, comprising:
In Semiconductor substrate, form dummy gate layer;
Graphical described dummy gate layer, forms dummy grid;
Described dummy grid is divided into the first dummy grid spaced apart from each other, the second dummy grid.
3. formation method as claimed in claim 1, is characterized in that, forms the method for the groove that connects first grid and second grid, comprising:
On described interlayer dielectric layer, first grid and second grid, form patterned mask layer, define the position of groove to be formed;
Take described patterned mask layer as mask, etched portions or all interlayer dielectric layer, form the groove that connects first grid and second grid;
Remove patterned mask layer.
4. formation method as claimed in claim 1, is characterized in that, is forming after the first dummy grid and the second dummy grid, before forming interlayer dielectric layer, also comprises:
In the Semiconductor substrate of the first dummy grid both sides, carry out Implantation, form the first source region and the first drain region;
In the Semiconductor substrate of the second dummy grid both sides, carry out Implantation, form the second source region and the second drain region, wherein, the first source region is different from the type in the second source region and the second drain region with the first drain region.
5. formation method as claimed in claim 4, is characterized in that, the ion injecting in the first source region and the first drain region is N-type ion, and the ion injecting in the second source region and the second drain region is P type ion.
6. formation method as claimed in claim 1, is characterized in that, removes the method for the first dummy grid, comprising:
Form patterned mask layer, the position of definition the first dummy grid;
Take described patterned mask layer as mask, use dry etching to remove the first dummy grid;
Use wet etching to remove the polymer forming in described dry etching;
Remove patterned mask layer.
7. formation method as claimed in claim 1, is characterized in that, removes the method for the second dummy grid, comprising:
Form patterned mask layer, the position of definition the second dummy grid;
Take patterned mask layer as mask, use dry etching to remove the second dummy grid;
Use wet etching to remove the polymer forming in described dry etching;
Remove patterned mask layer.
8. formation method as claimed in claim 7, is characterized in that, before forming patterned mask layer, forms titanium nitride layer, covers interlayer dielectric layer, first grid, the second dummy grid.
9. the formation method as described in claim 6 or 7, is characterized in that, uses dry etching to remove the first dummy grid or the second dummy grid, and the etching gas of use comprises O
2.
10. formation method as claimed in claim 9, is characterized in that, the etching gas of use also comprises NF
3, HBr or CF
4in one or more.
11. formation methods as claimed in claim 1, is characterized in that, while removing the part or all of interlayer dielectric layer formation groove between described first grid and second grid, also remove the sidewall that described first grid, second grid and groove are adjacent.
12. formation methods as claimed in claim 1, is characterized in that, described conductive materials is tungsten.
13. formation methods as claimed in claim 1, is characterized in that, the material of described the first dummy grid and the second dummy grid comprises polysilicon, silicon nitride or amorphous carbon.
14. formation methods as claimed in claim 1, is characterized in that, the material of described first grid and second grid comprises: one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi.
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| CN105513964A (en) * | 2014-09-24 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Formation method of transistor |
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| US6171910B1 (en) * | 1999-07-21 | 2001-01-09 | Motorola Inc. | Method for forming a semiconductor device |
| CN102347227A (en) * | 2010-07-30 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Metal gate formation method |
| CN102479716A (en) * | 2010-11-29 | 2012-05-30 | 中芯国际集成电路制造(北京)有限公司 | Manufacturing method of transistor |
| CN102640291A (en) * | 2009-12-30 | 2012-08-15 | 英特尔公司 | Self-aligned contacts |
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| US6171910B1 (en) * | 1999-07-21 | 2001-01-09 | Motorola Inc. | Method for forming a semiconductor device |
| CN102640291A (en) * | 2009-12-30 | 2012-08-15 | 英特尔公司 | Self-aligned contacts |
| CN102347227A (en) * | 2010-07-30 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Metal gate formation method |
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