CN103681375B - Square plane pin-free semiconductor packaging part and manufacturing method thereof - Google Patents
Square plane pin-free semiconductor packaging part and manufacturing method thereof Download PDFInfo
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- CN103681375B CN103681375B CN201210356342.8A CN201210356342A CN103681375B CN 103681375 B CN103681375 B CN 103681375B CN 201210356342 A CN201210356342 A CN 201210356342A CN 103681375 B CN103681375 B CN 103681375B
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- electric connection
- square planar
- semiconductor packaging
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 238000004806 packaging method and process Methods 0.000 title claims description 33
- 238000004519 manufacturing process Methods 0.000 title 1
- 229910052751 metal Inorganic materials 0.000 claims abstract description 66
- 239000002184 metal Substances 0.000 claims abstract description 66
- 239000000084 colloidal system Substances 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000012856 packing Methods 0.000 claims description 37
- 238000002360 preparation method Methods 0.000 claims description 36
- 239000010931 gold Substances 0.000 claims description 32
- 238000003466 welding Methods 0.000 claims description 28
- 229910052737 gold Inorganic materials 0.000 claims description 19
- 239000010949 copper Substances 0.000 claims description 18
- 229910052763 palladium Inorganic materials 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 7
- 229910001021 Ferroalloy Inorganic materials 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 238000007772 electroless plating Methods 0.000 claims description 3
- 238000004381 surface treatment Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 32
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 23
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 22
- 238000010586 diagram Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910000677 High-carbon steel Inorganic materials 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- 229910001209 Low-carbon steel Inorganic materials 0.000 description 1
- 229910000954 Medium-carbon steel Inorganic materials 0.000 description 1
- 229910001037 White iron Inorganic materials 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000010956 nickel silver Substances 0.000 description 1
- MOFOBJHOKRNACT-UHFFFAOYSA-N nickel silver Chemical compound [Ni].[Ag] MOFOBJHOKRNACT-UHFFFAOYSA-N 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
A quad flat non-leaded semiconductor package and a method for fabricating the same, the quad flat non-leaded semiconductor package comprising: the semiconductor package comprises a package colloid, a metal layer which is wide at the top and narrow at the bottom and is embedded on the lower surface of the package colloid, a plurality of electric connection pads which are embedded in the package colloid and combined on the metal layer, and a semiconductor chip which is embedded in the package colloid and electrically connected with the electric connection pads.
Description
Technical field
The present invention relates to a kind of semiconductor package part and its preparation method, espespecially a kind of square planar guide-pin-free semiconductor packaging part
And its preparation method.
Background technology
With the exhibition of breaking out of meeting of electronic industry, many high-order electronic products are all gradually towards toward light, thin, short, little contour aggregation
Degree direction is developed, and semiconductor package also develops the different circuit module of many kinds, wherein, without lead foot semiconductor package part
It is a kind of special circuit module, is characterized in that soldered ball all exposes to semiconductor package part bottom, it combines and adopts surface coupling mode.
Surface coupling is made in engaging process in quasiconductor and printed circuit board (PCB), encapsulation unit is directly welded and is tied to printed circuit board (PCB),
Enable the pin without lead foot semiconductor package part and circuit board fluid-tight engagement.
For example, the preparation method of the existing square planar guide-pin-free semiconductor packaging part 2 as shown in Fig. 2A to Fig. 2 D.
As shown in Fig. 2A and Fig. 2A ', there is provided a carrier 21, its material is copper, formed on the carrier 21 chip carrier 41a and
The electric connection pad 41b each and every one being located on more around chip carrier 41a, and as shown in Fig. 2A ', at least the part electric connection pad
41b is extended with conductive trace 42b.
As shown in Figure 2 B, connect on chip carrier 41a top surfaces and put semiconductor chip 51, being then electrically connected with bonding wire 61 should
Semiconductor chip 51 and respectively electric connection pad 41b, form afterwards packing colloid 71, to coat the chip on the carrier 21
Seat 41a, electric connection pad 41b, semiconductor chip 51 and bonding wire 61.
As shown in Figure 2 C, the carrier 21 is removed, the envelope is exposed outside with the bottom surface for making chip carrier 41a and electric connection pad 41b
The bottom surface of dress colloid 71.
As shown in Figure 2 D, welding resisting layer 81 is formed in the bottom surface of the packing colloid 71, chip carrier 41a and electric connection pad 41b,
And the welding resisting layer 81 has the welding resisting layer opening 811 of the portion bottom surface of multiple exposed chip seat 41a and electric connection pad 41b, connects
The formation soldered ball 91 in the welding resisting layer opening 811.
However, the side of the chip carrier 41a and electric connection pad 41b of the semiconductor package part 2 is generally presented plane, hold
Easily come off from the packing colloid 71, affect product reliability.
Therefore, a kind of square planar guide-pin-free semiconductor packaging part and preparation method how are provided, can ensure that the reliability of product
Spend, actually an important topic.
The content of the invention
In view of the defect of above-mentioned prior art, present invention is primarily targeted at provide a kind of square planar guide-pin-free partly leading
Body packaging part and its preparation method so that the electric connection pad is difficult from the packing colloid to come off, and can lift reliability.
The square planar guide-pin-free semiconductor packaging part of the present invention, it includes：Packing colloid, it has the first relative table
Face and second surface；Metal level, it is configuration wide at the top and narrow at the bottom, and is embedded on the second surface of the packing colloid；Multiple electricity
Property connection gasket, it is embedded in the packing colloid and is incorporated in the upper wide configuration of the metal level；And semiconductor chip, it is embedded in
In the packing colloid and it is electrically connected with those electric connection pads.
In aforesaid semiconductor package part and its preparation method, the metal level is the coat of metal.
The present invention also provides a kind of preparation method of square planar guide-pin-free semiconductor packaging part, and it includes：Form multiple electrical
Connection is padded on the metal level on a carrier；The metal level not covered by the electric connection pad is removed, the partly load is exposed in addition
Body, and make the metal level below the electric connection pad that there is configuration wide at the top and narrow at the bottom；Connect and put semiconductor chip in the carrier top,
And make the semiconductor chip be electrically connected with those electric connection pads；Packing colloid is formed on the carrier, to coat the quasiconductor
Chip and the electric connection pad and metal level below, and the packing colloid has relative first surface and second surface,
And the second surface of the packing colloid is contacted with the carrier；And the carrier is removed, to appear the second surface of the packing colloid
With the metal level below the electric connection pad.
In aforesaid preparation method, forming the technique of the electric connection pad includes：Formed with multiple resistance layer openings resistance layer in
On the metal level of the carrier, exposed portion metal level in addition；Plating forms the electric connection and is padded in the resistance layer opening；And
Remove the resistance layer.
In aforesaid preparation method, the carrier is ferroalloy carrier.
In aforesaid preparation method, the metal level surface treated of the carrier and obtain, and the mode of the surface treatment be physics gas
Phase deposition, plating, electroless plating or sputter.
In aforesaid preparation method, it removes the metal level not covered by the electric connection pad with etching mode, to make this electrical
Metal level below connection gasket has configuration wide at the top and narrow at the bottom.
In aforesaid semiconductor package part and its preparation method, the material for forming the metal level is copper.
In aforesaid semiconductor package part and its preparation method, the material for forming the electric connection pad is Au/Pd/Ni/Pd, Au/
Ni/Cu/Ni/Ag, Au/Ni/Cu/Ag, Pd/Ni/Pd, Au/Ni/Au or Pd/Ni/Au.
In aforesaid semiconductor package part and its preparation method, also have at least one to put brilliant pad on the metal level of the carrier, to set
The semiconductor chip is put, and those electric connection pads are put around brilliant pad positioned at this.
In aforesaid semiconductor package part and its preparation method, also including forming welding resisting layer in the second surface of the packing colloid
On, and the welding resisting layer has multiple welding resisting layer openings for exposing outside the metal level.Also include forming conductive component in the welding resisting layer
In opening.
In aforesaid semiconductor package part and its preparation method, the semiconductor chip is electrically connected with those with conductive projection or bonding wire
Electric connection pad.
From the foregoing, it will be observed that the present invention replaces copper alloy carrier with ferroalloy carrier, it is possible to decrease use cost.Furthermore, using copper
Conduction can be lifted as the coat of metal of ferroalloy carrier surface electrically, advantageously form and put brilliant pad and electric connection pad.
Additionally, preparation method of the invention, because being pre-formed metal level on the carrier, so packaging technology is without the need in shape
Protective layer is re-formed into before welding resisting layer, on the other hand, when the packing colloid envelopes metal level, the metal level is wide at the top and narrow at the bottom
Configuration can form anchor-shaped inlay card, it is to avoid this puts brilliant pad and electric connection pad comes off from packing colloid, is further lifted and is trusted
Property.
Description of the drawings
Figure 1A to Fig. 1 H is the preparation method schematic diagram for showing square planar guide-pin-free semiconductor packaging part of the present invention, wherein, figure
1E ' is the section view enlarged diagram for showing electric connection pad, and Fig. 1 H' and Fig. 1 H are " for the other embodiments of Fig. 1 H；And
Fig. 2A to Fig. 2 D is the preparation method schematic diagram for showing existing square planar guide-pin-free semiconductor packaging part, wherein, figure
2A' is the upper schematic diagram of Fig. 2A.
Primary clustering symbol description
1,1', 1 ", 2 semiconductor package parts
10 metal levels
20th, 21 carrier
30 resistance layers
301 resistance layer openings
40a puts brilliant pad
41a chip carriers
40b, 41b electric connection pad
42b conductive traces
50th, 51 semiconductor chip
500 sticky materials
60th, 61 bonding wire
62 conductive projections
70th, 71 packing colloid
70a first surfaces
70b second surfaces
80th, 81 welding resisting layer
801st, 811 welding resisting layer opening
90 conductive components
91 soldered balls.
Specific embodiment
Hereinafter embodiments of the present invention are illustrated by specific instantiation, those skilled in the art can be by this specification
Disclosed content understands easily the further advantage and effect of the present invention.The present invention also can be by other different instantiations
Implemented or applied, the every details in this specification may be based on different viewpoints and application, in the essence without departing substantially from the present invention
Various modifications and change are carried out under god.
It should be clear that structure, ratio, size depicted in this specification institute accompanying drawings etc., only to coordinate description to be taken off
The content shown, for understanding and the reading of those skilled in the art, is not limited to enforceable qualificationss of the invention, institute
Not have technical essential meaning, the modification of any structure, the change of proportionate relationship or the adjustment of size are not affecting this
Under bright effect that can be generated and the purpose to be reached, all should still fall obtain what is can covered in disclosed technology contents
In the range of.Meanwhile, in this specification cited such as " first ", " second ", " the 3rd " and " on " term, be also only and be easy to chat
That what is stated understands, and is not used to limit enforceable scope of the invention, and being altered or modified for its relativeness is changing skill without essence
Hold in art, when being also considered as enforceable category of the invention.
Figure 1A to Fig. 1 H is the generalized section of the preparation method for showing square planar guide-pin-free semiconductor packaging part 1 of the present invention.
As shown in Figure 1A, there is provided the carrier 20 of the metal level 10 with material such as copper on a surface.
In the present embodiment, the top surface of the carrier 20 and bottom surface all have metal level 10, certainly also can only at top surface or bottom
Face forms a metal level 10.The carrier 20 can be ferroalloy carrier, and be surface-treated the carrier 20 in advance and obtain metal level 10, and
The metal level 10 is the coat of metal, such as copper.
Additionally, the carrier 20 be ferroalloy when, its may be selected from mild steel, medium carbon steel, high-carbon steel, casting pig, white iron and
Any ferrum carbon bianry alloy for being doped into other foreign atoms.In addition, the surface treatment method includes：Physical vapour deposition (PVD), electricity
Plating, electroless plating or sputter.
As shown in Figure 1B, using patterning techniques, form the resistance layer 30 with multiple resistance layer openings 301 and push up in the carrier 20
On the metal level 10 in face, exposed portion metal level 10 in addition.
As shown in Figure 1 C, multiple crystalline substance pad 40a and electric connection pad 40b that put are formed in the way of such as plating to open in the resistance layer
In mouth 301.In the present embodiment, formed it is multiple put brilliant pad 40a, and those electric connection pads 40b to be located at and put quasiconductor connecing
The multiple of chip put the overall surroundings of brilliant pad 40a；In another embodiment, can only form multiple electric connection pad 40b and not formed
This puts brilliant pad 40a.The material for putting brilliant pad 40a and electric connection pad 40b is Au/Pd/Ni/Pd (gold/palladium/nickel/palladium), Au/Ni/
Cu/Ni/Ag (gold/nickel copper/nickel silver), Au/Ni/Cu/Ag (gold/nickel copper/silver), Pd/Ni/Pd (palladium/nickel/palladium), Au/Ni/Au
(gold/ni au) or Pd/Ni/Au (palladium/ni au), sequentially forms from the storehouse of metal level 10.
As shown in Fig. 1 D to Fig. 1 E, the resistance layer 30 is removed, then removed in the way of such as etching and brilliant pad 40a is not put by this
The metal level 10 covered with electric connection pad 40b, exposes in addition the partly carrier 20.As shown in Fig. 1 E ', due to the metal level 10
Side etching phenomenon is produced, respectively the metal level 10 put below brilliant pad 40a and electric connection pad 40b has configuration wide at the top and narrow at the bottom.
Additionally, in the present embodiment, as shown in Fig. 1 E ', also show this put brilliant pad 40a and electric connection pad 40b be comprising
Such as tetra- kinds of material persons of Au/Pd/Ni/Pd.
As shown in fig. 1f, put to be connect on brilliant pad 40a and put at least semiconductor chip 50 in this, and electrically connected with multiple bonding wires 60
The semiconductor chip 50 and electric connection pad 40b are met, wherein, the present embodiment is face-up with the start of the semiconductor chip 50
Mode is electrically connected with multiple bonding wires 60.Then, packing colloid 70 is formed on the carrier 20, to coat the semiconductor core
Piece 50, bonding wire 60, put brilliant pad 40a, electric connection pad 40b, put brilliant pad 40a and metal level 10 below and the electric connection
Pad 40b and metal level 10 below, wherein, the packing colloid 70 has relative first surface 70a and second surface 70b,
And second surface 70b is contacted with the carrier 20.
As shown in Figure 1 G, the carrier 20 is removed, brilliant pad 40a is put with this with the second surface 70b for appearing the packing colloid 70
With the metal level 10 below electric connection pad 40b.Then, a welding resisting layer is formed on the second surface 70b of the packing colloid 70
80, and the welding resisting layer 80 has and multiple expose outside this and put the anti-of part metal level 10 below brilliant pad 40a and electric connection pad 40b
Layer opening 801.
As shown in fig. 1h, formed if the conductive component 90 of soldered ball is in the welding resisting layer opening 801.Crystalline substance is put due to this ought be formed
Before pad 40a and electric connection pad 40b, the metal level 10 has been pre-formed on the carrier 20, so being formed before welding resisting layer 80
It is not required to form the protective layer such as electroless copper.
Fig. 1 H' and Fig. 1 H " are the other embodiments of Fig. 1 H.
As shown in Fig. 1 H', it is not make to put brilliant pad 40a with the difference of the preparation method of Fig. 1 H, so in the technique of Fig. 1 F
In, the semiconductor chip 50 optionally connects by sticky material 500 and is placed in the carrier 20.After carrier 20 are removed, outward
Reveal the bottom side of the semiconductor chip 50（Or sticky material 500）, make the welding resisting layer 80 be also formed into the bottom of the semiconductor chip 50
Side（Or sticky material 500）On.
Such as Fig. 1 H " shown in, it is to put crystal type with the difference of the preparation method of Fig. 1 H, so in the technique of Fig. 1 F, should be partly
Conductor chip 50 is incorporated on electric connection pad 40b by the flip of conductive projection 62.After carrier 20 are removed, the gold is exposed
Category layer 10.
According to aforesaid preparation method, the present invention provides a kind of square planar guide-pin-free semiconductor packaging part 1,1 ', 1 ", including：
Packing colloid 70 with relative first surface 70a and second surface 70b；One metal level 10, it is by multiple pulvilliform or piece shape
Metal segments are constituted, and respectively the pulvilliform or piece shape metal segments are configuration wide at the top and narrow at the bottom, and are embedded at the packing colloid 70
Second surface 70b on；Multiple electric connection pad 40b, it is embedded in the packing colloid 70 and is incorporated into the upper of the metal level 10
In wide configuration；And it is embedded in the packing colloid 70 and is electrically connected with the semiconductor chip 50 of those electric connection pads 40b.
The square planar guide-pin-free semiconductor packaging part 1,1 ' of the present invention, 1 " may also include at least one and be embedded in the packing colloid
Brilliant pad 40a is put in 70, and is incorporated in the upper wide configuration of the metal level 10, to arrange the semiconductor chip 50.
The square planar guide-pin-free semiconductor packaging part 1,1 ' of the present invention, 1 " may also include and be formed at the packing colloid 70
A welding resisting layer 80 on second surface 70b, and the welding resisting layer 80 has and multiple expose outside this and put brilliant pad 40a and electric connection pad
Multiple welding resisting layer openings 801 of the part metal level 10 below 40b.
The square planar guide-pin-free semiconductor packaging part 1,1 ', 1 of the present invention " may also include conductive component 90, and it is formed at
In the welding resisting layer opening 801.
The principle and its effect of above-described embodiment only illustrative present invention, it is of the invention not for limiting.Any
Art personnel can be modified above-described embodiment and are changed under the spirit and the scope without prejudice to the present invention.Therefore,
The scope of the present invention, should be as listed by claims.
Claims (18)
1. a kind of preparation method of square planar guide-pin-free semiconductor packaging part, it includes：
It is provided on a surface carrier with metal level；
Form multiple electric connections to be padded on the metal level on the carrier；
The metal level not covered by the electric connection pad is removed, the partly carrier is exposed in addition, and make electric connection pad lower section
Metal level there is the configuration that wide at the top and narrow at the bottom and side is an arc；
Connect and put semiconductor chip on the carrier, and make the semiconductor chip be electrically connected with those electric connection pads；
Packing colloid is formed on the carrier, to coat the semiconductor chip, the electric connection pad and metal level below, and
The packing colloid has relative first surface and second surface, and the second surface of the packing colloid is contacted with the carrier；With
And
The carrier is removed, with the metal level below the second surface and the electric connection pad that appear the packing colloid.
2. the preparation method of square planar guide-pin-free semiconductor packaging part according to claim 1, it is characterised in that form the electricity
The technique of property connection gasket includes：
Formation has the resistance layer of multiple resistance layer openings on the metal level, in addition the exposed portion metal level；
Plating forms the electric connection and is padded in the resistance layer opening；And
Remove the resistance layer.
3. the preparation method of square planar guide-pin-free semiconductor packaging part according to claim 1, it is characterised in that the carrier is
Ferroalloy carrier.
4. the preparation method of square planar guide-pin-free semiconductor packaging part according to claim 1, it is characterised in that the metal level
It is surface treated and obtains, and the mode of the surface treatment is physical vapour deposition (PVD), plating or electroless plating.
5. the preparation method of square planar guide-pin-free semiconductor packaging part according to claim 4, it is characterised in that the physics gas
Phase depositional mode is sputter.
6. the preparation method of square planar guide-pin-free semiconductor packaging part according to claim 1, it is characterised in that form the gold
The material of category layer is copper.
7. the preparation method of square planar guide-pin-free semiconductor packaging part according to claim 1, it is characterised in that with the side of etching
Formula removes the metal level not covered by the electric connection pad, wide at the top and narrow at the bottom to make the metal level below the electric connection pad have
Configuration.
8. the preparation method of square planar guide-pin-free semiconductor packaging part according to claim 1, it is characterised in that form the electricity
Property connection gasket material be Au/Pd/Ni/Pd, Au/Ni/Cu/Ni/Ag, Au/Ni/Cu/Ag, Pd/Ni/Pd, Au/Ni/Au or Pd/
Ni/Au。
9. the preparation method of square planar guide-pin-free semiconductor packaging part according to claim 1, it is characterised in that the metal level
On also have and at least one put brilliant pad, to arrange the semiconductor chip.
10. the preparation method of square planar guide-pin-free semiconductor packaging part according to claim 1, it is characterised in that the preparation method
Also include forming welding resisting layer on the second surface of the packing colloid and form conductive component in the welding resisting layer opening, and should
Welding resisting layer has multiple welding resisting layer openings for exposing outside the metal level.
The preparation method of 11. square planar guide-pin-free semiconductor packaging parts according to claim 1, it is characterised in that this is partly led
Body chip is electrically connected with those electric connection pads with conductive projection or bonding wire.
A kind of 12. square planar guide-pin-free semiconductor packaging parts, it includes：
Packing colloid, it has relative first surface and second surface；
Metal level, it is wide at the top and narrow at the bottom and side is the configuration of an arc, and is embedded on the second surface of the packing colloid, and
Expose outside configuration narrow under the metal level；
Multiple electric connection pads, it is embedded in the packing colloid and is incorporated in the upper wide configuration of the metal level；And
Semiconductor chip, it is embedded in the packing colloid and is electrically connected with those electric connection pads.
13. square planar guide-pin-free semiconductor packaging parts according to claim 12, it is characterised in that form this and electrically connect
The material of connection pad is Au/Pd/Ni/Pd, Au/Ni/Cu/Ni/Ag, Au/Ni/Cu/Ag, Pd/Ni/Pd, Au/Ni/Au or Pd/Ni/
Au。
14. square planar guide-pin-free semiconductor packaging parts according to claim 12, it is characterised in that the metal level is gold
Category coating.
15. square planar guide-pin-free semiconductor packaging parts according to claim 12, it is characterised in that the material of the metal level
Matter is copper.
16. square planar guide-pin-free semiconductor packaging parts according to claim 12, it is characterised in that the semiconductor packages
Part also puts brilliant pad including at least one, and it is embedded in the packing colloid, to arrange the semiconductor chip.
17. square planar guide-pin-free semiconductor packaging parts according to claim 12, it is characterised in that the quasiconductor subpackage
Part also includes the welding resisting layer being formed on the second surface of the packing colloid and conductive group be formed in the welding resisting layer opening
Part, and the welding resisting layer has multiple welding resisting layer openings for exposing outside the metal level.
18. square planar guide-pin-free semiconductor packaging parts according to claim 12, it is characterised in that the semiconductor chip
Those electric connection pads are electrically connected with conductive projection or bonding wire.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101132952A TWI463579B (en) | 2012-09-10 | 2012-09-10 | Quad flat no lead (qfn) semiconductor package and method of forming same |
| TW101132952 | 2012-09-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103681375A CN103681375A (en) | 2014-03-26 |
| CN103681375B true CN103681375B (en) | 2017-04-26 |
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ID=50318549
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210356342.8A Active CN103681375B (en) | 2012-09-10 | 2012-09-21 | Square plane pin-free semiconductor packaging part and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103681375B (en) |
| TW (1) | TWI463579B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104851866A (en) * | 2015-04-24 | 2015-08-19 | 郭秋卫 | Package utilizing metal hardness difference for optimizing pin arrangement, and manufacturing method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8227921B1 (en) * | 2007-10-03 | 2012-07-24 | Amkor Technology, Inc. | Semiconductor package with increased I/O density and method of making same |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7247526B1 (en) * | 1998-06-10 | 2007-07-24 | Asat Ltd. | Process for fabricating an integrated circuit package |
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| US8227921B1 (en) * | 2007-10-03 | 2012-07-24 | Amkor Technology, Inc. | Semiconductor package with increased I/O density and method of making same |
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| TW201411744A (en) | 2014-03-16 |
| CN103681375A (en) | 2014-03-26 |
| TWI463579B (en) | 2014-12-01 |
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