CN103681339A - Fin field effect transistor preparation method - Google Patents

Fin field effect transistor preparation method Download PDF

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Publication number
CN103681339A
CN103681339A CN201210352666.4A CN201210352666A CN103681339A CN 103681339 A CN103681339 A CN 103681339A CN 201210352666 A CN201210352666 A CN 201210352666A CN 103681339 A CN103681339 A CN 103681339A
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fin
substrate
semiconductor substrate
insulating barrier
etching
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CN201210352666.4A
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CN103681339B (en
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鲍宇
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention relates to a fin field effect transistor preparation method. The preparation method comprises the following steps: a base is provided, wherein the base comprises a semiconductor substrate and an insulating layer located on the semiconductor substrate, the base has a stepped shape and has a high region and a low region; a hard mask layer is formed on the insulating layer and planarization is performed; the hard mask layer and the insulating layer are etched, and at least one groove is formed in the high region and the low region of the base separately so as to expose the semiconductor substrate; the groove is filled with a semiconductor material and planarization is performed to form a fin pattern; and the hard mask layer is removed through etching to form fins having different heights. According to the invention, the heights of the fins, the height difference of the fins having different heights and the fin depth-width ratio can be controller easier, the problem that the fin height is not easy to control in the prior art can be solved skillfully, and the yield of semiconductor devices can be improved.

Description

A kind of preparation method of FinFET
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of preparation method of FinFET.
Background technology
To be mainly size by constantly dwindling integrated circuit (IC)-components realize with the speed that improves it in the raising of performance of integrated circuits.At present, because semi-conductor industry in pursuing high device density, high-performance and low cost has advanced to nanometer technology process node, from manufacturing and the challenge of design aspect has caused three dimensional design as the development of FinFET (FinFET).Thin vertical " fin " (or fin structure) that use is extended from the substrate by a part of silicon layer forms as etched away manufactured typical FinFET.The raceway groove of FinFET is formed in described vertical fin, above described fin, forms all around gate, and from both sides, control raceway groove by grid.In addition, in recess source/drain electrode (S/D) part of FinFET, utilize selective growth strain gauge material to can be used for improving carrier mobility.
With respect to existing planar transistor, described FinFET device has more superior performance aspect electrostatic control, is therefore widely used.In the equipment of conventional FinFET device, described in FinFET transistor, fin all has identical height.In order further to improve FinFET device performance, can prepare the fin with differing heights, in prior art, in order to obtain the field-effect transistor of highly different fins, adopt following method: first provide Semiconductor substrate, in described Semiconductor substrate, form hard mask layer, on described hard mask layer, form channel patterns mask layer, take described channel patterns mask layer as hard mask layer described in mask etch and substrate, in described substrate, form groove, then deposition of dielectric materials is to fill described groove, and carry out planarization, then on described substrate, form mask layer, Semiconductor substrate described in cover part, then the hard mask layer that the described mask layer of take exposes as mask etch removal, the dielectric material in part groove is removed in etching simultaneously, exposed portions serve is positioned at the Semiconductor substrate that is column of groove both sides, form fin, then remove described mask layer, when removing hard mask layer, the dielectric material in part groove is removed in etching, owing to not depositing dielectric material in the groove in hard mask layer region through twice etching, remove more, therefore form darker groove, so what be positioned at groove both sides is forming fin by Semiconductor substrate and having different height of cylindricality, the difference in height of the fin of described differing heights equals the thickness difference that dielectric material in groove is removed in etching, obtain pattern as shown in Figure 1, wherein said 210 is the first fin, described 212 is the second fin, in groove between described fin, it is dielectric material, described device also comprises grid 216 and gate dielectric layer 214, although described method can form differing heights fin, but formation method is to realize by the dielectric material in groove described in etching, along with further dwindling of device, it is wayward that the interior dielectric material of groove is removed in etching, thereby the difference in height of fin is also not easy to control, device performance and product yield are declined.
Fin height described in current described FinFET preparation process is difficult to control, and existing preparation method can't well address this problem, and has affected the performance of described FinFET.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The preparation method who the invention provides a kind of FinFET, comprising:
Substrate is provided, and described substrate comprises Semiconductor substrate and is positioned at the insulating barrier in described Semiconductor substrate, and this substrate is stairstepping, has He Di district, high district;
On described insulating barrier, form hard mask layer planarization;
Hard mask layer and described insulating barrier described in etching, form respectively at least one groove in He Di district, described substrate Gao district, to expose described Semiconductor substrate;
Adopt semi-conducting material to fill described groove planarization, to form fin pattern;
Described hard mask layer is removed in etching, with the different fin of height of formation.
As preferably, the formation method of described substrate is: Semiconductor substrate is provided, and the described Semiconductor substrate of part is removed in etching, to form the Semiconductor substrate of stairstepping, then on described substrate, forms insulating barrier, thereby obtains the substrate of stairstepping.
As preferably, the difference in height of the fin that described height is different equals the thickness of the described Semiconductor substrate that etching removes.
As preferably, the formation method of described substrate is: Semiconductor substrate is provided, and depositing insulating layer on described substrate, the described insulating barrier of part is removed in etching, to form the insulating barrier of stairstepping, thereby obtains the substrate of stairstepping.
As preferably, the difference in height of the fin that described height is different equals the thickness of the described insulating barrier that etching removes.
As preferably, described insulating barrier is oxide.
As preferably, described hard mask layer is one or more in SiN, A-C, BN and SiON.
As preferably, semi-conducting material is filled described groove described in epitaxial growth, to form fin pattern.
As preferably, the described semi-conducting material of filling is Si, Si-C or Si-Ge.
As preferably, the fin of described differing heights is used for forming many channel FinFETs
As preferably, the fin of described differing heights is used for respectively forming a plurality of different FinFETs.
As preferably, described method is also included in the step that forms all around gate on the described fin exposing.
As preferably, described method is also included in the step that leak in formation source, described all around gate both sides.
In the present invention, pass through to remove part semiconductor substrate or insulating barrier in etching, to form the stairstepping substrate with He Di district, high district, then the different fin of height of formation in described substrate, wherein, the difference in height of the fin that described height is different is the thickness of described Semiconductor substrate or the thickness of the described insulating barrier that etching is removed of described removal, the thickness of described removal substrate or insulating barrier is more prone to control, thereby, the height of described fin, the difference in height of highly different fins and fin depth-width ratio are also more prone to control, in the prior art solving cleverly, there is the uppity problem of fin height, improved the yield of semiconductor device.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1 is the structural representation of the FINFET for preparing in prior art;
Fig. 2-13 are for preparing the process schematic diagram of FINFET in the present invention;
Figure 14 prepares the process flow diagram of FINFET in the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, by propose detailed description in following description, so that the preparation method of FinFET FinFET of the present invention to be described.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these are described in detail, the present invention can also have other execution modes.
Should give attention, the term that used is here only in order to describe specific embodiment, but not intention restriction is according to exemplary embodiment of the present invention.As used herein, unless context explicitly points out in addition, otherwise singulative is also intended to comprise plural form.In addition, it is to be further understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination.
Now, describe in more detail according to exemplary embodiment of the present invention with reference to the accompanying drawings.Yet these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.To should be understood that, to provide these embodiment of the present inventionly to disclose thoroughly and complete in order making, and the design of these exemplary embodiments is fully conveyed to those of ordinary skills.In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and region, and used the identical Reference numeral to represent identical element, thereby will omit description of them.
Below in conjunction with the preparation process of Fig. 2-13 pair fin transistor FINFET of the present invention and the preparation flow figure of Figure 14, the inventive method is described further,
Figure 14 prepares the process flow diagram of FinFET in the present invention, described technique comprises the following steps:
Step 101 provides substrate, and described substrate comprises Semiconductor substrate and be positioned at the insulating barrier in described Semiconductor substrate, and this substrate is stairstepping, has He Di district, high district;
Step 102 forms hard mask layer planarization on described insulating barrier;
Hard mask layer and described insulating barrier described in step 103 etching, form respectively at least one groove in He Di district, described substrate Gao district, to expose described Semiconductor substrate;
Step 104 adopts semi-conducting material to fill described groove planarization, to form fin pattern;
Described hard mask layer is removed in step 105 etching, with the different fin of height of formation.
According to this flow chart, in the present invention, can there are following two kinds of execution modes, below these two kinds of execution modes are described respectively, first with reference to Fig. 2-7 pair the first situation, describe:
With reference to Fig. 2, first Semiconductor substrate 201 is provided, described Semiconductor substrate can be at least one in following mentioned material: silicon, Ge or SiGe etc.
In described Semiconductor substrate, can also form isolation structure, described isolation structure is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.Be preferably formed in the present invention shallow trench isolation from, in described Semiconductor substrate, be also formed with the channel layer of various traps (well) structure and substrate surface.In general, the ion doping conduction type that forms trap (well) structure is identical with channel layer ion doping conduction type, but concentration is low compared with gate channel layer, and the degree of depth of Implantation is general encloses extensivelyr, needs to reach the degree of depth that is greater than isolation structure simultaneously.In described substrate, can also further comprise other active devices, all omit in the figure.
As preferably, described Semiconductor substrate thickness is more than 500um, preferred 700-800um, then on described substrate, form insulating barrier 202, particularly, described insulating barrier is oxide in the present invention, be preferably the oxides such as SiO2, TEOS, the formation method of described insulating barrier can be selected a kind of in low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the selective epitaxy growth (SEG) that chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method etc. form.Preferred chemical vapor deposition (CVD) method in the present invention, in an embodiment of the present invention, the thickness of described insulating barrier is 50-300 dust.
With reference to Fig. 3, one end of insulating barrier described in etching, removes partial insulative layer, to form stairstepping, described insulating barrier is divided into I district (low district) HeII district (high district) as shown in FIG., in conjunction with described Semiconductor substrate, forms the substrate of stairstepping.
Particularly, on described insulating barrier, form photoresist mask, insulating barrier described in cover part, take described photoresist as insulating barrier described in mask layer etching, the not strict restriction of the thickness of the insulating barrier that wherein said etching is removed, can be according to target devices need to carry out etching, the thickness of the insulating barrier of described removal is the difference in height of differing heights fin, and the thickness of the insulating barrier of removing in this process is more prone to control, therefore the difference in height of described fin is also more prone to control with respect to prior art.
With reference to Fig. 4, on described insulating barrier, deposit hard mask layer 203, preferably one or more combinations in SiN, A-C, BN and SiON, for example can to comprise the SiN of 50-100 dust and be positioned at the upper thickness of SiN be the BN of 500-1500 dust to described hard mask layer, particularly, the deposition process of described hard mask layer can be selected a kind of in low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the selective epitaxy growth (SEG) that chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method etc. form.Preferred chemical vapor deposition (CVD) method in the present invention, deposition is carried out a planarisation step after forming described hard mask layer, make described hard mask layer obtain even curface, in an embodiment of the present invention, the thickness of described hard mask layer is 500-2000 dust.
With reference to Fig. 5, insulating barrier and hard mask layer described in etching are until expose described substrate, respectively to form at least one groove in described insulating barrier I district (low district) HeII district (high district), particularly, the method for described etching can be a kind of in reactive ion etching (RIE), ion beam milling, plasma etching in the present invention.In one embodiment of this invention, preferred reaction ion(ic) etching (RIE), is etched to described Semiconductor substrate, forms a plurality of grooves that are positioned at zones of different.The step that can also comprise the photoresist mask layer that forms patterning in a specific embodiment of the present invention, this pattern definition the CD of described groove opening, after etching completes, can further include the step of removing this photoresist.
With reference to Fig. 6, fill described groove, to form semiconductor fin 204 and 204 ˊ, particularly, epitaxial growth of semiconductor material in described groove in the present invention, to fill described groove, then carrying out planarization makes itself and described hard mask layer in sustained height, to form a plurality of fin pattern, wherein, described semi-conducting material is preferably Si, Si-C or Si-Ge, described semi-conducting material can be selected reduced pressure epitaxy, low-temperature epitaxy, selective epitaxy, liquid phase epitaxy, heteroepitaxy and molecular beam epitaxy, preferred selective epitaxy in the present invention, only in described groove, grow carrying out semi-conducting material described in epitaxial process, and can on described mask layer, not grow, make this process simpler, avoided the outer material layer of removing mask layer of delaying.
With reference to Fig. 7, described hard mask layer is removed in etching, to expose described fin, particularly, select in the present invention hard mask described in dry etching or wet etching, etching is removed after described hard mask, obtains highly different fin, as preferably, select in the present invention and method that described insulating barrier has a high etch selection ratio is removed described hard mask layer.
After forming described fin, be also further included in the step that forms all around gate on described fin, as preferably, after forming grid, can further include the step that leak in formation source.Wherein said grid and source are leaked to form and all can be selected this area common method.
In addition, the present invention also provides another execution mode, as shown in Fig. 8-13:
With reference to Fig. 8, first Semiconductor substrate 201 is provided, described substrate can with the first execution mode in identical, those skilled in the art can also select material conventional in prior art, do not repeat them here, then one end of Semiconductor substrate described in etching, removes part semiconductor substrate, to form stairstepping Semiconductor substrate, described Semiconductor substrate is divided into I district (low district) HeII district (high district) as shown in FIG.; Particularly, in described Semiconductor substrate, form photoresist mask, Semiconductor substrate described in cover part, take described photoresist as Semiconductor substrate described in mask layer etching, the not strict restriction of the thickness of the Semiconductor substrate that wherein said etching is removed, can be according to target devices need to carry out etching, the thickness of the Semiconductor substrate of described removal is the difference in height of differing heights fin, and the thickness of the Semiconductor substrate of removing in this process is more prone to control, therefore the difference in height of described fin is also more prone to control with respect to prior art.
With reference to Fig. 9, depositing insulating layer in described Semiconductor substrate, described insulating barrier is oxide in the present invention, is preferably SiO 2, the oxide such as TEOS, the formation method of described insulating barrier can be selected a kind of in low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the selective epitaxy growth (SEG) that chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method etc. form.Preferred chemical vapor deposition (CVD) method in the present invention, in an embodiment of the present invention, the thickness of described insulating barrier is 50-300 dust.Deposit after described insulating barrier in conjunction with described Semiconductor substrate, form the substrate of stairstepping.
With reference to Figure 10-13, described operating process is corresponding with Fig. 4-7 in the first execution mode, described operating procedure and process conditions all can be with reference to operations accordingly in Fig. 4-7, at this, be no longer repeated in this description, but it should be noted that described operation and condition are only exemplary, but be not limited to described execution mode.
In the present invention, pass through to remove part semiconductor substrate or insulating barrier in etching, to form the stairstepping substrate with He Di district, high district, then the different fin of height of formation in described substrate, wherein, the difference in height of the fin that described height is different is the thickness of described Semiconductor substrate or the thickness of the described insulating barrier that etching is removed of described removal, the thickness of described removal substrate or insulating barrier is more prone to control, thereby, the height of described fin, the difference in height of highly different fins and fin depth-width ratio are also more prone to control, in the prior art solving cleverly, there is the uppity problem of fin height, improved the yield of semiconductor device.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.

Claims (13)

1. a preparation method for FinFET, comprising:
Substrate is provided, and described substrate comprises Semiconductor substrate and is positioned at the insulating barrier in described Semiconductor substrate, and this substrate is stairstepping, has He Di district, high district;
On described insulating barrier, form hard mask layer planarization;
Hard mask layer and described insulating barrier described in etching, form respectively at least one groove in He Di district, described substrate Gao district, to expose described Semiconductor substrate;
Adopt semi-conducting material to fill described groove planarization, to form fin pattern;
Described hard mask layer is removed in etching, with the different fin of height of formation.
2. method according to claim 1, is characterized in that, the formation method of described substrate is: Semiconductor substrate is provided, the described Semiconductor substrate of part is removed in etching, to form the Semiconductor substrate of stairstepping, then on described substrate, form insulating barrier, thereby obtain the substrate of stairstepping.
3. method according to claim 2, is characterized in that, the difference in height of the fin that described height is different equals the thickness of the described Semiconductor substrate of etching removal.
4. method according to claim 1, is characterized in that, the formation method of described substrate is: Semiconductor substrate is provided, depositing insulating layer on described substrate, the described insulating barrier of part is removed in etching, to form the insulating barrier of stairstepping, thereby obtains the substrate of stairstepping.
5. method according to claim 4, is characterized in that, the difference in height of the fin that described height is different equals the thickness of the described insulating barrier of etching removal.
6. method according to claim 1, is characterized in that, described insulating barrier is oxide.
7. method according to claim 1, is characterized in that, described hard mask layer is one or more in SiN, A-C, BN and SiON.
8. method according to claim 1, is characterized in that, semi-conducting material is filled described groove described in epitaxial growth, to form fin pattern.
9. method according to claim 1, is characterized in that, the described semi-conducting material of filling is Si, Si-C or Si-Ge.
10. method according to claim 1, is characterized in that, the fin of described differing heights is used for forming many channel FinFETs.
11. methods according to claim 1, is characterized in that, the fin of described differing heights is used for respectively forming a plurality of different FinFETs.
12. methods according to claim 1, is characterized in that, described method is also included in the step that forms all around gate on the described fin exposing.
13. methods according to claim 12, is characterized in that, described method is also included in the step that leak in formation source, described all around gate both sides.
CN201210352666.4A 2012-09-20 2012-09-20 A kind of preparation method of FinFET Active CN103681339B (en)

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CN105448728A (en) * 2014-08-29 2016-03-30 中芯国际集成电路制造(上海)有限公司 Method of forming fin field-effect transistor
CN107785419A (en) * 2016-08-25 2018-03-09 中芯国际集成电路制造(上海)有限公司 A kind of fin formula field effect transistor and its manufacture method
CN108054100A (en) * 2017-12-12 2018-05-18 深圳迈辽技术转移中心有限公司 The production method of fin formula field effect transistor

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US20100163971A1 (en) * 2008-12-31 2010-07-01 Shih-Ting Hung Dielectric Punch-Through Stoppers for Forming FinFETs Having Dual Fin Heights
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Publication number Priority date Publication date Assignee Title
CN105448728A (en) * 2014-08-29 2016-03-30 中芯国际集成电路制造(上海)有限公司 Method of forming fin field-effect transistor
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CN108054100A (en) * 2017-12-12 2018-05-18 深圳迈辽技术转移中心有限公司 The production method of fin formula field effect transistor

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