CN103456632A - Mos transistor and forming method thereof - Google Patents
Mos transistor and forming method thereof Download PDFInfo
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- CN103456632A CN103456632A CN2012101745900A CN201210174590A CN103456632A CN 103456632 A CN103456632 A CN 103456632A CN 2012101745900 A CN2012101745900 A CN 2012101745900A CN 201210174590 A CN201210174590 A CN 201210174590A CN 103456632 A CN103456632 A CN 103456632A
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Abstract
Disclosed are a MOS transistor and a forming method thereof. The forming method of the MOS transistor includes: providing a semiconductor substrate, covering the surface of the semiconductor substrate with a voltage control layer, covering the surface of the voltage control layer with a first epitaxial intrinsic layer, covering the surface of the first epitaxial intrinsic layer with an insulating layer which is provided with a first gate structure passing the thickness-wise part of the insulating layer; using the first gate structure as a mask to dope in the first epitaxial intrinsic layer to form a source/drain area; removing the first gate structure to form an opening exposed out of the surface of the first epitaxial layer; forming a second epitaxial intrinsic layer covering the bottom of the opening; forming a second gate structure, covering the second epitaxial intrinsic layer, in the opening. The formed MOS transistor is low in threshold voltage and stable in performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of metal-oxide-semiconductor and forming method thereof.
Background technology
The formation method of the metal-oxide-semiconductor of prior art comprises:
Please refer to Fig. 1, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 surface coverage have insulation film 101, and described insulation film 101 surface coverage have polysilicon membrane 103, and described polysilicon membrane 103 surfaces have photoresist layer 105;
Please refer to Fig. 2, take described photoresist layer 105 as the described polysilicon membrane of mask etching and insulation film, until expose Semiconductor substrate 100, form polysilicon layer 103a and insulating barrier 101a, described polysilicon layer 103a is positioned at described insulating barrier 101a surface;
Please refer to Fig. 3, after insulating barrier 101a to be formed and polysilicon layer 103a, take described photoresist layer 105 as mask to the interior doping ion of described Semiconductor substrate 100, formation source/drain region 107.
Development along with semiconductor process techniques, reducing gradually of process node, gate features size (CD) constantly reduces, rear grid technique is widely used, and adopt high-K gate dielectric material to replace generic media as gate dielectric layer, adopt metal material to replace polysilicon as gate electrode layer, to improve the performance of MOS device.
Yet the threshold voltage of the metal-oxide-semiconductor that prior art forms is higher, the performance of metal-oxide-semiconductor still has much room for improvement.Specifically please refer to the United States Patent (USP) that publication number is " US20100084719A1 ".
Summary of the invention
The problem that the present invention solves is to provide a kind of superior performance, metal-oxide-semiconductor that threshold voltage is low and forming method thereof.
For addressing the above problem, embodiments of the invention form the formation method of metal-oxide-semiconductor, comprising:
Semiconductor substrate is provided, described semiconductor substrate surface is coated with voltage control layer, described voltage control layer surface coverage has the first extension intrinsic layer, described the first extension intrinsic layer surface coverage has insulating barrier, there is the first grid structure that runs through its thickness in described insulating barrier, wherein, in described the first extension intrinsic layer and voltage control layer, the ion of doping has concentration gradient, and the ion concentration of described the first extension intrinsic layer is less than the ion concentration of described voltage control layer;
The described first grid structure of take is mask, to doping formation source/drain region in described the first extension intrinsic layer;
Remove described first grid structure, form the opening that exposes described the first extension intrinsic layer surface;
Form the second extension intrinsic layer that covers described open bottom;
Form the second grid structure that covers described the second extension intrinsic layer in described opening.
Alternatively, have the doping ion in described voltage control layer, the concentration of described doping ion is greater than 5E17atoms/cm
3, be less than 5E18atoms/cm
3.
Alternatively, when forming the NMOS pipe, the doping ion in described voltage control layer is the p-type ion, and in described voltage control layer, also doped with carbon ion, and the volume ratio that the carbon ion of doping accounts for total doping ion of voltage control layer is less than 1%; When forming the PMOS pipe, the doping ion in described voltage control layer is the N-shaped ion, and in described voltage control layer, also doped with germanium ion, and the volume ratio that the germanium ion of doping accounts for total doping ion of voltage control layer is less than 3%.
Alternatively, the volume ratio that the carbon ion of described doping accounts for total doping ion of voltage control layer is less than 0.1%.
Alternatively, do not there is the doping ion in described the first extension intrinsic layer; Or the ion concentration of doping in described the first extension intrinsic layer is less than 1E16atoms/cm
3.
Alternatively, do not there is the doping ion in described the second extension intrinsic layer; Or the ion concentration of doping in described the second extension intrinsic layer is less than 1E16atoms/cm
3.
Alternatively, the thickness of described the second epitaxial loayer is 3nm-10nm.
Alternatively, the formation technique of described the second extension intrinsic layer is the selective epitaxial depositing operation.
Alternatively, also comprise: before forming the second extension intrinsic layer, annealing in process is carried out in the first extension intrinsic layer surface of described open bottom.
Alternatively, the gas that described annealing in process adopts is hydrogen or argon gas.
Alternatively, the formation step of described first grid structure comprises: form the pseudo-gate electrode layer that runs through described insulating barrier and be positioned at described the first extension intrinsic layer surface; Formation is positioned at the pseudo-side wall of described pseudo-gate electrode layer both sides.
Alternatively, also comprise: after forming pseudo-gate electrode layer, before forming pseudo-side wall, the described pseudo-gate electrode layer of take is mask, to light dope in described the first extension intrinsic layer, forms light doping section; After forming pseudo-side wall, before forming insulating barrier, take described pseudo-side wall and pseudo-gate electrode layer is mask, to heavy doping in described the first extension intrinsic layer, formation source/drain region.
Alternatively, the formation step of described second grid structure comprises: form the side wall that is positioned at described opening both sides; Form the high-K gate dielectric layer that covers described the second extension intrinsic layer and side wall; Form the metal gate electrode layer that covers described high-K gate dielectric layer and flush with described surface of insulating layer.
Alternatively, also comprise: before forming the first grid structure, form the etching barrier layer that covers described the first extension intrinsic layer surface.
Corresponding volume, also provide a kind of metal-oxide-semiconductor, comprising:
Semiconductor substrate;
Cover the voltage control layer of described semiconductor substrate surface;
Cover the first extension intrinsic layer on described voltage control layer surface, in described the first extension intrinsic layer and voltage control layer, the ion of doping has concentration gradient, and the ion concentration of described the first extension intrinsic layer is less than the ion concentration of described voltage control layer;
Cover the insulating barrier on described the first extension intrinsic layer surface;
The opening that runs through described thickness of insulating layer;
Be positioned at the second extension intrinsic layer of described open bottom, described the second extension intrinsic layer is positioned at described the first extension intrinsic layer surface, and do not there is the doping ion in described the second extension intrinsic layer, or the ion concentration of its doping is less than the ion concentration of doping in described the first extension intrinsic layer;
Be positioned at the grid structure on the described second extension intrinsic layer surface of described opening, described grid structure flushes with described surface of insulating layer.
Alternatively, in described the second extension intrinsic layer, do not there is the doping ion, or the ion concentration of doping in described the second extension intrinsic layer is less than 1E16atoms/cm
3.
Alternatively, the thickness of described the second extension intrinsic layer is 3nm-10nm.
Alternatively, in described voltage control layer, the concentration of doping ion is greater than 5E17atoms/cm
3, be less than 5E18atoms/cm
3.
Alternatively, when managing for NMOS, the doping ion in described voltage control layer is the p-type ion, and in described voltage control layer, also doped with carbon ion, and the volume ratio that the carbon ion of doping accounts for total doping ion of voltage control layer is less than 1%; When managing for PMOS, the doping ion in described voltage control layer is the N-shaped ion, and in described voltage control layer, also doped with germanium ion, and the volume ratio that the germanium ion of doping accounts for total doping ion of voltage control layer is less than 3%.
Alternatively, the volume ratio that the carbon ion of described doping accounts for total doping ion of voltage control layer is less than 0.1%.
Alternatively, described grid structure comprises the side wall that is positioned at described opening sidewalls; Cover the high-K gate dielectric layer of described the second extension intrinsic layer and sidewall; The metal gate electrode layer that covers described high-K gate dielectric layer and flush with described surface of insulating layer.
Alternatively, also comprise: the light doping section that is positioned at the first extension intrinsic layer of described metal gate electrode layer both sides; Be positioned at the source/drain region of the first extension intrinsic layer of described metal gate electrode layer and side wall both sides.
Alternatively, described semiconductor substrate surface place has the doping ion, and the concentration of described doping ion is greater than 1E18atoms/cm
3, be less than 1E19atoms/cm
3.
Alternatively, when managing for NMOS, the doping ion in described Semiconductor substrate is p-type, also comprises carbon ion in described Semiconductor substrate, and the volume ratio that described carbon ion accounts for total doping ion in Semiconductor substrate is less than 1%; When managing for PMOS, the doping ion in described Semiconductor substrate is N-shaped, also comprises germanium ion in described Semiconductor substrate, and the volume ratio that described germanium ion accounts for total doping ion in Semiconductor substrate is less than 1%.
Alternatively, in described Semiconductor substrate, the carbon ion of doping accounts for total volume ratio of adulterating ion in Semiconductor substrate and is less than 0.4%.
Compared with prior art, embodiments of the invention have the following advantages:
The technique that forms metal-oxide-semiconductor is simple, take the first grid structure as mask, in the first extension intrinsic layer behind formation source/drain region, remove described first grid structure and form the opening that exposes described the first extension intrinsic layer surface, and form the second extension intrinsic layer in described open bottom, then form the second grid structure that covers described the second extension intrinsic layer.The the second extension intrinsic layer formed is more near the second grid structure, existence due to the second extension intrinsic layer, even the ion concentration behind formation source/drain region in the first extension intrinsic layer increases, can not cause negative effect to the threshold voltage of the metal-oxide-semiconductor that forms yet, the threshold voltage of the metal-oxide-semiconductor that the embodiment of the present invention forms is low, the stable performance of the metal-oxide-semiconductor of formation.
Further, also comprise: form light doping section, described light doping section can effectively stop that heavily doped source/drain region intermediate ion, through high-K gate dielectric layer, impacts metal gate electrode layer, effectively suppress hot carrier's effect, the performance of the metal-oxide-semiconductor of formation is more stable.
Metal-oxide-semiconductor has the second extension intrinsic layer of close grid structure (second grid structure), does not possess doping ion or doping ion concentration in described the second extension intrinsic layer lower than 1E16atoms/cm
3, metal-oxide-semiconductor can obtain lower threshold voltage.
The accompanying drawing explanation
Fig. 1-Fig. 3 is the cross-sectional view of forming process of the metal-oxide-semiconductor of prior art;
Fig. 4 is the schematic flow sheet of embodiment of the formation method of metal-oxide-semiconductor of the present invention;
Fig. 5-Figure 15 is the cross-sectional view of embodiment of the forming process of metal-oxide-semiconductor of the present invention;
Figure 16 is the distribution schematic diagram of ion concentration in any point in the second extension intrinsic layer, the first extension intrinsic layer, voltage control layer and the Semiconductor substrate of the metal-oxide-semiconductor that forms of the embodiment of the present invention.
Embodiment
As described in background, the threshold voltage of the metal-oxide-semiconductor of prior art is higher, and the performance of metal-oxide-semiconductor still has much room for improvement.
Through research, the inventor finds, can form at semiconductor substrate surface the extension intrinsic layer of voltage control layer and the described voltage control layer of covering, the ion concentration of described voltage control layer is greater than the ion concentration of described extension intrinsic layer, and, when both have concentration gradient, the metal-oxide-semiconductor of formation can obtain lower threshold voltage.
After further research, the inventor finds, during due to the formation metal-oxide-semiconductor, formation source/the drain region of need to adulterating in described extension intrinsic layer, even the ion of annealing in process with activation of source/drain region carried out in described source/drain region, the ion in described source/drain region can further spread in described extension intrinsic layer, makes the extension intrinsic layer ion concentration that is positioned at described grid structure base plate increase.When the extension intrinsic layer ion concentration that is positioned at described grid structure base plate increases, the threshold voltage of the metal-oxide-semiconductor formed can be affected and increase to some extent, for the threshold voltage that reduces the metal-oxide-semiconductor formed and the stability that improves the metal-oxide-semiconductor performance, embodiments of the invention provide a kind of metal-oxide-semiconductor and forming method thereof.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Please refer to Fig. 4, the formation method of the metal-oxide-semiconductor of the embodiment of the present invention comprises:
Step S201, Semiconductor substrate is provided, described semiconductor substrate surface is coated with voltage control layer, described voltage control layer surface coverage has the first extension intrinsic layer, described the first extension intrinsic layer surface coverage has insulating barrier, has the first grid structure that runs through its thickness in described insulating barrier, wherein, in described the first extension intrinsic layer and voltage control layer, the ion of doping has concentration gradient, and the ion concentration of described the first extension intrinsic layer is less than the ion concentration of described voltage control layer;
Step S203, the described first grid structure of take is mask, to doping formation source/drain region in described the first extension intrinsic layer;
Step S205, remove described first grid structure, forms the opening that exposes described the first extension intrinsic layer surface;
Step S207, form the second extension intrinsic layer that covers described open bottom;
Step S209 forms the second grid structure that covers described the second extension intrinsic layer in described opening.
Concrete, please refer to Fig. 5-Figure 16, Fig. 5-Figure 15 shows the cross-sectional view of forming process of the metal-oxide-semiconductor of the embodiment of the present invention, and Figure 16 shows in the second extension intrinsic layer, the first extension intrinsic layer, voltage control layer and the Semiconductor substrate of the metal-oxide-semiconductor that the embodiment of the present invention forms the distribution schematic diagram of ion concentration in any point.
Please refer to Fig. 5, Semiconductor substrate 300 is provided.
Described Semiconductor substrate 300 is used to subsequent technique that workbench is provided.Described Semiconductor substrate 300 is silicon substrate (Si) or silicon-on-insulator (SOI).In an embodiment of the present invention, described Semiconductor substrate 300 is silicon substrate, and its material is monocrystalline silicon, and its indices of crystallographic plane are (100).
It should be noted that, the interior anti-break-through layer (not shown) that can also there is well region (not shown), sub-channel (sub-channel) (not shown) or prevent break-through (punch-through) in metal-oxide-semiconductor of described Semiconductor substrate 300, for making the ion distribution in described well region even, can also carry out annealing process to described Semiconductor substrate 300, because annealing process is well known to those skilled in the art, do not repeat them here.
In an embodiment of the present invention, also comprise: adopt spike doping (spike channel) technique, adulterated in described Semiconductor substrate 300, make to be greater than 1E18atoms/cm near the ion concentration of Semiconductor substrate 300 surfaces
3, be less than 1E19atoms/cm
3.Owing to forming the NMOS pipe in the embodiment of the present invention, doping ion in described Semiconductor substrate 300 is p-type, the carrier mobility of the NMOS channel region formed for follow-up raising, in described Semiconductor substrate 300 also doped with carbon ion, and the volume ratio that the carbon ion of its doping accounts for total doping ion in Semiconductor substrate is less than 1%, especially is less than 0.4%.
It should be noted that, in other embodiments of the invention, when forming the PMOS pipe, doping ion in described Semiconductor substrate is N-shaped, the carrier mobility of the PMOS channel region formed for follow-up raising, in described Semiconductor substrate 300, also doped with germanium ion, and the volume ratio that the germanium ion of its doping accounts for total doping ion in Semiconductor substrate is less than 1%.
Please refer to Fig. 6, form the voltage control layer 301 that covers described Semiconductor substrate 300 and the first extension intrinsic layer 303 that covers described voltage control layer 301, the ion of described the first extension intrinsic layer 303 and voltage control layer 301 interior doping has concentration gradient, and the ion concentration of described the first extension intrinsic layer 303 is less than the ion concentration of described voltage control layer 301.
There is the doping ion in described voltage control layer (epitaxial Vt control layer) 301, follow-up for controlling the threshold voltage of metal-oxide-semiconductor.Through research, the inventor finds, when the concentration of the interior doping ion of voltage control layer 301 is greater than 5E17atoms/cm
3, be less than 5E18atoms/cm
3the time, the threshold voltage of the metal-oxide-semiconductor of formation is minimum.In embodiments of the invention, while forming the NMOS pipe, the doping ion in described voltage control layer 301 is the p-type ion.
For increasing the stress of NMOS pipe channel region; improve the carrier mobility of NMOS pipe channel region; usually also can be in voltage control layer 301 the doping carbon ion; when the volume ratio that accounts for total doping ion of voltage control layer 301 when the carbon ion of doping is less than 1%, the carrier mobility of NMOS pipe channel region is higher.In an embodiment of the present invention, the volume ratio that the carbon ion of described voltage control layer 301 interior doping accounts for total doping ion of voltage control layer 301 is less than 0.1%, and the carrier mobility of the NMOS pipe channel region of formation is high, and the threshold voltage of NMOS pipe is low.
It should be noted that, in other embodiments of the invention, when forming the PMOS pipe, doping ion in described voltage control layer 301 is the N-shaped ion, and the ratio of the germanium ion adulterated for the channel region stress that improves the PMOS pipe and carrier mobility also has requirement, when the volume ratio that accounts for total doping ion of voltage control layer 301 when the germanium ion of doping is less than 3%, the channel region stress of PMOS pipe and carrier mobility is high and the threshold voltage of PMOS pipe is low.
The material of described voltage control layer 301 is monocrystalline silicon or other semi-conducting materials, and the formation method of described voltage control layer 301 is epitaxial growth technology or ion doping technique.In an embodiment of the present invention, the formation technique of described voltage control layer 301 is: epitaxial growth technology, its concrete steps comprise: adopt the silicon source gas that comprises p-type ion and carbon ion, in the surperficial extension of described Semiconductor substrate 300, form voltage control layer 301.
It should be noted that, in other embodiments of the invention, also can directly to the interior doped p type of described Semiconductor substrate 300 or N-shaped ion, form voltage control layer 301.
Described the first extension intrinsic layer 303 is for together adjusting the threshold voltage of metal-oxide-semiconductor with voltage control layer 301 and barrier layer.Through research, find, when the ion concentration of described the first extension intrinsic layer 303 interior doping is less than 1E16atoms/cm
3the time, metal-oxide-semiconductor more easily obtains lower threshold voltage, and while especially in described the first extension intrinsic layer 303, not having the doping ion, the final metal-oxide-semiconductor formed can obtain minimum threshold voltage.In an embodiment of the present invention, owing to forming the NMOS pipe, the ion of described the first extension intrinsic layer 303 interior doping is p-type.
It should be noted that, in other embodiments of the invention, when forming the PMOS pipe, the ion of described the first extension intrinsic layer 303 interior doping is N-shaped.
Please refer to Fig. 7, form the etching barrier layer 305 that covers described the first extension intrinsic layer 303, form the pseudo-gate electrode layer 307 that is positioned at described etching barrier layer 305 surfaces.
For the pseudo-side wall of follow-up removal, time protection extension intrinsic layer 303 is not damaged described etching barrier layer 305.The formation technique of described etching barrier layer 305 is depositing operation, for example physics or chemical vapor deposition method.The material of described etching barrier layer 305 is for to compare with pseudo-side wall, the material that etching selection ratio is little, such as silica, silicon nitride, silicon oxynitride etc.In an embodiment of the present invention, the material of described etching barrier layer 305 is silicon oxynitride.
Described pseudo-gate electrode layer 307 as mask, forms light doping section and source/drain region for follow-up.The material of described pseudo-gate electrode layer 307 is polysilicon, and rear extended meeting is removed.The formation step of described pseudo-gate electrode layer 307 comprises: form the pseudo-gate electrode film (not shown) that covers described etching barrier layer 305 surfaces; Form the photoresist layer (not shown) that covers described pseudo-gate electrode film surface; Take described photoresist layer as mask, and the described pseudo-gate electrode film of etching forms pseudo-gate electrode layer 307.Because the formation technique of described pseudo-gate electrode layer 307 is well known to those skilled in the art, do not repeat them here.
Please refer to Fig. 8, the described pseudo-gate electrode layer 307 of take is mask, to the interior light dope of described the first extension intrinsic layer 303, forms light doping section 308.
Described light doping section 308 is follow-up for stopping that heavily doped source/drain region intermediate ion, through high-K gate dielectric layer, impacts metal gate electrode layer, produces hot carrier's effect.The formation technique of described light doping section 308 is ion doping technique, during doping, when Implantation the first epitaxial semiconductor layer 303 and described the first epitaxial semiconductor layer 303 surfaces be 30-60 ° of angle (implant angle), the light doping section 308 of formation is comparatively desirable.Because the technique that forms light doping section 308 is well known to those skilled in the art, do not repeat them here.
Please refer to Fig. 9, after forming light doping section 308, form the pseudo-side wall 309 that is positioned at described pseudo-gate electrode layer 307 both sides.
Described pseudo-side wall 309 for described pseudo-gate electrode layer 307 jointly as the mask in follow-up formation source/drain region.The material of described pseudo-side wall 309 is silicon nitride.The formation technique of described pseudo-side wall 309 is depositing operation, and it specifically forms step and comprises: the pseudo-side wall film that forms the roof, sidewall and the etching barrier layer 305 that cover described pseudo-gate electrode layer 307; The described pseudo-side wall film of etching, expose top and etching barrier layer 305 surfaces of pseudo-gate electrode layer 307, forms pseudo-side wall 309.Because the technique that forms pseudo-side wall 309 is well known to those skilled in the art, do not repeat them here.
Please refer to Figure 10, take described pseudo-gate electrode layer 307 and pseudo-side wall 309 is mask, to the interior heavy doping of described the first extension intrinsic layer 303, formation source/drain region 311.
The formation technique in described source/drain region 311 is doping process, due to the doping formation source/drain region 311 technique be well known to those skilled in the art, do not repeat them here.
It should be noted that, after forming source/drain region 311 to the interior doping of described the first extension intrinsic layer 303, also comprise: annealed in described source/drain region 311, activated the ion in described source/drain region 311, and impaired the first extension intrinsic layer 303 surfaces during repair in the formation source/drain region 311.
Please refer to Figure 11, behind formation source/drain region 311, form the insulating barrier 313 that covers described pseudo-gate electrode layer 307, pseudo-side wall 309 and etching barrier layer 305, described insulating barrier 313 surfaces flush with described pseudo-gate electrode layer 307 tops.
Described insulating barrier 313 is for the second grid structure of follow-up isolation adjacent mos pipe.Material oxidation silicon, silicon oxynitride or the silicon nitride etc. of described insulating barrier 313, and in order to facilitate the removal of pseudo-side wall 309, the material of described insulating barrier 313 is different from the material of described pseudo-side wall 309, and both have larger etching selection ratio.In an embodiment of the present invention, the material of described insulating barrier 313 is silica.
The formation technique of described insulating barrier 313 is depositing operation, for example physics or chemical vapor deposition method.The formation step of described insulating barrier 313 comprises: form the insulation film (not shown) that covers described pseudo-gate electrode layer 307, pseudo-side wall 309 and etching barrier layer 305; Chemico-mechanical polishing or time described insulation film of etching, form the insulating barrier 313 with described pseudo-gate electrode layer 307 and pseudo-side wall 309 flush.
Please refer to Figure 12, after forming insulating barrier 313, remove described pseudo-gate electrode layer and pseudo-side wall, form the opening 315 that exposes described the first extension intrinsic layer 303 surfaces.
Described opening 315 is for the follow-up window as forming the second extension intrinsic layer.The formation technique of described opening 315 is etching technics, for example dry etch process.Because the technique that adopts dry etch process to form opening 315 is well known to those skilled in the art, do not repeat them here.
It should be noted that, be subject to the protection of described etching barrier layer 305, can not destroy described the first extension intrinsic layer 303 surfaces during the described opening 315 of etching.
Please refer to Figure 13, form the second extension intrinsic layer 317 that covers described opening 315 bottoms.
The inventor finds, owing in the interior doping of described the first extension intrinsic layer 303, forming light doping section 308 and source/drain region 311, and also carried out annealing in process behind formation source/drain region 311, described light dope goes 308, the ions in source/drain region 311 further diffuse to part the first extension intrinsic layer 303 that is positioned at described opening 315 bottoms, causes the interior ion concentration of the first extension intrinsic layer 303 to increase.If the first extension intrinsic layer 303 surfaces that increase in described ion concentration form the second grid structure, the threshold voltage of the metal-oxide-semiconductor formed is higher, the unstable properties of metal-oxide-semiconductor.
After further research, the inventor finds, can be after forming light doping section 308, source/drain region 311, then form the second extension intrinsic layers 317 on described first extension intrinsic layer 303 surfaces of described opening 315 bottoms.Do not there is the doping ion in described the second extension intrinsic layer 317, or there is the doping ion, but the ion concentration of described the second extension intrinsic layer 317 interior doping is less than 1E16atoms/cm
3, the more close second grid structure of described the second extension intrinsic layer 317, be beneficial to the low metal-oxide-semiconductor of follow-up formation threshold voltage.
The formation technique of described the second extension intrinsic layer 317 is depositing operation, for example physics or chemical vapor deposition method.In an embodiment of the present invention, the formation technique of described the second extension intrinsic layer 317 is the selective epitaxial depositing operation, and the thickness of the described second extension intrinsic layer 317 of formation is 3nm-10nm, is beneficial to form the metal-oxide-semiconductor of high integration.
It should be noted that, while due to the employing etching technics, removing described pseudo-gate electrode layer and pseudo-side wall, the first extension intrinsic layer 303 surfaces of described opening 315 bottoms may exist uneven, therefore, for the stability of metal-oxide-semiconductor that embodiments of the invention are formed better, also comprise: before forming the second extension intrinsic layer 317, annealing in process is carried out in the first extension intrinsic layer 303 surfaces of described opening 315 bottoms, the gas that described annealing in process adopts is hydrogen or argon gas.
Please refer to Figure 14, form the side wall 319 that is positioned at described opening 315 both sides.
Described side wall 319 is not for being damaged at subsequent technique protection metal gate electrode layer and high-K gate dielectric layer.The formation technique of described side wall 319 is depositing operation, for example chemical vapor deposition method.The formation step of described side wall 319 comprises: form the side wall film (not shown) that covers described opening 315 bottoms, sidewall and insulating barrier 313 surfaces; Return the described side wall film of etching until expose the first extension intrinsic layer 303 surface and insulating barrier 313 surfaces of described opening 315 bottoms, form side wall 319.
The material of described side wall 319 is silica, silicon nitride or silicon oxynitride.In an embodiment of the present invention, the material of described side wall 319 is identical with the material of described pseudo-side wall, is silicon nitride.
Please refer to Figure 15, form the high-K gate dielectric layer 321 that covers described the second extension intrinsic layer 317 and side wall 319; Form to cover described high-K gate dielectric layer 321 and with the metal gate electrode layer 323 of described insulating barrier 313 flush.
Described side wall 319, high-K gate dielectric layer 321 and the common formation second grid of metal gate electrode layer 323 structure.The concrete formation step of described high-K gate dielectric layer 321 and metal gate electrode layer 323 comprises: form the high-K gate dielectric film (not shown) that covers described the second extension intrinsic layer 217, side wall 319 and insulating barrier 313 surfaces; Form the metal electrode film (not shown) that covers described high-K gate dielectric film; The described metal electrode film of chemico-mechanical polishing and high-K gate dielectric film, form high-K gate dielectric layer 323 and metal electrode layer 325 with described insulating barrier 313 flush.
After above-mentioned steps completes, the completing of the MOS device of the embodiment of the present invention.
Please in conjunction with reference Figure 15 and Figure 16, the ion concentration distribution schematic diagram that Figure 16 is the second extension intrinsic layer 317 in the metal-oxide-semiconductor shown in Figure 15, the first extension intrinsic layer 303, voltage control layer 301 and Semiconductor substrate 300 interior any points.Wherein, the second extension intrinsic layer 317, the first extension intrinsic layer 303, voltage control layer 301 and the interior any point of Semiconductor substrate 300 that X-axis is metal-oxide-semiconductor is to the distance on extension intrinsic layer 303 surfaces, the ion concentration of the second extension intrinsic layer 317, the first extension intrinsic layer 303, voltage control layer 301 and Semiconductor substrate 300 interior any points that Y-axis is described metal-oxide-semiconductor.
The concentration of described the first extension intrinsic layer 303 interior ions is as shown in first area I in Figure 16; The concentration of described voltage control layer 301 interior ions, as shown in second area II in Figure 16, is greater than 5E17atoms/cm
3, be less than 5E18atoms/cm
3; The concentration of described Semiconductor substrate 300 interior ions is as shown in the 3rd regional III in Figure 16, and the highest near the concentration of Semiconductor substrate 300 surfaces, the concentration of described the second extension intrinsic layer 317 interior ions, as shown in the 4th regional IV in Figure 16, is less than 1E16atoms/cm
3.The ion concentration of the voltage control layer 319 of the metal-oxide-semiconductor formed is greater than the ion concentration of described extension intrinsic layer 321, is conducive to obtain lower threshold voltage.
Accordingly, please continue to refer to Figure 15, embodiments of the invention also provide a kind of metal-oxide-semiconductor that adopts said method to form, and comprising:
Cover the voltage control layer 301 on described Semiconductor substrate 300 surfaces;
Cover the first extension intrinsic layer 303 on described voltage control layer 301 surfaces, the ion of described the first extension intrinsic layer 303 and voltage control layer 301 interior doping has concentration gradient, and the ion concentration of described the first extension intrinsic layer 303 is less than the ion concentration of described voltage control layer 301;
Cover the insulating barrier 313 on described the first extension intrinsic layer 303 surfaces;
The opening (not indicating) that runs through described insulating barrier 313 thickness;
Be positioned at the second extension intrinsic layer 317 of described open bottom, described the second extension intrinsic layer 317 is positioned at described the first extension intrinsic layer 303 surfaces, and do not there is the doping ion in described the second extension intrinsic layer 317, or the ion concentration of its doping is less than the ion concentration of described the first extension intrinsic layer 303 interior doping;
Be positioned at grid structure (second grid structure), described grid structure and described insulating barrier 313 flush on described second extension intrinsic layer 317 surfaces of described opening.
Wherein, described Semiconductor substrate 300 is silicon substrate (Si) or silicon-on-insulator (SOI).In embodiments of the invention, described Semiconductor substrate 300 is silicon substrate, and its material is monocrystalline silicon, and its indices of crystallographic plane are (100).The ion concentration of described Semiconductor substrate 300 surfaces is greater than 1E18atoms/cm
3, be less than 1E19atoms/cm
3.Owing to forming the NMOS pipe in the embodiment of the present invention, doping ion in described Semiconductor substrate 300 is p-type, carrier mobility for the NMOS pipe channel region that improves follow-up formation, also comprise carbon ion in described Semiconductor substrate 300, and the volume ratio that the carbon ion of its doping accounts for the interior total doping ion of Semiconductor substrate 300 is less than 1%, especially is less than 0.4%.
It should be noted that, in other embodiments of the invention, when forming the PMOS pipe, doping ion in described Semiconductor substrate 300 is N-shaped, carrier mobility for the PMOS pipe channel region that improves follow-up formation, also comprise germanium ion in described Semiconductor substrate 300, and the volume ratio that the germanium ion of its doping accounts for the interior total doping ion of Semiconductor substrate 300 is less than 1%.
Have the doping ion in described voltage control layer 301, the concentration of described doping ion is greater than 5E17atoms/cm
3, be less than 5E18atoms/cm
3, to obtain the threshold voltage of little metal-oxide-semiconductor.In an embodiment of the present invention, described metal-oxide-semiconductor is the NMOS pipe, and the doping ion in described voltage control layer 301 is the p-type ion.For increasing the stress of NMOS pipe channel region, improve the carrier mobility of NMOS pipe channel region, go back the doping carbon ion in described voltage control layer 301, the volume ratio that the carbon ion of described doping accounts for total doping ion of voltage control layer 301 is less than 1%, when the volume ratio that especially when the carbon ion of voltage control layer 301 interior doping, accounts for total doping ion of voltage control layer 301 is less than 0.1%, the carrier mobility of the NMOS pipe channel region formed is high, and the threshold voltage of NMOS pipe is low.
It should be noted that, in other embodiments of the invention, when described metal-oxide-semiconductor is the PMOS pipe, the doping ion in described voltage control layer 301 is the N-shaped ion, go back the doped germanium ion in described voltage control layer 301, to improve channel region stress and the carrier mobility of PMOS pipe.Usually, when the volume ratio that accounts for total doping ion of voltage control layer 301 when the germanium ion of doping is less than 3%, the channel region stress of PMOS pipe and carrier mobility is high and the threshold voltage of PMOS pipe is low.
Described the first extension intrinsic layer 303 is for together adjusting the threshold voltage of metal-oxide-semiconductor with voltage control layer 301 and the second extension intrinsic layer 317.The ion concentration of described the first epitaxial loayer 303 is less than the interior ion concentration of described voltage control layer 301.In an embodiment of the present invention, owing to being the NMOS pipe, the ion of described extension intrinsic layer 303 interior doping is p-type.
It should be noted that, in other embodiments of the invention, when being the PMOS pipe, the ion of described extension intrinsic layer 303 interior doping is N-shaped.
Described insulating barrier 313 is for isolating the grid structure of adjacent mos pipe.Material oxidation silicon, silicon oxynitride or the silicon nitride of described insulating barrier 313.In an embodiment of the present invention, the material of described insulating barrier 313 is silica.
Do not there is the doping ion in the second extension intrinsic layer 317, or the ion concentration of the second extension intrinsic layer 317 interior doping is less than the ion concentration of described the first extension intrinsic layer 303 interior doping, for further reducing the threshold voltage of metal-oxide-semiconductor.Do not there is the doping ion in described the second epitaxial loayer 317, or there is the doping ion, but the ion concentration of described the second extension intrinsic layer 317 interior doping is less than 1E16atoms/cm
3.The thickness of described the second extension intrinsic layer 317 is 3nm-10nm.
Described grid structure (being the second grid structure) comprising: the side wall 319 that is positioned at described opening both sides; Cover the high-K gate dielectric layer 321 of described the second extension intrinsic layer 317 and side wall 319; Cover described high-K gate dielectric layer 321 and with the metal gate electrode layer 323 of described insulating barrier 313 flush.
It should be noted that, the MOS of the embodiment of the present invention also comprises: the light doping section 308 that is positioned at the first extension intrinsic layer 303 of described metal gate electrode 323 both sides; Be positioned at the source/drain region 311 of the first extension intrinsic layer 303 of described metal gate electrode layer 323 and side wall 319 both sides.Wherein, described light doping section 308 is for suppressing hot carrier's effect, and described source/drain region 311 is for the source of follow-up formation metal-oxide-semiconductor/drain electrode.
The metal-oxide-semiconductor of the embodiment of the present invention, have the first extension intrinsic layer and the second extension intrinsic layer, and be less than 1E16atoms/cm near the concentration that does not possess doping ion or doping ion in the second extension intrinsic layer of second grid structure
3, metal-oxide-semiconductor can obtain lower threshold voltage.
In sum, the technique that forms metal-oxide-semiconductor is simple, take the first grid structure as mask, in the first extension intrinsic layer behind formation source/drain region, remove described first grid structure and form the opening that exposes described the first extension intrinsic layer surface, and form the second extension intrinsic layer in described open bottom, then form the second grid structure that covers described the second extension intrinsic layer.The the second extension intrinsic layer formed is more near the second grid structure, existence due to the second extension intrinsic layer, even the ion concentration behind formation source/drain region in the first extension intrinsic layer increases, can not cause negative effect to the threshold voltage of the metal-oxide-semiconductor that forms yet, the threshold voltage of the metal-oxide-semiconductor that the embodiment of the present invention forms is low, the stable performance of the metal-oxide-semiconductor of formation.
Further, also comprise: form light doping section, described light doping section can effectively stop that heavily doped source/drain region intermediate ion, through high-K gate dielectric layer, impacts metal gate electrode layer, effectively suppress hot carrier's effect, the performance of the metal-oxide-semiconductor of formation is more stable.
Metal-oxide-semiconductor has the second extension intrinsic layer of close grid structure (second grid structure), does not possess doping ion or doping ion concentration in described the second extension intrinsic layer lower than 1E16atoms/cm
3, metal-oxide-semiconductor can obtain lower threshold voltage.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not break away from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (25)
1. the formation method of a metal-oxide-semiconductor, is characterized in that, comprising:
Semiconductor substrate is provided, described semiconductor substrate surface is coated with voltage control layer, described voltage control layer surface coverage has the first extension intrinsic layer, described the first extension intrinsic layer surface coverage has insulating barrier, there is the first grid structure that runs through its thickness in described insulating barrier, wherein, in described the first extension intrinsic layer and voltage control layer, the ion of doping has concentration gradient, and the ion concentration of described the first extension intrinsic layer is less than the ion concentration of described voltage control layer;
The described first grid structure of take is mask, to doping formation source/drain region in described the first extension intrinsic layer;
Remove described first grid structure, form the opening that exposes described the first extension intrinsic layer surface;
Form the second extension intrinsic layer that covers described open bottom;
Form the second grid structure that covers described the second extension intrinsic layer in described opening.
2. the formation method of metal-oxide-semiconductor as claimed in claim 1, is characterized in that, has the doping ion in described voltage control layer, and the concentration of described doping ion is greater than 5E17atoms/cm
3, be less than 5E18atoms/cm
3.
3. the formation method of metal-oxide-semiconductor as claimed in claim 2, it is characterized in that, when forming the NMOS pipe, doping ion in described voltage control layer is the p-type ion, in described voltage control layer, also doped with carbon ion, and the volume ratio that the carbon ion of doping accounts for total doping ion of voltage control layer is less than 1%; When forming the PMOS pipe, the doping ion in described voltage control layer is the N-shaped ion, and in described voltage control layer, also doped with germanium ion, and the volume ratio that the germanium ion of doping accounts for total doping ion of voltage control layer is less than 3%.
4. the formation method of metal-oxide-semiconductor as claimed in claim 3, is characterized in that, the volume ratio that the carbon ion of described doping accounts for total doping ion of voltage control layer is less than 0.1%.
5. the formation method of metal-oxide-semiconductor as claimed in claim 1, is characterized in that, in described the first extension intrinsic layer, do not have the doping ion; Or the ion concentration of doping in described the first extension intrinsic layer is less than 1E16atoms/cm
3.
6. the formation method of metal-oxide-semiconductor as claimed in claim 1, is characterized in that, in described the second extension intrinsic layer, do not have the doping ion; Or the ion concentration of doping in described the second extension intrinsic layer is less than 1E16atoms/cm
3.
7. the formation method of metal-oxide-semiconductor as claimed in claim 1, is characterized in that, the thickness of described the second epitaxial loayer is 3nm-10nm.
8. the formation method of metal-oxide-semiconductor as claimed in claim 1, is characterized in that, the formation technique of described the second extension intrinsic layer is the selective epitaxial depositing operation.
9. the formation method of metal-oxide-semiconductor as claimed in claim 1, is characterized in that, also comprises: before forming the second extension intrinsic layer, annealing in process is carried out in the first extension intrinsic layer surface of described open bottom.
10. the formation method of metal-oxide-semiconductor as claimed in claim 1, is characterized in that, the gas that described annealing in process adopts is hydrogen or argon gas.
11. the formation method of metal-oxide-semiconductor as claimed in claim 1, is characterized in that, the formation step of described first grid structure comprises: form the pseudo-gate electrode layer that runs through described insulating barrier and be positioned at described the first extension intrinsic layer surface; Formation is positioned at the pseudo-side wall of described pseudo-gate electrode layer both sides.
12. the formation method of metal-oxide-semiconductor as claimed in claim 11, is characterized in that, also comprises: after forming pseudo-gate electrode layer, before forming pseudo-side wall, the described pseudo-gate electrode layer of take is mask, to light dope in described the first extension intrinsic layer, forms light doping section; After forming pseudo-side wall, before forming insulating barrier, take described pseudo-side wall and pseudo-gate electrode layer is mask, to heavy doping in described the first extension intrinsic layer, formation source/drain region.
13. the formation method of metal-oxide-semiconductor as claimed in claim 1, is characterized in that, the formation step of described second grid structure comprises: form the side wall that is positioned at described opening both sides; Form the high-K gate dielectric layer that covers described the second extension intrinsic layer and side wall; Form the metal gate electrode layer that covers described high-K gate dielectric layer and flush with described surface of insulating layer.
14. the formation method of metal-oxide-semiconductor as claimed in claim 1, is characterized in that, also comprises: before forming the first grid structure, form the etching barrier layer that covers described the first extension intrinsic layer surface.
15. a metal-oxide-semiconductor, is characterized in that, comprising:
Semiconductor substrate;
Cover the voltage control layer of described semiconductor substrate surface;
Cover the first extension intrinsic layer on described voltage control layer surface, in described the first extension intrinsic layer and voltage control layer, the ion of doping has concentration gradient, and the ion concentration of described the first extension intrinsic layer is less than the ion concentration of described voltage control layer;
Cover the insulating barrier on described the first extension intrinsic layer surface;
The opening that runs through described thickness of insulating layer;
Be positioned at the second extension intrinsic layer of described open bottom, described the second extension intrinsic layer is positioned at described the first extension intrinsic layer surface, and do not there is the doping ion in described the second extension intrinsic layer, or the ion concentration of its doping is less than the ion concentration of doping in described the first extension intrinsic layer;
Be positioned at the grid structure (second grid structure) on the described second extension intrinsic layer surface of described opening, described grid structure flushes with described surface of insulating layer.
16. metal-oxide-semiconductor as claimed in claim 15, is characterized in that, in described the second extension intrinsic layer, do not have the doping ion, or the ion concentration of doping in described the second extension intrinsic layer is less than 1E16atoms/cm
3.
17. metal-oxide-semiconductor as claimed in claim 15, is characterized in that, the thickness of described the second extension intrinsic layer is 3nm-10nm.
18. metal-oxide-semiconductor as claimed in claim 15, is characterized in that, in described voltage control layer, the concentration of doping ion is greater than 5E17atoms/cm
3, be less than 5E18atoms/cm
3.
19. metal-oxide-semiconductor as claimed in claim 18, it is characterized in that, when managing for NMOS, the doping ion in described voltage control layer is the p-type ion, in described voltage control layer, also doped with carbon ion, and the volume ratio that the carbon ion of doping accounts for total doping ion of voltage control layer is less than 1%; When managing for PMOS, the doping ion in described voltage control layer is the N-shaped ion, and in described voltage control layer, also doped with germanium ion, and the volume ratio that the germanium ion of doping accounts for total doping ion of voltage control layer is less than 3%.
20. metal-oxide-semiconductor as claimed in claim 19, is characterized in that, the volume ratio that the carbon ion of described doping accounts for total doping ion of voltage control layer is less than 0.1%.
21. metal-oxide-semiconductor as claimed in claim 15, is characterized in that, described grid structure comprises the side wall that is positioned at described opening sidewalls; Cover the high-K gate dielectric layer of described the second extension intrinsic layer and sidewall; The metal gate electrode layer that covers described high-K gate dielectric layer and flush with described surface of insulating layer.
22. metal-oxide-semiconductor as claimed in claim 21, is characterized in that, also comprises: the light doping section that is positioned at the first extension intrinsic layer of described metal gate electrode layer both sides; Be positioned at the source/drain region of the first extension intrinsic layer of described metal gate electrode layer and side wall both sides.
23. metal-oxide-semiconductor as claimed in claim 15, is characterized in that, described semiconductor substrate surface place has the doping ion, and the concentration of described doping ion is greater than 1E18atoms/cm
3, be less than 1E19atoms/cm
3.
24. metal-oxide-semiconductor as claimed in claim 23, it is characterized in that, when managing for NMOS, the doping ion in described Semiconductor substrate is p-type, also comprise carbon ion in described Semiconductor substrate, and the volume ratio that described carbon ion accounts for total doping ion in Semiconductor substrate is less than 1%; When managing for PMOS, the doping ion in described Semiconductor substrate is N-shaped, also comprises germanium ion in described Semiconductor substrate, and the volume ratio that described germanium ion accounts for total doping ion in Semiconductor substrate is less than 1%.
25. metal-oxide-semiconductor as claimed in claim 24, is characterized in that, in described Semiconductor substrate, the carbon ion of doping accounts for total volume ratio of adulterating ion in Semiconductor substrate and is less than 0.4%.
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| US20090032843A1 (en) * | 2007-07-27 | 2009-02-05 | Atsushi Ohta | Semiconductor device and method for manufacturing the same |
| US20100044781A1 (en) * | 2007-03-28 | 2010-02-25 | Akihito Tanabe | Semiconductor device |
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| US20020037619A1 (en) * | 2000-09-22 | 2002-03-28 | Kohei Sugihara | Semiconductor device and method of producing the same |
| US20100044781A1 (en) * | 2007-03-28 | 2010-02-25 | Akihito Tanabe | Semiconductor device |
| US20090032843A1 (en) * | 2007-07-27 | 2009-02-05 | Atsushi Ohta | Semiconductor device and method for manufacturing the same |
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