CN103151070B - For the method and apparatus of FinFET SRAM array integrated circuit - Google Patents
For the method and apparatus of FinFET SRAM array integrated circuit Download PDFInfo
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
For providing single FinFET and multiple FinFET on a single integrated circuit? the method and apparatus of SRAM array.Describe the first single-port SRAM array of multiple first bit location, each first bit location has Y spacing Y1 and X spacing X1, the ratio of X1 and Y1 is more than or equal to 2, does each bit location have single fin FinFET transistor further to form 6T? sram cell, and unit CVdd power supply is connected to the first voltage control circuit; And the second single-port SRAM array of multiple second unit, each second unit has Y spacing Y2 and X spacing X2, the ratio of X2 and Y2 is more than or equal to 3, does each of multiple second unit comprise the 6T with many fins FinFET transistor? sram cell, wherein, the ratio of X2 and X1 is greater than about 1.1.
Description
Related application
The application and the title of the United States serial 13312810 that on Dec 6th, 2011 submits to are that the apply for agency case TSM11-1189 of " MethodandApparatusforfinFETSRAMCells " is relevant, and its full content is hereby expressly incorporated by reference.
Technical field
The present invention relates to semiconductor applications, more specifically, relate to the method and apparatus for FinFETSRAM array integrated circuit.
Background technology
Static RAM (" SRAM ") array is generally used for the storage in integrated circuit (IC)-components.The advanced sram cell of the use FinFET transistor of the nearest exploitation of the transistor technology of FinFET becomes possibility.Compared with previous planar MOS transistors (having the raceway groove being formed in semiconductor substrate surface place), FinFET has three dimension channel region.In FinFET, the raceway groove for transistor is formed in the side of " fin " of semiconductor material, and is sometimes also formed in top.The grid being generally polysilicon or metal gates extends above fin, and gate-dielectric is arranged between grid and fin.The 3D shape of FinFET channel region allows increase grid width and do not increase silicon area, though the total scale of device along with semiconductor technology convergent-divergent and with the grid length reduced and reducing; Rational channel width characteristic is provided with low silicon area cost.
But, when using the single fin FinFET transistor or " PU " transistor and transmission gate " PG " transistor formation sram cell that are used for pull-up, " Alpha's ratio " (i.e. the ratio PU_Ion/PG_Ion) of the On current (" Ion ") for PU and PG transistor is had a negative impact.Therefore, the sram cell formed by these transistors can demonstrate poor writes nargin tolerance, and can reduce unit positive voltage Vcc (" Vcc_min ") and keep the amount of suitable operation to reduce simultaneously.The power consumption of Vcc_min tolerance to the integrated circuit using sram cell reduced has a negative impact.In known method, the solution of the adjustment of the threshold voltage (" Vt ") of such as specific FinFET and grid length deformation adjustment is for increasing the performance of sram cell.But these methods suffer the ion implantation of additional photoetching or increase, add the cost of manufacturing process, and critical dimension or cell size problem can be produced.
In some applications, the main target of the SRAM array that integrated circuit uses is the silicon area that every bank bit uses, and it needs reduction as much as possible.But when SRAM stores for high-speed data processing, as the high-speed cache for microprocessor stores (in such as one-level " L1 " or secondary " L2 " plate buffer memory), access speed is also extremely important.For these GHz speed high-speed caches SRAM, unit can form to increase transistor drive current and operating speed by the transistor device of larger width.Be used to now provide the Vt of these devices with more large-drive-current or the use of other technique adjustment to produce additional treatments cost and manufacturing issue.
Summary of the invention
For solving the problem, the invention provides a kind of integrated circuit, comprise: the first single-port SRAM array of multiple first bit location, be configured in row and column, each bit location has the y spacing of distance Y1 and the x spacing of distance X1, the ratio of X1 and Y1 is more than or equal to 2, and each of multiple bit location forms the 6TSRAM unit of single fin FinFET transistor, and each in the first bit location receives the unit positive voltage source CVdd from the first voltage control circuit; And the second single-port SRAM array of multiple second unit, be configured in row and column, each second unit has the y spacing of distance Y2 and the x spacing of distance X2, the ratio of X2 and Y2 is more than or equal to 3, each of multiple second unit comprises 6TSRAM unit further, 6TSRAM unit comprises many fins FinFET transistor, and each in second unit receives the second unit positive voltage source CVdd from the second voltage control circuit; Wherein, the ratio of X2 and X1 is greater than about 1.1.
Wherein, each of first bit location comprises further: two phase inverters, cross connection is between memory node and complementary storage node, and each of two phase inverters comprises the single fin FinFET be connected between corresponding in unit positive voltage source CVdd and memory node and pulls up transistor and be connected to the single fin FinFET pull-down transistor in memory node between corresponding and unit negative voltage source CVss; And a pair transmission gate, be connected between one corresponding in corresponding one and memory node and complementary storage node in bit line and paratope line, each transmission gate comprises single fin FinFET transistor with the gate terminal being connected to wordline; Wherein, unit positive supply CVdd is connected to the first voltage control circuit; And wherein, each of second unit comprises further: two phase inverters, cross connection is between memory node and complementary storage node, and each single fin FinFET comprised between one that is connected in second unit positive voltage source CVdd and memory node of two phase inverters pulls up transistor and is connected to the many fins FinFET pull-down transistor in memory node between corresponding and unit negative voltage source CVss; And a pair transmission gate, be connected in bit line and paratope line between corresponding one corresponding with memory node and complementary storage node one, each transmission gate comprises many fins FinFET transistor with the grid being connected to wordline further.
Wherein, first voltage control circuit is write assist circuit, it comprises the input being connected to peripheral Vdd power lead, the output being connected to unit positive voltage source CVdd and enable input, and enable input has instruction and reads the reading state of circulation and the write state of instruction write circulation.
Wherein, in write cycle period, the first voltage control circuit exports the CVdd voltage lower than peripheral Vdd power lead.
Wherein, in reading cycle period, the first voltage control circuit exports the CVdd voltage being equal to or greater than peripheral Vdd power lead.
Wherein, the first voltage control circuit comprises standby mode circuit further, and the CVdd voltage exported lower than peripheral Vdd power lead in response to standby mode input.
Wherein, in write cycle period, the word line voltage to unit equals peripheral Vdd voltage, and the first voltage control circuit exports the CVdd voltage lower than word line voltage at least 50 millivolts.
Wherein, the first single-port SRAM array has the voltage control circuit of each row for the first bit location.
Wherein, for each of the first bit location, pull up transistor as the p-type transistor in n trap, and each of the first bit location comprises n trap web member further, n trap web member and unit positive voltage source CVdd electric isolution.
In addition, additionally provide a kind of integrated circuit, comprise: the first single-port SRAM array of multiple first bit location, be configured in row and column, each bit location has the y spacing of distance Y1 and the x spacing of distance X1, the ratio of X1 and Y1 is more than or equal to 2, and each of multiple bit location forms the 6TSRAM unit of single fin FinFET transistor, and each of the first bit location receives the unit positive voltage source CVdd from the first voltage control circuit; And the second single-port SRAM array of multiple second unit, be configured in row and column, each second unit has the y spacing of distance Y2 and the x spacing of distance X2, the ratio of X2 and Y2 is more than or equal to 3, each of multiple second unit comprises 6TSRAM unit further, 6TSRAM unit comprises many fins FinFET transistor, and each of second unit receives the second unit positive voltage source CVdd from predetermined Vdd voltage source; Wherein, the ratio of X2 and X1 is greater than about 1.1.
Wherein, each of first bit location comprises further: two phase inverters, cross connection is between memory node and complementary storage node, and each of two phase inverters comprises the single fin FinFET be connected between corresponding in unit positive voltage source CVdd and memory node and pulls up transistor and be connected to the single fin FinFET pull-down transistor in memory node between corresponding and unit negative voltage source CVss; And a pair transmission gate, be connected between one corresponding in corresponding one and memory node and complementary storage node in bit line and paratope line, each transmission gate comprises single fin FinFET transistor with the gate terminal being connected to wordline; Wherein, each of second unit comprises further: two phase inverters, cross connection is between memory node and complementary storage node, and each single fin FinFET comprised between one that is connected in second unit positive voltage source CVdd and memory node of two phase inverters pulls up transistor and is connected to the many fins FinFET pull-down transistor in memory node between corresponding and unit negative voltage source CVss; And a pair transmission gate, be connected in bit line and paratope line between corresponding one corresponding with memory node and complementary storage node one, each transmission gate comprises many fins FinFET transistor with the grid being connected to wordline further.
Wherein, first voltage control circuit comprises the voltage input node being connected to the input of Vdd power supply, the output being connected to unit positive voltage source CVdd and enable input further, and enable input has the waiting status that the reading state of circulation, the write state indicating write circulation and instruction standby mode are read in instruction.
Wherein, in write cycle period, the first voltage control circuit exports the CVdd voltage lower than the input of Vdd power supply.
Wherein, in reading cycle period, the first voltage control circuit exports the CVdd voltage being greater than the input of Vdd power supply.
Wherein, in write cycle period, wordline is in the voltage being substantially equal to the input of Vdd power supply, and the first voltage control circuit exports the voltage lower than word line voltage 50 millivolts to 400 millivolts.
This integrated circuit comprises further: Three S's array ram, Three S's array ram comprises multiple 3rd size bit location, each in 3rd size bit location comprises: two cross-coupled inverter, for storing data at memory node and complementary storage node place, each in cross-coupled inverter comprises the p-type list fin FinFET be connected between unit positive voltage CVdd one corresponding to memory node and complementary storage node and pulls up transistor, be connected to the N-shaped list fin FinFET pull-down transistor between corresponding and first module negative supply voltage Cvss in memory node and complementary storage node, and two write transmission gates, each comprises single fin FinFET transistor with the grid being connected to wordline, and by write bit line and complementary write bit line corresponding one be connected to corresponding memory node and complementary storage node, and read port, comprise and be connected in series in reading transmission gate between reading bit line and second unit negative supply voltage CVss and read pull-down transistor, read transmission gate and each reading in pull-down transistor comprises many fins FinFET.
In addition, additionally provide a kind of method, comprise: the first single-port SRAM array is set on the integrated, single-port SRAM array comprises further: multiple first size bit location, each in multiple first size bit location comprises the cross-coupled inverter pair for storing data on memory node and complementary storage node, and each of phase inverter centering comprises single fin FinFET pull-up device and single fin FinFET pull-down; And a pair transmission gate, to be connected in bit line and paratope line and memory node and complementary storage node between corresponding one, each in transmission gate comprises single fin FinFET with the grid being connected to wordline, and the first voltage control circuit exports first module positive voltage source CVdd to first size bit location; Second single-port SRAM array is set on the integrated, second single-port SRAM array comprises multiple second size bit location, each comprises: for storing the cross-coupled inverter pair of data on memory node and complementary storage node, and each phase inverter comprises single fin FinFET pull-up device and many fins FinFET pull-down; And a pair transmission gate, to be connected in bit line and paratope line and memory node and complementary storage node between corresponding one, each in transmission gate comprises many fins FinFET with the grid being connected to wordline, and the second voltage control circuit exports second unit positive voltage source CVdd to the second size bit location; First voltage control circuit and the second voltage control circuit are connected to peripheral voltage Vdd; And operation the first voltage control circuit, to change first module positive voltage source CVdd during institute's selection operation.
The method comprises further: during write operation, operates the first voltage control circuit, first module positive voltage source CVdd to be reduced to the voltage lower than peripheral voltage Vdd.
The method comprises further: at read operations, operates the first voltage control circuit, to export the first module positive voltage source CVdd being equal to or greater than peripheral voltage Vdd.
The method comprises further: waiting period to be operated, operates the first voltage supply circuit and the second voltage supply circuit, to reduce first module positive voltage source CVdd and second unit positive voltage source CVdd.
Accompanying drawing explanation
In order to more intactly understand the present invention and advantage thereof, carry out following description by reference to the accompanying drawings now, wherein:
Fig. 1 is to simplify the sram cell that circuit schematically illustrates embodiment use;
Fig. 2 simplifies with another optional sram cell that circuit schematically illustrates embodiment use;
Fig. 3 show in cross section bulk many fins FinFET that embodiment uses;
Fig. 4 show in cross section silicon-on-insulator many fins FinFET that embodiment uses;
Fig. 5 show in plan view the layout of embodiment sram cell;
Fig. 6 show in plan view the layout of embodiment sram cell;
Fig. 7 show in plan view the layout of another embodiment sram cell;
Fig. 8 shows the metal patterns used in SRAM array embodiment with top view;
Fig. 9 shows the selective metal pattern used in SRAM array embodiment with top view;
Figure 10 shows the voltage control circuit of embodiment use with block diagram;
Figure 11 shows embodiment voltage control circuit with block diagram;
Figure 12 shows SRAM array embodiment with block diagram;
Figure 13 show in plan view the cell layout of SRAM array embodiment;
Figure 14 show in plan view the layout of trap band (wellstrap) unit of Figure 13;
Figure 15 shows integrated circuit implementation with block diagram; And
Figure 16 shows embodiment of the method with process flow diagram.
Accompanying drawing, schematic diagram are schematic and be not used in restriction, but simplify the example of the embodiment of the present invention in order to illustration purpose, and accompanying drawing is not drawn in proportion.
Embodiment
Below discuss manufacture and the use of each embodiment in detail.But, should be appreciated that, present disclose provides many can specialize under various specific environment can application invention concept.The specific embodiment discussed is only the concrete mode manufacturing and use, and is not limited to the scope of the present disclosure and does not limit the scope of claims.
The embodiment of the application of the present detailed description example provides the novel method and apparatus for the manufacture of integrated circuit, wherein, integrated circuit comprises the high density manufactured in a single integrated circuit, single fin FinFETSRAM cell array and high speed, many fins FinFETSRAM cell array.The manufacture of performer and do not increase processing step and do not increase photoetching complexity, and the sram cell array of two types formed by FinFET in public technique and do not need that Vt adjusts, special raceway groove or gate length device or inject adjustment.
In one embodiment, the single fin FinFET transistor being used for all crystals pipe in unit is used to provide the sram cell array of the first type.Disclose there is the single-port SRAM unit of 6 transistors (" 6T ") and there is the dual-port sram cell of 8 transistors (" 8T ") as embodiment.Additionally provide the sram cell for more the second type of high-speed SRAM array.In an embodiment, the sram cell of the second type is by using the drive current that many fins FinFET transistor is larger for special transistor provides.Many fins FinFET transistor provides larger drive current for the transmission gate in sram cell and pull-down.In an embodiment, many fins FinFET has two, three or more fin to be to provide FinFET transistor in parallel.In certain embodiments, pull up transistor the single fin FinFET of maintenance.Embodiment provides Alpha's ratio of improvement by increasing PG_Ion electric current, what which thereby enhance unit writes nargin.By using the sram cell array of the first and second types in a single integrated circuit, can use public technique and simple manufacturing step on identity unit, meet performance required by high-speed SRAM array and high density SRAM, and not increase the manufacturing cost for additional photolithography step (such as injecting adjustment).
Fig. 1 shows the ball bearing made using figure of the 6TSRAM unit 10 that embodiment uses.In FIG, unit 10 stores data with true and complementary type on the memory node being designated as " SN " and " SNB ".Bit line (being sometimes referred to as " numeral " line) transmits and receive data from sram cell with true and complementary type on the bit line being designated as " BL " and the bit line bar being designated as " BLB ".In the SRAM array using 6T unit 10, carry out dispensing unit with row and column, and usually by bit line to formation row, each bit line between setting unit.Transmission gate transistor PG-1 and PG-2 is reading and is providing during write operation the access of the memory node to sram cell, and in response to the voltage in wordline " WL ", memory node is connected to bit line.
The storage area of SRAM circuit is formed by four transistors that the cross connection forming CMOS phase inverter is right.The PU-1 and pull-down transistor PD-1 that pulls up transistor is formed in the phase inverter that memory node SN place has output.The PU-2 and pull-down transistor PD-2 that pulls up transistor is formed in another phase inverter that memory node SNB place has output.First phase inverter be input as node SNB, be connected to the grid of transistor PU-1 and PD-1, and the second phase inverter be input as node SN, be connected to the grid of transistor PU-2 and PD-2.As shown in the figure, PU-1 and PU-2 that pull up transistor can be p-type transistor; When the gate terminal of these p-type transistor is under threshold voltage, these transistors are connected to corresponding memory node by conducting and by the unit positive voltage supply company being designated as " CVdd ", thus on the node exported " pull-up ".Pull-down transistor is generally n-type transistor, and when grid voltage exceedes predetermined threshold voltage, the memory node of correspondence is also connected to the ground for " unit Vss " or Vss supply that are designated as " CVss " by pull-down transistor conducting.Voltage supply will be connected to being designated as CVddN1, CVddN2 and being used for the unit of Nodes of CVssN1, CVssN2 of CVss for CVdd.
In operation, if transmission gate PG1 and PG2 is invalid, then sram cell 10 will maintain the complementary at node SN and SNB place indefinitely.This is because each phase inverter of cross-coupled inverter centering drives another input, thus maintain the voltage at memory node place.Maintenance is stablized by this situation, until remove electric energy or perform the write circulation changing and store data from SRAM.
In write cycle period, wordline WL will become effectively (being generally logical one or " height " voltage) and conducting transmission gate PG1 and PG2, memory node SN, SNB will be connected to corresponding bit line.If memory node SN is " logical one " or high voltage and bit-line voltage BL is " 0 " or low-voltage, then transmission gate transistor PG-1 and bit line BL will discharge memory node SN, contrary with the action of the PU-1 that pulls up transistor.Meanwhile, the complementary data on bit line BLB will be " 1 " or high voltage, and it will be connected to " low " voltage or " 0 " of the storage of node SNB place.Therefore, pull-down transistor PD-2 will attempt on bit line BLB drop-down.Along with memory node SNB rises, the PU-1 that pulls up transistor will end, along with memory node SN value declines (release due to by transmission gate PG-1), pull-down transistor PD-2 will end, similarly, PU-1 is pulled up transistor by conducting and memory node SN will rise to " 1 " or high voltage.Therefore, in write cycle period, when storing data exchange, PU-1 with PU-2 that pull up transistor can be connected with contrary with transmission gate (passgate) PG-1 and PG-2, and this is why " Alpha " is compared to write-access time important reason.If true and paratope line on the write data that present be different from the data be stored in sram cell, then transmission gate PG-1, PG-2 must overcome " pull-up " of transistor PU-1 and PU-2 in address period.
In reading cycle period, in " precharge " operation, bit line and bit line bar BL, BLB can be placed with medium voltage or high voltage.But in reading cycle period, bit line is not initially effectively driven.Then, wordline WL becomes effective and the bit line of correspondence is connected to memory node SN and SNB.One in two memory nodes will be logical zero or low-voltage, this means that in pull-down transistor PD-1 or PD-2 will be connected to bit line by transmission gate PG-1 or PG-2, and needs pairs of bit line be carried out discharging so that it is drop-down by pull-down transistor.So the driving intensity effect read access time of pull-down transistor.On the contrary, if bit line is the pre-charge voltage of logical one and the storing value of correspondence is logical one, then PU-1 or PU-2 that pull up transistor being connected to this bit line only needs to keep the voltage on bit line; So can see that the driving intensity pulled up transistor is not very strict for the read access time.
In optional sram cell Circnit Layout, embodiment can use dual-port sram cell.Fig. 2 shows dual-port sram cell 12 with simplified electrical circuit diagram.Again provide the 6TSRAM unit of Fig. 1 in the mode identical with Fig. 1, but present above-mentioned bit line is only designated as W_BL and W_BLB for write operation.There is provided special write wordline W_WL write bit line W_BL and W_BLB to be connected to memory node SN and SNB of sram cell.Be designated as the transistor of W-PG1 for writing transmission gate 1, W-PG2 for writing transmission gate 2, W-PD1 for writing pull-down transistor 1, W-PD2 for writing pull-down transistor 2.Write wordline is denoted as W_WL.
For storage and write, the carrying out described by 6T unit 10 in sram cell 12 as above Fig. 1 operates.During write operation, write bit line is connected to corresponding stored node SN and SNB in sram cell 12 by wordline W_WL to W_BL and W_BLB.As long as electric energy is supplied to unit via the unit positive supply CVdd at node CVddN1, CVddN2, CVssN1 and CVssN2 place and ground or Vss power supply CVss, just will the data that store of maintenance.
Read operation is different in this embodiment, and it has special reading bit line, is designated as R_BL.The use of special reading bit line makes small-signal sensor amplifier be used to the little reading output signal on R_BL to be amplified to full logic level in the output of the output bit-line of SRAM array.Sram cell is no longer connected directly to output bit-line at read, allows the less load on pulling up transistor, can use lower Vcc_min thus.In this embodiment, memory node SN is connected to the grid of transistor R-PD, and this transistor is pull-down transistor, is generally N-shaped device.Node CVssN is connected to ground or Vss voltage.At read operations, read wordline R_WL and become effective, can make transmission gate R-PG that reading bit line R_BL is connected to pull-down R_PD.Memory node SN is connected to R_PD transistor gate and is not attached to bit line, can realize operation faster and lower voltage level in sram cell.The read port added requires two extra transistor, and special reading bit line is by the row of unit.But special read port also add bandwidth and provides lower operating voltage (lower Vcc_min) for sram cell.
Fig. 3 show in cross section the spendable many fins FinFET 30 of embodiment.In figure 3, Semiconductor substrate 31 is shown.In this " many fin " configuration, fin 33 is formed by semiconductor material.Such as, fin 33 can be formed by lithographic pattern and etch process to remove semiconductor material from substrate 31.Illustrate that field oxide or other dielectrics 35 deposit on the surface of a substrate and partly extend to above the side of fin 33.Illustrate on the vertical side that gate-dielectric 37 is formed in fin 33 and top.Illustrate that grid 39 is deposited on the top of fin 37 and dielectric 37.Active region is formed on the end face of each fin 33, and is formed along the vertical side of each fin 33.Public grid 39 extends above three fins.If three further parallel joins of fin together, then can form single FinFET transistor; Alternatively, will structure shown in Fig. 3 be used to form three the single fin FinFET transistors having public grid and connect.Illustrate that inter-level dielectric material 41 is deposited on the top of grid material.Such as, grid 39 can be doped polycrystalline body pipe.Silicide can be formed in the top of grid 39 to reduce impedance.Metal gate material can be used for grid 39 to replace polysilicon or to combine with polysilicon.Gate-dielectric 37 can be for the oxide of gate-dielectric, nitride, high k or low-k materials.As is known, multilayer dielectric substance can be used for gate-dielectric, field oxide or interlayer dielectric.Fin 33 can carry out adulterating being formed source electrode outside the channel region that covered by grid 39 and drain region, thus forms FET transistor.Alternatively, fin can form the depletion-mode transistor with Uniform Doped fin.
In an alternative embodiment, Fig. 4 show in cross section silicon-on-insulator or " SOI " embodiment F inFET transistor 40.In the diagram, identical with Fig. 3 of multiple element, and common reference number is used for those elements.Silicon, germanium etc. can be comprised for the substrate 31 of Semiconductor substrate or other substrates as limiting examples, field oxide or other dielectrics 35 side of being deposited thereon are shown.Illustrate that epitaxial growth fin 43 is formed on the surface of insulator 35.Gate-dielectric 37, grid 39 and interlayer dielectric 41 are arranged as shown in Figure 3.The use of SOI fin makes to form fin by different process, but, residue element can be formed in the mode identical with Fig. 3 embodiment; SRAM array unit described below can use many fins or SOI fin mode.
Fig. 5 show in plan view the layout of the first embodiment sram cell 50 of single fin.In Figure 5, local interlinkage, fin and trap are shown for the 6TSRAM unit using single fin FinFET.As above-mentioned Fig. 1 marks transistor, such as PG-1, PU-2 etc.Fin is denoted as Fin1, Fin2, Fin3 and Fin4, and is respectively semiconductor fin.Fin1 and Fin4 is formed in the top of P_well-1 and P_well-2.Fin2 and 3 is formed in the top of N well region to be provided for the semiconductor regions of p-type transistor PU-1, PU-2.N well region additionally provides the contact of body for p-type transistor or block terminal (bulkterminal), and in the embodiment of sram cell, it can be connected to different positive voltages to strengthen the property further.This fin provides for the raceway groove of N-shaped device, source electrode and drain region, such as PD-1 and PG-1 of Fin1 and PD-2 and PG-2 for Fin4.For each transistor, grid material is shown, and grid covers fin, form transistor.Therefore, for illustrate and in this orientation optional, PD-1 is formed in the top of the bottom of Fin1, and PG-2 is formed in the top of the bottom of Fin4.
Fin is also the tie point for higher level's metal patterns (Fig. 5 is not shown), and so that sram cell is connected to bit line, wordline, and unit electric energy provides CVdd and CVss.Such as, institute target WLC1 and WLC2 in wordline hookup.Show that the contact of the rectangle material for having X pattern will vertically extend as the metal in the opening formed in the dielectric layer or other conductive materials, and vertical connection will be provided for covering metal conductor.Contact also provides local interlinkage between elements, and such as, the bottom of Fin3 is connected to the bottom of Fin4.When needed, also show through hole, it is shown in center and has the round-shaped of X, and through hole vertically between different metal levels (such as between metal metal-1 and metal-2) connection is provided.So wordline contact WLC1 is shown to have covering through hole.Contact also provides local interlinkage, the such as contact at memory node SN place, and the corresponding source/drain terminal of the grid of PU-2, PD-2 and transistor PU-1 (Fin2) and PD-1 (Fin1) etc. links together by it.Bit line node BLND is connected to a source/drain of transmission gate transistor PG-1 by Fin1, memory node SN is connected in another source/drain terminal, so these nodes can be linked together by conducting transmission gate transistor PG-1 by the voltage in the wordline of WLC1.Similarly, Fin4 provides bit line bar Node B LBND at a source/drain terminal place of transmission gate transistor PG-2, and wordline contact WLC2 and through hole thereof provide connection for wordline, make word line voltage can conducting PG-2 so that BLBND is connected to memory node SNB.
Sram cell 50 has center N trap part, and it forms fin Fin2 and Fin3.Fin2 provides as the node CVddN1 in Fig. 1, is connected to a terminal of the PU-1 that pulls up transistor by contact and through hole.Fin2 also provides the memory node SN of the another terminal being connected to PU-1.Fin3 provides the terminal being connected to all PU-2 that pulls up transistor as shown in Figure 1, and another source/drain terminal is connected to SNB as shown in Figure 1.As shown in Figure 1, PU-1 and PU-2 is generally p-type transistor.N trap can be connected to voltage terminal and be connected to provide block or body for the transistor be formed on Fin2 with Fin3.Such as, N trap can be connected to peripheral Vdd power lead, importantly this voltage and unit positive voltage CVdd electric isolution.In other embodiments, N trap can be connected to unit supply voltage CVdd.
Unit 50 has spacing Y1 and have spacing X1 in level or X-direction in vertical or Y-direction.The physical size of these spacing is determined by the design rule of semiconductor technology that using and scale.In a particular embodiment, the ratio of X1 and Y1 can be more than or equal to 2.As described below, the unit of the Second Type combinationally used with single fin embodiment of Fig. 5 has larger X spacing, that is, X-direction gap ratio X1 is greatly at least about 1.1.
Fig. 6 show in plan view the exemplary embodiment of the sram cell 60 of the second type, for many fins FinFETSRAM unit of 6T unit.In figure 6, circuit function is identical with the circuit in Fig. 1.Bit line node BLND and BLBND is connected to memory node SN and SNB by transmission gate transistor PG-1 and PG-2 again respectively.In N trap, form PU-1 and PU-2 that pull up transistor, and the unit positive supply CVdd at node CVddN1 and CVddN2 place is connected to node SN and SNB.As shown in Figure 5, transistor PU-1 is formed on Fin2, and PU-2 is formed on Fin3.
In this embodiment, use for the fin of pull-down transistor PD-1 and transmission gate transistor PG-1 fin Fin1A and Fin1B that be connected in parallel and double.That is, the grid for PG-1 extends above fin Fin1A and Fin1B.Fin links together at a source/drain terminal place of transistor PG-1 by the contact at Node B LND place.Similarly, the residue source/drain terminal of transistor PG-1 links together by the contact at memory node SN place, makes two fin Fin1A and Fin1B formation for the single larger driving transistors of transmission gate PG-1.Similarly, be formed in fin Fin1A and Fin1B for the source electrode of transistor PD-1 and drain terminal, and grid extends above fin Fin1A and Fin1B.In this embodiment, two fins be used for N-type transistor PG-1, PD-1 each, and for PG-2 and PD-2.PG-2 and PD-2 is formed in the top of fin Fin4A and Fin4B, and they are all in P_well-2.Wordline (not shown) is by the grid at wordline contact WLC1 place contact PG-1, and bit line node BLND is connected to memory node SN in response to the voltage in wordline by this transmission gate.Similarly, wordline contact WLC2 provides the connection of the grid for transmission gate PG-2, and bit line bar Node B LBND is connected to memory node SNB by it.Note, the flat contact for memory node SN is now wider to cover fin Fin1A and Fin1B, and similarly, the flat contact for SNB extends above fin Fin4A and Fin4B.
In operation, two embodiments (the single FinFET unit of Fig. 5 and multiple FinFET unit of Fig. 6) operate respectively in the same manner.But the n-type transistor due to Fig. 6 many fins FinFET embodiment has the driving intensity of interpolation, so the electrical connection of those unit can be simplified, this will be described further below.As shown in Figure 6, many fins embodiment of Fig. 6 has different distance Y2 and X2.The ratio of X2 and Y2 can be such as be more than or equal to 3.The many fins in Fig. 6 are used to increase X spacing above single fin configuration of Fig. 5.Such as, X2 can be greater than X1, and the design rule of the given set of semiconductor technology is at least to 1.1 times of X1.But Y spacing does not increase, and Y1 can be substantially equal to Y2; Although in an alternative embodiment, spacing can be different.If require further to drive intensity, the quantity for the fin of Fin1 and Fin4 can expand to three, a four or more fin.In these embodiment, X spacing X2 can increase further.In these embodiments, contact and will extend further with the increase spacing corresponded between fin, and source electrode and drain electrode part are joined together to form many fins FinFET transistor.
Fig. 7 show in plan view the layout of the embodiment sram cell 70 of the two-port SRAM circuit implementing Fig. 2.In the figure 7, single fin transistor, for the formation of the transistor of 6TSRAM unit, comprises write transmission gate W_PG-1, W_PG-2 and pull-up and pull-down transistor PU-1, PD-1, PU-2, PD-2.Arrange write wordline at contact W_WLC1 with W_WLC2 and the through hole that is associated to be connected.Fin Fin1, Fin2, Fin3 and Fin4 be provided for respectively having cover fin mark the source electrode of the FinFET transistor of transistor gate, drain electrode and channel region.During write operation, write wordline will be connected to the grid of transistor W-PG-1 and W-PG-2, and the voltage on bit line node W_BLND and W_BLBND place bit line is connected to cell storage node SN and SNB by making transistor by high voltage in wordline respectively.
As the circuit diagram of Fig. 2, sram cell 70 has the reading transistor pair that special reading bit line is connected with cascade system of connecting.Transmission gate R-PG has the grid being connected to and reading wordline contact RWLC.When read operation, when reading wordline and being effective, the reading bit line at node R BLND place is connected to pull-down transistor R-PD by transmission gate R-PG.Note, cell storage node SN is isolated by read port transistor AND gate reading bit line R_BLND, unit pull-down transistor PD-1, PD-2 is made not to be the capacitive loads of the bit line that must discharge node R BLND place, dual-port sram cell can operate with the voltage CVdd reduced thus, and is not used in the increase driving intensity transistor used in Fig. 6 embodiment.The cost of isolating for this bit line unit is the area used by transistor R_PG and R_PD of special reading bit line and increase.When the bank bit at node SN place be " 1 " or high voltage time, the Vss that reading bit line node R _ BLND is connected to ground or CVssN2 place by pull-down transistor R_PD supplies.
Because read port transistor is by release read bitline, implement these transistors so be formed in this exemplary embodiment of the many fins FinFET be designated as on two fins of Fin5A and Fin5B in use.The use of many fins adds the channel width of read port transistor and drives intensity.Additional fin can be used for increasing and further drives intensity, and these amendment configurations provide additional alternative embodiment.
In the embodiment of Fig. 5, Fig. 6, Fig. 7, fin is shown to have common width.But some fins can have the width different from other fins, such as, the fin in N well region can wider than the fin in P well area.These are revised as above-mentioned each unit and provide additional alternative embodiment.
In order to represent clear, illustrate that Fig. 5, Fig. 6 of each embodiment and the layout of Fig. 7 show topological interconnection, contact, through hole are connected with grid, but eliminate metal level.Fig. 8 shows an embodiment of the covering metal pattern for sram cell with simplified plan view.In fig. 8, word line conductor (it can be metal-1 or metal-2 conductor) is illustrated as extending across in the middle of unit in the X direction.Check the through hole contacted with the wordline of Fig. 7 for Fig. 5, Fig. 6, can observe, wordline connection is from left to right configured along the core of unit usually.Configured in parallel on the opposite side that bit line and bit line bar are connected to N trap and extending in the Y direction.Dispensing unit positive supply CVdd in the Y-direction that N trap upper center extends.Again check the layout of Fig. 5 and Fig. 6, such as, can observe, node CVddN1 with CVddN2 and the through hole be associated linearly configure for vertical connection.
In the embodiment in fig. 8, the first and second Vss lines are also shown in the right outside vertical configuration in the outside of N trap and opposite side and bit line.Such as, node CVssN1 with CVssN2 in Fig. 5 with Fig. 6 shows the contact that is connected for these and through hole and is formed on which place of each cell layout.In the embodiment in fig. 8, in row, configure bit line, CVdd and the first and second CVss lines.These conductors can be formed in metal 1, metal 2 or other metal levels, as long as they are isolated from each other and isolate with word line conductor.Note, for dual-port embodiment sram cell (all layouts as shown in Figure 7), read word line conductor and additional reading bit line conductor by additional for interpolation.Can be formed abreast to add with word line conductor shown in Fig. 8 and read word line conductor; Similarly, can be parallel with the bit line bar conductor of Fig. 8 or form the reading bit line conductor of increase with closing on it; Represented by contact as shown in Figure 7.
Fig. 9 show in plan view the selective metal pattern that can be used for the sram cell of Fig. 5, Fig. 6 and Fig. 7 being connected to corresponding metal level conductor.In fig .9, along the X direction or be expert at middle formation word line conductor and the first and second Vss conductors; And Vdd conductor CVdd and bit line are in the Y direction and parallel or extend in row.Again check contacting and through hole shown in Fig. 5 with Fig. 6, easily can observe aiming at of cell node and conductor.
Some is different in the operation of single fin FinFETSRAM unit and many fins FinFETSRAM unit embodiment, and in use cellular array, Control of Voltage or " assisting " circuit can be used for the different voltages for different operating providing unit positive supply CVdd.For single fin FinFETSRAM unit, in write circulation, use the CVdd voltage of reduction, and reading in circulation the voltage using the voltage be equal to or greater than in wordline.For many fins sram cell, reading and write operation do not require any different CVdd voltage, although in certain embodiments, voltage control circuit is used in the CVdd providing reduction in all types of unit for standby mode.
For each embodiment sram cell, table 1 shows the multiple characteristics shown compared with the unit of other types.
Table 1
As shown in table 1, the sram cell of the first kind requires that adjunct circuit is to be provided in the different voltages that CVdd line needs for specific operation.In certain embodiments, wait for that auxiliary circuit can also be used by the sram cell of Second Type.Figure 10 shows column voltage control circuit 75, and as described further below, it can be arranged for each row in example SRAM array.As shown in table 1, enable control signal can make voltage control circuit 75 output voltage CVdd during write operation, and it is less than the voltage that wordline V_WL places.In addition, in other embodiments, circuit can also export rising or the booster tension of CVdd at read operations; Alternatively, voltage CVdd can be approximately equal to the word line circuit in read operation, and this illustrates in Table 1.Finally, when SRAM array is in " wait " pattern, unit positive voltage CVdd can reduce similar 600 millivolts from nominal level substantially, and this also illustrates in Table 1.When arranging (such as phone, graphic tablet, kneetop computer, PDA, reading machine, music or video player etc.) middle use in powered battery and comprising system or the integrated circuit of SRAM array, this feature is especially remarkable.Note, many fins FinFETSRAM cellular array that voltage control circuit can also be in the Second Type of standby mode uses to reduce electric energy.
As shown in table 1, for sram cell that is faster or Second Type, many fins FinFETSRAM unit of embodiment, for simple than for single fin FinFET unit embodiment of the voltage supply level that reads and write.Usually, for reading and the write circulation of these unit, unit supply voltage CVdd is approximately equal to the effective high voltage on wordline V_WL.Such as, the increase of the transmission gate in these larger sram cells and drop-down FinFET drives intensity to decrease the demand of read increase cell voltage.Pull-down transistor in many fins unit has the drive current of increase with drop-down bit line; Or allow to reduce unit supply voltage in address period.Transmission gate transistor in these unit is also many fins device, and has the drive current of increase, to overcome previously stored data on memory node in data address period.In standby mode, many fins FinFET unit can also reduce their unit Vdd supply voltage to save electric energy.This also illustrates in Table 1.Alternatively, the unit positive voltage source CVdd of many fins FinFET unit can be connected directly to peripheral voltage Vdd, and in the configuration, for these sram cells, does not need voltage control circuit.
Figure 11 shows the simplified electrical circuit diagram of selectable voltage control circuit 76.In fig. 11, replace creating the reduction voltage for writing and the alive voltage control circuit of increasing for reading, input Vdd voltage comprises " hi " and " lo " voltage.Then, voltage control circuit 76 is selected between which based on control inputs signal, and exports to the CVdd of unit the voltage selected.Again, as shown in table 1, unit positive voltage CVdd can write and etc. period to be operated reduce and increase at read, to strengthen the access time of single fin embodiment sram cell.For the sram cell of Second Type with many fins FinFET, only have standby mode can use the CVdd of reduction.
Figure 12 shows and uses the embodiment SRAM array 80 of the FinFET unit 50 of such as Fig. 5 to form array.The FinFET unit 60 of Fig. 6 can also be used.Sram cell 50 is configured in the row being designated as C1-CN.Each row of unit all have the unit Vdd line being designated as CVDD_1-CVdd_N.To be expert at middle allocation unit unit, and the every a line along unit extends by wordline (not shown in order to simplify).In given circulation (such as reading circulation), can by the row of the voltage selection unit in wordline, and the data stored export at the bit line often arranged (not shown in this Figure) is upper.
Each row of unit C1-Cn all have CVdd control circuit 75.Be input as single Vdd voltage in this example embodiment, such as Vdd is peripheral.Alternatively, such as, voltage control circuit for shown in Figure 11, and can receive high and low voltage input.
Figure 13 there is shown the layout of the SRAM array 85 of the sram cell using embodiment in another plane.In fig. 13, SRAM array comprises the row of the unit being designated as " trap tape cell ".These unit do not store data, but instead provide the connection between N and P trap to provide block terminal voltage as required.Similarly, the edge of SRAM array 85 comprises column border band/dummy unit, and it provides connection for voltage supply Vdd and Vss.In addition, as shown in the figure, array comprises WL_edge (edge) dummy unit, and it provides the connection for wordline, and can comprise the drive circuit for wordline.
The layout of the single trap tape cell that Figure 14 array 85 that show in plan view in Figure 13 uses.In fig. 14, bit location is illustrated in the top of trap tape cell.Such as, bit location can be single fin embodiment sram cell of Fig. 5.In row conductor (such as, can be the metal level of such as metal-2), left side is a CVss line, is then bit line, CVdd line is extended by the core of bit location, bit line bar line, is the 2nd CVss line afterwards.In being expert at, wordline flatly extends across bit location, and wordline can be metal-1 conductor, such as, be separated with row conductor by interlayer dielectric.Other metal level can also be used.In trap tape cell, such as, through hole is illustrated and N trap band line is connected to Cvdd line.In an array, the trap metal using the N trap of the configuration of Figure 14 can have for CVdd connects.Can be applicable to unit as can be seen from Table 1 and there is no voltage auxiliary circuit, that is, there is the unit of many fins FinFET.P trap band line also horizontal-extending and use two through holes (for a CVss line, another is for the 2nd CVss line) to be connected to Vss.
For single fin FinFETSRAM unit embodiment, as shown in table 1, N trap and CVdd isolate, and N trap can not be connected to the CVdd for these embodiment unit by the through hole of Figure 14.Instead, Vdd will be connected to from peripheral or another source electrode for the N trap band of these unit and with CVdd electric isolution.
Figure 15 shows the embodiment integrated circuit of the core processor of three SRAM array being connected to the general-purpose storage being configured to grade 1 high-speed cache L1, grade 2 high-speed cache L2 and being designated as SRAM with block diagram.Core processor can be the license core, digital signal processor (" DSP ") etc. of microprocessor, Reduced Instruction Set Computer (RISC) core, such as SRM core.Such as, single fin FinFETSRAM unit of Fig. 5 may be used for being formed on integrated circuit 87 storing SRAM.For the SRAM array of the type, density (data bit of per unit area) is most important.For high-speed cache L1 and L2, such as, can use many fins FinFET unit of Fig. 6.For high-speed cache SRAM array, the area that data access speed uses than every is more important.Alternatively, the dual-port sram cell of Fig. 7 can be used for L1 or the L2 cache arrays which may on integrated circuit 87.
Figure 16 shows process flow diagram with case method embodiment.In a step 61, the first array of the sram cell of single fin FinFET transistor is formed on a semiconductor substrate.In step 63, form the second array comprising the sram cell of many fins FinFET transistor on a semiconductor substrate.In step 65, in the write cycle period of the first array for sram cell, unit positive voltage CVdd is reduced to the level of the voltage in the wordline being less than selected unit; And in step 67, in wait cycle period, unit positive voltage CVdd is reduced to the first array of sram cell and the sram cell of the second array.By unit supply voltage being changed into the less sram cell only with single fin FinFET transistor, can improve and write nargin and read the access time; And for having the larger area sram cell of many fins FinFET transistor on identity unit, change unit positive voltage CVdd not necessarily.
Use the embodiment of the application directly in single manufacturing process, to provide high density and high-speed SRAM array in a single integrated circuit, and this ability is provided and does not need the injection of Additional manufacturing steps, complexity and the design of Vt adjustment or the certain device change grid length for sram cell.
In the exemplary embodiment, a kind of integrated circuit comprises at least two SRAM array of different units.The single FinFET transistor of each of each transistor of the first single-port SRAM array by the cross-coupled inverter for sram cell of 6TSRAM unit and two transmission gates for each sram cell is formed.Each sram cell is connected to unit positive supply CVdd, unit negative supply CVss and for selecting bit line and the wordline pair of sram cell.CVdd line for each unit is connected to the first voltage control circuit.The second SRAM array on integrated circuit is the single-port SRAM array of the 6T unit of the second type; Each is formed by cross-coupled inverter, and each phase inverter comprises single FinFETp type and pulls up transistor and many fins FinFETn type pull-down transistor.The sram cell of each Second Type also comprises two transmission gates being connected to true and paratope line, and two transmission gates are formed respectively by many fins FinFET transistor, and each sram cell of the second array is connected to the second voltage control circuit.The sram cell of the first array has spacing X1 in the X direction and has spacing Y1 in the Y direction; And the sram cell of the second array has spacing X2 in the X direction and have spacing Y2 in the Y direction; The ratio of X1 and Y1 is more than or equal to about 2, and the ratio of X2 and Y2 is more than or equal to about 3, and the ratio of X2 and X1 is greater than about 1.1.
In other embodiment, the first voltage control circuit is write assist circuit, and it is connected to the sram cell of the first SRAM array, and it receives the input from the peripheral supply line of Vdd further, and it has the output being connected to unit supply voltage CVdd.First voltage control circuit has enable input, and it has the first state for writing circulation and the second state for reading circulation.In write circulation, the output on unit supply voltage CVdd is lower than input voltage.In reading circulation, the output on unit supply voltage CVdd is greater than or equal to input voltage.
In an additional embodiment, in the integrated circuit with two SRAM array, the second voltage control circuit be standby mode circuit and have voltage input, enable input, and on the unit supply voltage CVdd for sram cell output voltage.Voltage input can be connected to the supply voltage of such as peripheral Vdd electric energy voltage.Enable input has two states, one for read or write circulation, second for etc. to be recycled.In reading or write cycle period, voltage exports and is substantially equal to input voltage.Wait to be recycled in, voltage export lower than input voltage.In an additional embodiment, the output voltage of reduction can be lower than the input voltage of the second voltage control circuit about 100 millivolts to 600 millivolts.
In other embodiment, the SRAM array in integrated circuit can have wordline, and it is placed in the voltage equaling peripheral Vdd voltage level or Vss or ground voltage level.In write cycle period, wordline can be in the level of peripheral Vdd voltage, and the sram cell in the first array can have the supply voltage CVdd being less than word line voltage.In an additional embodiment, voltage CVdd can lower than word line voltage 50 millivolts to about 400 millivolts.
In an additional embodiment, the p-type of the sram cell in the first and second arrays pulls up transistor and can have source electrode, drain electrode and block terminal.Block terminal is formed by N-type light dope N trap.In the first SRAM array of integrated circuit, N trap can contact in N trap tape cell.N trap tape cell is placed on the center of array, or is placed on array edges alternatively, and has the trap metal wire extended by N trap tape cell.Trap metal wire can be connected to positive voltage, itself and unit supply voltage CVdd (such as Vdd is peripheral) electric isolution.In another embodiment, the trap metal wire of the first SRAM array can be isolated with unit supply voltage CVdd, and the trap metal wire of the second SRAM array is connected to unit supply voltage CVdd.
In another embodiment, the first voltage control circuit can for reading auxiliary circuit.Read auxiliary circuit and can have the input being connected to predetermined positive voltage.Output is connected to unit positive supply CVdd.First voltage control circuit has enable input, and it has two states, one for writing circulation, another is for reading circulation.The output of reading in circulation is substantially equal to or higher than input voltage.In another embodiment, in reading cycle period, the output of the first voltage control circuit can between be greater than voltage in write cycle period wordline 30 millivolts and 200 millivolts.
In other embodiment, in row and column, configure the sram cell of the first and second SRAM array.Wordline is parallel with row and extends along row, and bit line pair with arrange parallel and extend along arranging.Sram cell to be configured between true and paratope line and to be connected to true and paratope line.First voltage control circuit carries out arranging for each row of unit and is provided for the CVDD supply of cell columns.In addition, unit negative supply voltage line CVss extends and the pull-down transistor be connected in cell columns along the row of unit.
In another embodiment, the sram cell of the first SRAM array has spacing Y1 in the Y direction, and the sram cell of the second SRAM array has spacing Y2 in the Y direction, spacing Y1 and Y2 approximately equal.
In another embodiment, a kind of integrated circuit comprises: two single-port SRAM arrays; First SRAM array of first size unit and the second SRAM array of the second dimension cells.First SRAM array is formed by 6TSRAM unit, it is included in memory node and is connected phase inverter with pair of cross complementary storage node storing data, and has and to connect between bit line and paratope line and to be connected to the transmission gate of memory node and complementary storage node.First array of sram cell is connected to voltage control circuit respectively, and it is to unit providing unit positive voltage CVdd.Each transistor in 6TSRAM unit in first array is single fin FinFET transistor.Second array of sram cell is formed by 6TSRAM unit, it comprises pair of cross and connects phase inverter, each phase inverter has single fin FinFET and pulls up transistor and many fins FinFET pull-down transistor, and each sram cell comprises further and is connected to memory node and complementary storage node and two transmission gates between bit line and paratope line, two transmission gates are formed by many fins FinFET respectively; And each 6TSRAM unit in the second array has the unit positive supply CVdd being connected directly to predetermined VDD supply voltage.The sram cell of integrated circuit has X-direction spacing and Y-direction spacing respectively, and the unit in the first SRAM array has X spacing X1 and Y spacing Y1, and X1 is equal to or greater than the about twice of Y1; Sram cell in second SRAM array has X spacing X2 and Y spacing Y2, and X2 is equal to or greater than about three times of Y2, and the ratio of X2 and X1 is equal to or greater than about 1.1.
In another embodiment, the voltage control circuit in the first SRAM array is write assist circuit.Voltage control circuit has input voltage, is connected to the output of unit positive voltage CVdd and enable input signal.In an embodiment, input node is connected to Vdd peripheral power supply.Enable input signal circulates as a state for write, and for reading circulation as another state.In write cycle period, voltage control circuit exports the voltage lower than input voltage on unit supply voltage CVdd.In reading cycle period, voltage control circuit exports the voltage being substantially equal to or being greater than input voltage.
In another embodiment, in the integrated circuit with two SRAM array, controlled the transmission gate of each sram cell by wordline.Word line voltage can be controlled by Vdd peripheral power supply line and Vss power lead.In write cycle period, wordline can equal the voltage on Vdd peripheral power supply line.In write cycle period, voltage control circuit can voltage on output unit positive supply CVdd, and it is less than word line voltage.In an embodiment, CVdd line can be lower than input voltage 50 millivolts to 400 millivolts.
In another embodiment, in the integrated circuit of two SRAM array with first size unit and the second dimension cells, each of cross-coupled inverter comprise have source electrode, drain electrode, grid and block terminal p-type pull up transistor.In an embodiment, block terminal is N-type light dope N trap.Trap tape cell can be configured in center or the wedge place of SRAM array, and is connected to trap band metal wire by both contact, through hole or contact and through hole.In another embodiment, trap band metal wire is connected to positive voltage Vdd periphery.
In another embodiment, the trap metal wire of first size sram cell be connected to Vdd peripheral and with unit positive voltage CVdd electric isolution.In another embodiment, the trap metal wire of the second size sram cell is connected to the unit positive voltage CVdd of the second array for sram cell.
In another embodiment, in said integrated circuit, the voltage control circuit for the first SRAM array is reading auxiliary circuit.Voltage control circuit is reading the voltage on cycle period output unit positive power line CVdd, and it is greater than input voltage.In an embodiment, the voltage on read CVdd can than input voltage larger about 30 millivolts to about 200 millivolts.
In another embodiment, the sram cell of the first and second SRAM array of collocating integrate circuit in row and column.Each row of first SRAM array of first size sram cell all have the voltage control circuit being connected to unit positive supply CVdd.Each row of unit are all connected between true and paratope line, and each row of unit are all connected at least one negative unit supply CVss.
In another embodiment, the integrated circuit with the first and second SRAM array can comprise Three S's array ram, and it can be dual-port SRAM array.Each sram cell in dual-port SRAM array is the unit of the third type, and it has pair of cross and connects phase inverter for storing write data on memory node and complementary storage node.Each of the sram cell of the third type in dual-port SRAM array has a pair write transmission gate, and they are connected to the memory node of true and complementary write bit line and correspondence.Each unit in dual-port SRAM array have in true and complementary storage node one with the read port be connected between reading bit line.In one embodiment, each read port is included in the reading transmission gate and reading pull-down transistor that connect in series connection cascade circuit.In response to the reading word-line signal on the grid of transmission gate and be connected to pull-down transistor grid memory node on voltage, reading bit line is connected to negative supply voltage CVss by read port.Reading is conveyed through door and reads pull-down transistor and formed by many fins FinFET transistor respectively.In an additional embodiment, reading transmission gate and read pull-down transistor can be N-type many fins FinFET transistor.In another embodiment, other transistors in dual-port sram cell can also be formed by many fins FinFET transistor, and pulling up transistor in the sram cell of the third type is formed by single fin FinFET transistor.
In another embodiment, in dual-port SRAM array, with row and column dispensing unit.Be that each row of the dual-port sram cell of the 3rd type arrange write assist circuit.Each write assist circuit receives positive voltage source Vdd in write cycle period and bit-line voltage is exported to the write bit line of the sram cell in row.In an additional embodiment, write assist circuit can write the voltage (negative voltage) on cycle period output write bit line as pulse or waveform.
In another embodiment, integrated circuit comprises at least the first single-port SRAM array of the sram cell with first module size.Each first module size sram cell is formed by 6TSRAM unit, and it has cross-coupled inverter, and they are connected to store data on memory node and complementary storage node; And each unit is connected to bit line pair that is true and paratope line in response to the voltage in wordline further by transmission gate.Each transistor in first module size sram cell is single fin FinFET transistor.Each cross-coupled inverter of first module size sram cell comprises p-type and pulls up transistor, and it is connected between in true and complementary storage node one and unit positive supply CVdd.Each of unit in first SRAM array arranges the write assist circuit all comprised for output unit positive voltage CVdd.
In identical integrated circuit, at least the second single-port SRAM array is provided to have the 6TSRAM unit of second unit size.The sram cell of second unit size comprises: cross-coupled inverter, and they are connected for storing data on memory node and complementary storage node; And transmission gate pair, for will there is the bit line of true and paratope line to being connected to corresponding memory node in response to the word line voltage on the gate terminal of transmission gate.Cross-coupled inverter comprises N-shaped pull-down transistor and p-type pulls up transistor.Pull up transistor and unit positive voltage CVdd is connected to a memory node of correspondence.The pull-down transistor of second unit size sram cell and transmission gate are formed by many fins FinFET transistor, and pull up transistor and to be formed by single fin FinFET transistor.The unit of the second SRAM array is also configured with row and column, but unit positive supply CVdd is connected to predetermined voltage and does not use write assist circuit in the second SRAM array.
In said integrated circuit, first module size sram cell has Y-direction spacing Y1 and X-direction spacing X1, and the ratio of X1 and Y1 is more than or equal to about 2.Second unit size sram cell has Y-direction spacing Y2 and X-direction spacing X2, and the ratio of X2 and Y2 is more than or equal to about 3.The ratio of X2 and X1 is greater than about 1.1.The size of X1, X2, Y1, Y2 is determined by the design rule of the semiconductor technology for using.In another embodiment, spacing Y1 approximates spacing Y2 greatly.
In said integrated circuit embodiment, write assist circuit has two states, a kind of for reading circulation, a kind of for writing circulation.In an additional embodiment, in reading cycle period, the voltage on unit positive voltage CVdd exports will be approximately equal to word line voltage.In write cycle period, in another embodiment, unit positive voltage CVdd is by lower than the voltage in wordline 50 to 300 millivolts.
In another embodiment, in said integrated circuit, configure the unit of the first and second SRAM array with row and column.The wordline of the transmission gate being connected to sram cell is configured abreast with row; And bit line to provide to unit CVdd positive voltage line parallel arrange and above the row of unit.In addition, the line of negative supply voltage CVss is provided will to be arranged in parallel with row and above sram cell to the pull-down transistor of sram cell.
In another embodiment, provide a kind of integrated circuit, comprise: processor, at least the first single-port SRAM array of the sram cell of first size formed by single fin FinFET transistor completely and comprise at least the second single-port SRAM array of sram cell of the second size that many fins FinFET transistor is formed, wherein, the sram cell of the second size forms the cache memory being connected to processor.
In embodiment of the method, first array of the sram cell formed by single fin FinFET transistor is respectively provided in integrated circuits, and in identical integrated circuit, provide the second array of the sram cell comprising many fins FinFET transistor respectively, and voltage control circuit is connected to the first array.In embodiment of the method, voltage control circuit provides unit positive supply CVdd, and it is reduced to the voltage lower than voltage in wordline during the write operation of the first array.In another embodiment, perform the method, and in the reading cycle period of the first array, unit positive supply CVdd is added to the voltage being greater than voltage in wordline at read operations.In another embodiment, a kind of method comprises: during the standby mode of the operation for the unit in the unit in the first array and the second array, and provide the unit positive supply CVdd of reduction, it is lower than input supply voltage.
The scope of the application is not limited to the specific illustrated embodiment of structure, method and the step described in instructions.Those skilled in the art from example embodiment open easily understand technique or the step that can utilize execution that is existing or that develop the after a while function substantially identical with describing corresponding embodiment herein or realize substantially identical result, and these embodiment can as the part of embodiment.Therefore, claims are used for comprising these techniques or step in their scope.
Claims (18)
1. an integrated circuit, comprising:
First single-port SRAM array of multiple first bit location, be configured in row and column, each first bit location has the y spacing of distance Y1 and the x spacing of distance X1, the ratio of X1 and Y1 is more than or equal to 2, each of multiple first bit location forms the 6TSRAM unit of single fin FinFET transistor, and each in described first bit location receives the first module positive voltage source from the first voltage control circuit; And
Second single-port SRAM array of multiple second unit, be configured in row and column, each second unit has the y spacing of distance Y2 and the x spacing of distance X2, the ratio of X2 and Y2 is more than or equal to 3, each of described multiple second unit comprises 6TSRAM unit further, described 6TSRAM unit comprises many fins FinFET transistor, and each in described second unit receives the second unit positive voltage source from the second voltage control circuit;
Wherein, the ratio of X2 and X1 is greater than 1.1, wherein, described first voltage control circuit is write assist circuit, it comprises the input being connected to peripheral Vdd power lead, the output being connected to described first module positive voltage source and enable input, described enable input has instruction and reads the reading state of circulation and the write state of instruction write circulation, and described first voltage control circuit provides different voltage for different indicating status.
2. integrated circuit according to claim 1, wherein, each of described first bit location comprises further:
Two phase inverters, cross connection is between memory node and complementary storage node, one of them phase inverter comprises the single fin FinFET be connected between described first module positive voltage source and described memory node and pulls up transistor, and the single fin FinFET pull-down transistor be connected between described memory node and unit negative voltage source, another phase inverter wherein comprises another the single fin FinFET be connected between described first module positive voltage source and described complementary storage node and pulls up transistor, and another the single fin FinFET pull-down transistor be connected between described complementary storage node and described unit negative voltage source, and
A pair transmission gate, one of them transmission gate is connected between bit line and described memory node, another transmission gate is wherein connected between paratope line and described complementary storage node, and each transmission gate comprises single fin FinFET transistor with the gate terminal being connected to wordline;
Wherein, described first module positive voltage source is connected to described first voltage control circuit; And
Wherein, each of described second unit comprises further:
Two phase inverters, cross connection is between memory node and complementary storage node, one of them phase inverter comprises the single fin FinFET be connected between second unit positive voltage source and described memory node and pulls up transistor, and the many fins FinFET pull-down transistor be connected between described memory node and unit negative voltage source, another phase inverter wherein comprises another the single fin FinFET be connected between second unit positive voltage source and described complementary storage node and pulls up transistor, and another the many fin FinFET pull-down transistor be connected between described complementary storage node and described unit negative voltage source, and
A pair transmission gate, one of them transmission gate is connected between bit line and described memory node, another transmission gate is wherein connected between paratope line and described complementary storage node, and each transmission gate comprises many fins FinFET transistor with the grid being connected to wordline further.
3. integrated circuit according to claim 1, wherein, in said write cycle period, described first voltage control circuit exports the voltage lower than the first module positive voltage source of described peripheral Vdd power lead.
4. integrated circuit according to claim 1, wherein, in described reading cycle period, described first voltage control circuit exports the voltage being equal to or greater than the first module positive voltage source of described peripheral Vdd power lead.
5. integrated circuit according to claim 1, wherein, described first voltage control circuit comprises standby mode circuit further, and the voltage exported lower than the first module positive voltage source of described peripheral Vdd power lead in response to standby mode input.
6. integrated circuit according to claim 1, wherein, in write cycle period, the word line voltage to unit equals described peripheral Vdd voltage, and described first voltage control circuit exports the voltage lower than the first module positive voltage source of described word line voltage at least 50 millivolts.
7. integrated circuit according to claim 1, wherein, described first single-port SRAM array has the voltage control circuit of each row for the first bit location.
8. integrated circuit according to claim 2, wherein, for each of described first bit location, describedly pull up transistor as the p-type transistor in n trap, and each of described first bit location comprises n trap web member further, described n trap web member and described first module positive voltage source electric isolution.
9. an integrated circuit, comprising:
First single-port SRAM array of multiple first bit location, be configured in row and column, each first bit location has the y spacing of distance Y1 and the x spacing of distance X1, the ratio of X1 and Y1 is more than or equal to 2, each of multiple first bit location forms the 6TSRAM unit of single fin FinFET transistor, and each of described first bit location receives the first module positive voltage source from the first voltage control circuit; And
Second single-port SRAM array of multiple second unit, be configured in row and column, each second unit has the y spacing of distance Y2 and the x spacing of distance X2, the ratio of X2 and Y2 is more than or equal to 3, each of described multiple second unit comprises 6TSRAM unit further, described 6TSRAM unit comprises many fins FinFET transistor, and each of described second unit receives the second unit positive voltage source from predetermined Vdd voltage source;
Wherein, the ratio of X2 and X1 is greater than 1.1, wherein, described first voltage control circuit comprises the voltage input node being connected to the input of Vdd power supply, the output being connected to described first module positive voltage source and enable input further, described enable input has the waiting status that the reading state of circulation, the write state indicating write circulation and instruction standby mode are read in instruction, further, described first voltage control circuit provides different voltage for different indicating status.
10. integrated circuit according to claim 9, wherein, each of described first bit location comprises further:
Two phase inverters, cross connection is between memory node and complementary storage node, one of them phase inverter comprises the single fin FinFET be connected between described first module positive voltage source and described memory node and pulls up transistor, and the single fin FinFET pull-down transistor be connected between described memory node and unit negative voltage source, another phase inverter wherein comprises another the single fin FinFET be connected between described first module positive voltage source and described complementary storage node and pulls up transistor, and another the single fin FinFET pull-down transistor be connected between described complementary storage node and described unit negative voltage source, and
A pair transmission gate, one of them transmission gate is connected between bit line and described memory node, another transmission gate is wherein connected between paratope line and described complementary storage node, and each transmission gate comprises single fin FinFET transistor with the gate terminal being connected to wordline;
Wherein, each of described second unit comprises further: two phase inverters, cross connection is between memory node and complementary storage node, one of them phase inverter comprises the single fin FinFET be connected between second unit positive voltage source and described memory node and pulls up transistor, and the many fins FinFET pull-down transistor be connected between described memory node and unit negative voltage source, another phase inverter wherein comprises another the single fin FinFET be connected between second unit positive voltage source and described complementary storage node and pulls up transistor, and another the many fin FinFET pull-down transistor be connected between described complementary storage node and described unit negative voltage source,
And a pair transmission gate, one of them transmission gate is connected between bit line and described memory node, another transmission gate is wherein connected between paratope line and described complementary storage node, and each transmission gate comprises many fins FinFET transistor with the grid being connected to wordline further.
11. integrated circuit according to claim 9, wherein, in write cycle period, described first voltage control circuit exports the voltage of the first module positive voltage source lower than described Vdd power supply input.
12. integrated circuit according to claim 9, wherein, in reading cycle period, described first voltage control circuit exports the voltage of the first module positive voltage source being greater than the input of described Vdd power supply.
13. integrated circuit according to claim 10, wherein, in write cycle period, described wordline is in the voltage equaling the input of described Vdd power supply, and described first voltage control circuit exports the voltage lower than described word line voltage 50 millivolts to 400 millivolts.
14. integrated circuit according to claim 9, comprise: Three S's array ram further, and described Three S's array ram comprises multiple 3rd size bit location, and each in described 3rd size bit location comprises:
Two cross-coupled inverter, for storing data at memory node and complementary storage node place, one of them cross-coupled inverter comprises the p-type list fin FinFET be connected between described first module positive voltage source and described memory node and pulls up transistor, and the N-shaped list fin FinFET pull-down transistor be connected between described memory node and first module negative voltage source, another phase inverter wherein comprises another p-type list fin FinFET be connected between described first module positive voltage source and described complementary storage node and pulls up transistor, and another N-shaped list fin FinFET pull-down transistor be connected between described complementary storage node and described first module negative voltage source, and
Two write transmission gates, each comprises single fin FinFET transistor with the grid being connected to wordline, and one of them write transmission gate is connected between write bit line and described memory node, another write transmission gate is wherein connected between complementary write bit line and described complementary storage node; And
Read port, comprises and is connected in series in reading transmission gate between reading bit line and second unit negative supply voltage and reads pull-down transistor, and each in described reading transmission gate and described reading pull-down transistor comprises many fins FinFET.
15. 1 kinds of methods forming integrated circuit, comprising:
First single-port SRAM array is set on the integrated, described first single-port SRAM array comprises further: multiple first size bit location, each in described multiple first size bit location comprises the cross-coupled inverter pair for storing data on memory node and complementary storage node, and each of described phase inverter centering comprises single fin FinFET pull-up device and single fin FinFET pull-down; And a pair transmission gate, one of them transmission gate is connected between bit line and described memory node, another transmission gate is wherein connected between paratope line and described complementary storage node, each in described transmission gate comprises single fin FinFET with the grid being connected to wordline, and the first voltage control circuit exports first module positive voltage source to described first size bit location;
Described integrated circuit arranges the second single-port SRAM array, described second single-port SRAM array comprises multiple second size bit location, each comprises: for storing the cross-coupled inverter pair of data on memory node and complementary storage node, and each phase inverter is to comprising single fin FinFET pull-up device and many fins FinFET pull-down; And a pair transmission gate, one of them transmission gate is connected between bit line and described memory node, another transmission gate is wherein connected between paratope line and described complementary storage node, each in described transmission gate comprises many fins FinFET with the grid being connected to wordline, and the second voltage control circuit exports second unit positive voltage source to described second size bit location;
Described first voltage control circuit and described second voltage control circuit are connected to peripheral voltage Vdd, wherein, described first voltage control circuit is write assist circuit, it comprises the power lead input being connected to described peripheral voltage Vdd, be connected to the output of described first module positive voltage source and enable input, described enable input has instruction and reads the reading state of circulation and the write state of instruction write circulation; And
Operate described first voltage control circuit, to change described first module positive voltage source for different indicating status during institute's selection operation.
16. methods according to claim 15, comprise: further during write operation, operate described first voltage control circuit, described first module positive voltage source to be reduced to the voltage lower than described peripheral voltage Vdd.
17. methods according to claim 15, comprise: further at read operations, operate described first voltage control circuit, to export the first module positive voltage source being equal to or greater than described peripheral voltage Vdd.
18. methods according to claim 15, comprise further: waiting period to be operated, operate described first voltage control circuit and described second voltage control circuit, to reduce described first module positive voltage source and described second unit positive voltage source.
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| US13/312,810 US8693235B2 (en) | 2011-12-06 | 2011-12-06 | Methods and apparatus for finFET SRAM arrays in integrated circuits |
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| CN103151070B true CN103151070B (en) | 2016-02-10 |
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| CN103151070A (en) | 2013-06-12 |
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| KR101402264B1 (en) | 2014-06-02 |
| US20150029785A1 (en) | 2015-01-29 |
| US9659634B2 (en) | 2017-05-23 |
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