CN102916048A - Junctionless silicon nanowire transistor based on bulk-silicon material and method for manufacturing junctionless silicon nanowire transistor - Google Patents
Junctionless silicon nanowire transistor based on bulk-silicon material and method for manufacturing junctionless silicon nanowire transistor Download PDFInfo
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- CN102916048A CN102916048A CN2012104086178A CN201210408617A CN102916048A CN 102916048 A CN102916048 A CN 102916048A CN 2012104086178 A CN2012104086178 A CN 2012104086178A CN 201210408617 A CN201210408617 A CN 201210408617A CN 102916048 A CN102916048 A CN 102916048A
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Abstract
The invention discloses a junctionless silicon nanowire transistor based on a bulk-silicon material and a method for manufacturing the junctionless silicon nanowire transistor. The junctionless silicon nanowire transistor comprises a bulk-silicon substrate, a polycrystalline grid, a drain electrode, a source electrode and a grid electrode, a P-type doped layer or an N-type doped layer is manufactured on the bulk-silicon substrate, an N-type doped layer or a P-type doped layer with a doping type opposite to the first P-type doped layer or first the N-type doped layer is manufactured on the first P-type doped layer or the first N-type doped layer, and a PN junction is formed by the different types of doped layers and realizes an electric isolation effect; a source region, a drain region and a silicon nanowire are manufactured on the second N-type doped layer or the second P-type doped layer, and the source region and the drain region are connected with each other by the silicon nanowire to form conducting channels; an insulating dielectric layer is manufactured on the surface of the integral silicon nanowire, the surface of the source region and the surface of the drain region; the polycrystalline grid is manufactured between the source region and the drain region and completely wraps the silicon nanowire; the drain electrode is manufactured on the drain region of silicon; the source electrode is manufactured on the source region of the silicon; and the grid electrode is manufactured on the polycrystalline grid. The junctionless silicon nanowire transistor and the method have the advantage that the junctionless silicon nanowire transistor can be manufactured on the bulk-silicon substrate.
Description
Technical field
The present invention relates to the semiconductor device manufacture technology field, be specifically related to a kind of nothing based on the body silicon materials and tie silicon nano line transistor and preparation method thereof.
Background technology
Along with the continuous progress of ic manufacturing technology, current metal-oxide semiconductor fieldeffect transistor (MOSFET) technology node has entered 22nm, and the device physics grid are long less than 20nm.Follow device size to continue to dwindle, its matter of utmost importance that faces is to be subjected to the impact of short-channel effect day by day serious.
Silicon nano line transistor is because controlling raceway grooves from a plurality of directions, and therefore energy establishment short-channel effect is expected to solve the day by day serious problem of impact that is subjected to short-channel effect, makes device size can be continued to reduce.But for traditional inversion mode field-effect transistor, channel region is different from the source-drain area doping type, when device grid length is reduced to the 10nm magnitude, to in the several nanometers in raceway groove two ends, realize the sudden change of doping content and doping type, realize very high doping content gradient, brought huge challenge for ion implantation technology and subsequent annealing, whole device preparation technology heat budget is low, the device preparation cost is high, and difficulty is large.
Along with the continuous progress of semiconductor technology, the channel silicon thickness of MOSFET can be realized 10nm even less, more and more becomes the focus of research without knot (Junctionless) silicon nano line transistor.All realize unified heavy doping without knot silicon nano line transistor channel region and source-drain area, can by the shutoff that entirely exhausts the realization device of channel region, can realize very high current on/off ratio.There is not the problem of high doping content gradient in its device technology preparation, and device preparation technology and traditional Bulk CMOS process compatible, and device preparation technology is simple, can realize the field-effect transistor of smaller szie when reducing process costs.Present many seminar successfully realize on the silicon on the insulator (SOI) substrate without the knot silicon nano line transistor, can obtain even better performance comparable with traditional inversion mode field-effect transistor, have very much researching value, but there is not yet report based on the nothing knot silicon nano line transistor of body silicon.
Summary of the invention
The technical problem that (one) will solve
In view of this, main purpose of the present invention is to provide a kind of nothing based on the body silicon materials to tie silicon nano line transistor and preparation method thereof, to realize without the knot silicon nano line transistor at the body silicon substrate.
(2) technical scheme
For achieving the above object, the invention provides a kind of nothing knot silicon nano line transistor based on the body silicon materials, comprising:
The one silicon substrate;
One first doped layer, this first doped layer is formed at the top of this body silicon substrate by Implantation, and the doping type of this first doped layer is P type or N-type;
One second doped layer, this second doped layer is formed at the top of this body silicon substrate by Implantation, and is positioned on this first doped layer, and the doping type of this second doped layer is opposite with the doping type of this first doped layer;
One source region, a drain region and a silicon nanowires, this source region, drain region and silicon nanowires are made on this second doped layer;
One insulating medium layer, this insulating medium layer are made in the surface in this silicon nanowires and source region, drain region;
One polysilicon grizzly bar, this polysilicon grizzly bar is made between this source region and the drain region, and wraps up this silicon nanowires fully;
One drain electrode, this drain electrode are made on this drain region;
One source electrode, this source electrode fabrication is on this source region; And
One gate electrode, this gate electrode are made on this polysilicon grizzly bar.
For achieving the above object, the present invention also provides a kind of preparation method without the knot silicon nano line transistor based on the body silicon materials, comprising:
Step 1: adopt the Implantation mode that the body silicon substrate is mixed from the body surface of silicon, doping type is N-type or P type, then carries out quick thermal annealing process;
Step 2: again adopt the Implantation mode that the body silicon substrate is mixed from the body surface of silicon, doping type is P type or N-type, then carries out quick thermal annealing process;
Step 3: adopt low-pressure chemical vapor deposition to cover one deck silicon nitride hard mask in the body surface of silicon;
Step 4: by photoetching and silicon nitride etch, define source-drain area in the body surface of silicon, and expose channel region silicon;
Step 5: by thermal oxidation, the channel silicon Surface Creation SiO that is exposing
2, source region and drain region are not oxidized under the stopping of silicon nitride hard mask, and the silicon of oxidation consumption channel surface floats the SiO that generates except oxidation
2, the concavity structure in formation source region, channel region, drain region;
Step 6: define the channel region silicon nanowires by electron beam lithography and silicon inductively coupled plasma (ICP) etching;
Step 7: by thermal oxidation, generate SiO at surface of silicon nanowires
2, thermal oxidation reduces the cross sectional dimensions of silicon nanowires to the consumption of silicon;
Step 8: adopt phosphoric acid solution to remove the silicon chip surface silicon nitride hard mask;
Step 9: by thermal oxidation or chemical vapour deposition (CVD) in the source region, the superficial growth insulating medium layer of drain region and silicon nanowires;
Step 10: cover polycrystalline silicon grid layer at insulating medium layer by chemical vapour deposition (CVD);
Step 11: by photoetching be etched in and define the polysilicon grizzly bar on the conductive material layer;
Step 12: on source region, drain region and polysilicon grizzly bar, make respectively source electrode, drain electrode and gate electrode, finish the preparation of device.
(3) beneficial effect
Can find out that from technique scheme the present invention has following beneficial effect:
(1) nothing based on the body silicon materials provided by the invention is tied silicon nano line transistor and preparation method thereof, consist of the effect that PN junction plays electric isolation by introducing dissimilar doped layers, can realize without the knot silicon nano line transistor at the body silicon substrate, can excellent when significantly reducing the device preparation cost without the knot silicon nano line transistor device.
(2) nothing based on the body silicon materials provided by the invention is tied silicon nano line transistor and preparation method thereof, can realize thicker effective source-drain area by the junction depth of control Implantation, do not need extra source-drain area growing epitaxial silicon, can realize little source-drain contact resistance.
(3) provided by the invention based on the body silicon materials without knot silicon nano line transistor and preparation method thereof, can control effective silicon thickness of channel region by partial thermal oxidation attenuate mode, can realize the preparation without the knot silicon nano line transistor.
(4) nothing based on the body silicon materials provided by the invention is tied silicon nano line transistor and preparation method thereof, device preparation technology is simple, compatible with the traditional cmos bulk silicon technological, after realizing the isolation of single transistor on the body silicon substrate by shallow grooved-isolation technique, just can realize the integrated of cmos circuit.
Description of drawings
For further specifying technology contents of the present invention, be described in detail as follows with accompanying drawing in conjunction with the embodiments, wherein:
Fig. 1, Fig. 2 are the schematic three dimensional views without the knot silicon nano line transistor based on the body silicon materials provided by the invention, wherein, for making designed structure clearer, have specially exposed part silicon nanowires 12 in Fig. 2;
Fig. 3 is that the nothing knot silicon nano line transistor based on the body silicon materials provided by the invention consists of the PN junction schematic diagram by introducing dissimilar doped layers; Wherein Fig. 3 A is N-type without knot silicon nano line transistor schematic diagram, and Fig. 3 B is that the P type is without knot silicon nano line transistor schematic diagram;
Fig. 4 is that low-pressure chemical vapor deposition is at the hard mask 8 rear schematic diagrames of silicon chip surface grown silicon nitride;
After Fig. 5 is photoetching and etch silicon nitride, expose channel silicon 11 schematic diagrames;
Fig. 6 is the SiO by the silicon channel region is carried out thermal oxidation and floats the silica removal Surface Creation
2Rear in the source region 4, the concavity structural representation that forms of channel region 11, drain region 5;
Fig. 7 is schematic diagram after electron beam lithography and silicon ICP etching define channel region silicon nanowires 12 and remove the silicon chip surface silicon nitride hard mask;
Fig. 8 for by thermal oxidation or chemical vapour deposition (CVD) behind the superficial growth insulating medium layer 15 in source region 4, silicon nanowires 12 and drain region 5, along the profile of A-A '.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
See also Fig. 1 to shown in Figure 6, the nothing knot silicon nano line transistor based on the body silicon materials provided by the invention comprises: one silicon substrate 1; One first doped layer 2, this first doped layer 2 is formed at the top of this body silicon substrate 1 by Implantation, and the doping type of this first doped layer 2 is P type or N-type; One second doped layer 3, this second doped layer 3 is formed at the top of this body silicon substrate 1 by Implantation, and be positioned on this first doped layer 2, the doping type of this second doped layer 3 is opposite with the doping type of this first doped layer 2, and dissimilar doped layers consists of the effect that PN junction plays electric isolation; One source region 4, a drain region 5 and a silicon nanowires 12, this source region 4, drain region 5 and silicon nanowires 12 are made on this second doped layer 3; Silicon nanowires 12 connects source region 4 and consists of conducting channel with drain region 5; One insulating medium layer 15, this insulating medium layer 15 are made in the surface in this silicon nanowires 12 and source region 4, drain region 5; One polysilicon grizzly bar 13, this polysilicon grizzly bar 13 is made between this source region 4 and the drain region 5, and wraps up this silicon nanowires 12 fully; One drain electrode 7, this drain electrode 7 are made on this drain region 5; One source electrode 6, this source electrode 6 are made on this source region 4; And a gate electrode 14, this gate electrode 14 is made on this polysilicon grizzly bar 13.
Wherein, this first doped layer 2 consists of PN junction with this second doped layer 3 in this body silicon substrate inside, and this PN junction plays the effect of electric isolation.This first doped layer 2 adopts P type or N-type to mix in apart from this body silicon substrate 1 upper surface 1-2 μ m, and doping content is 10
15-10
17Cm
-3This second doped layer 3 adopts N-type or P type to mix in apart from this body silicon substrate 1 upper surface 50-400nm, and doping content is 10
19-10
20Cm
-3, and the doping type of this second doped layer 3 is opposite with the doping type of this first doped layer 2.This silicon nanowires 12 connects this source region 4 and consists of conducting channel with drain region 5.This source region 4, drain region 5 and connection source region 4 are same doping type with this silicon nanowires 12 in drain region 5.The material that this insulating medium layer 15 adopts is SiO
2, nitrogen oxide, HfO
2, Si
3N
4, ZrO
2, Ta
2O
5, BST or PZT.
See also Fig. 3 to shown in Figure 8, a kind of preparation method without the accurate nano-wire transistor of knot based on body silicon provided by the invention comprises the steps:
Step 1: with reference to figure 3, select body silicon substrate 1, by Implantation mixed in body silicon substrate 1 surface, after injecting under 1000 ℃ of temperature quick thermal annealing process 10 seconds, the activator impurity ion.Doping type is N-type or P type, and doping content is 10
15-10
17Cm
-3, the Implantation junction depth is 1-2 μ m; Obtain the first doped layer 2 of N-type or P type;
Step 2: with reference to figure 3, again by Implantation mixed in body silicon substrate 1 surface, after injecting under 1000 ℃ of temperature quick thermal annealing process 10 seconds, the activator impurity ion.Doping type is opposite with doping type in the step 1, and doping content is 10
19-10
20Cm
-3, the Implantation junction depth is 50-400nm; Obtain with step 1 in the second doped layer 3 of type opposite;
Step 3: with reference to figure 4, by low-pressure chemical vapor deposition in body silicon substrate 1 surface coverage one deck silicon nitride hard mask 8; Wherein the thickness of silicon nitride hard mask is 50-200nm.
Step 4: with reference to figure 5 and 6, by photoetching and silicon nitride etch, define device source region 4 and drain region 5, and expose channel region silicon 11;
Step 5: with reference to figure 6, by thermal oxidation, the channel silicon Surface Creation SiO that is exposing
2, source region and drain region are not oxidized under the stopping of silicon nitride hard mask, float the SiO that generates except oxidation
2, the concavity structure in formation source region 4, channel region 11, drain region 5; Select 900 ℃ of dry oxidations, oxidization time is decided according to the thickness of the silicon of required consumption, decides according to step 2 intermediate ion implantation concentration junction depth and need to consume channel silicon thickness, injects the little 30-100nm of junction depth than step 2 intermediate ion, also namely obtaining channel region 11 effective silicon thickness d is 30-100nm;
Step 6: with reference to figure 7, define channel region silicon nanowires 12 by electron beam lithography and inductively coupled plasma (ICP) etching, etching depth is 30-80nm, according to situation than the little 20-40nm of channel region 11 effective silicon thickness d in the step 5.Etching obtains silicon nanowires 12 and is 30-100nm, and width is also consistent with the effective silicon thickness d of channel region in the step 5;
Step 7: by thermal oxidation, at silicon nanowires 12 Surface Creation SiO
2, thermal oxidation reduces the cross sectional dimensions of silicon nanowires 12 to the consumption of silicon, and wherein the thickness of thermal oxidation consumption silicon can not be above the difference of effective silicon thickness and etching depth in the step 6.Choose 900 ℃ of dry oxidations 90 minutes, and float except the SiO that generates with 5% diluted hydrofluoric acid (DHF)
2, in removal process 6, introduce the size that reduces silicon nanowires in the etching injury, the width that obtains silicon nanowires is 10-30nm, thickness is 10-30nm.
Step 8: adopt phosphoric acid solution to remove silicon chip surface silicon nitride hard mask 9,10;
Step 9: with reference to figure 8, by thermal oxidation or chemical vapour deposition (CVD) in the source region 4, the superficial growth insulating medium layer 15 of drain region 5 and silicon nanowires 12; The material of insulating medium layer 15 is SiO
2, nitrogen oxide, HfO
2, Si
3N
4, ZrO
2, Ta
2O
5, BST or PZT;
Step 10: cover polysilicon layer at insulating medium layer 15 by chemical vapour deposition (CVD);
Step 11: by photoetching be etched in and define polysilicon grizzly bar 13 on the conductive material layer;
Step 12: on source region 4, drain region 5 and polysilicon grizzly bar 13, make respectively source electrode 6, drain electrode 7 and gate electrode 14, finish the preparation of device.
This nothing based on the body silicon materials provided by the invention is tied silicon nano line transistor and preparation method thereof, consists of the effect that PN junction plays electric isolation by introducing dissimilar doped layers, can realize without tying silicon nano line transistor at the body silicon substrate; In addition, this nothing knot silicon nano line transistor based on the body silicon materials provided by the invention, device preparation technology is simple, and is compatible with the conventional bulk silicon technology, is easy to realize the integrated of cmos circuit.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (15)
1. the nothing knot silicon nano line transistor based on the body silicon materials is characterized in that, comprising:
The one silicon substrate;
One first doped layer, this first doped layer is formed at the top of this body silicon substrate by Implantation, and the doping type of this first doped layer is P type or N-type;
One second doped layer, this second doped layer is formed at the top of this body silicon substrate by Implantation, and is positioned on this first doped layer, and the doping type of this second doped layer is opposite with the doping type of this first doped layer;
One source region, a drain region and a silicon nanowires, this source region, drain region and silicon nanowires are made on this second doped layer;
One insulating medium layer, this insulating medium layer are made in the surface in this silicon nanowires and source region, drain region;
One polysilicon grizzly bar, this polysilicon grizzly bar is made between this source region and the drain region, and wraps up this silicon nanowires fully;
One drain electrode, this drain electrode are made on this drain region;
One source electrode, this source electrode fabrication is on this source region; And
One gate electrode, this gate electrode are made on this polysilicon grizzly bar.
2. the nothing knot silicon nano line transistor based on the body silicon materials according to claim 1 is characterized in that this first doped layer and this second doped layer are at the inner formation of this body silicon substrate PN junction, and this PN junction plays the effect of electric isolation.
3. the nothing knot silicon nano line transistor based on the body silicon materials according to claim 1 is characterized in that this first doped layer adopts P type or N-type to mix in apart from this body silicon substrate upper surface 1-2 μ m, and doping content is 10
15-10
17Cm
-3
4. the nothing knot silicon nano line transistor based on the body silicon materials according to claim 3 is characterized in that this second doped layer adopts N-type or P type to mix in apart from this body silicon substrate upper surface 50-400nm, and doping content is 10
19-10
20Cm
-3, and the doping type of this second doped layer is opposite with the doping type of this first doped layer.
5. the nothing knot silicon nano line transistor based on the body silicon materials according to claim 1 is characterized in that this silicon nanowires in this source region, drain region and connection source region and drain region is same doping type.
6. the nothing knot silicon nano line transistor based on the body silicon materials according to claim 1 is characterized in that the surface of this silicon nanowires is manufactured with an insulating medium layer.
7. the nothing knot silicon nano line transistor based on the body silicon materials according to claim 1 is characterized in that the material that this insulating medium layer adopts is SiO
2, nitrogen oxide, HfO
2, Si
3N
4, ZrO
2, Ta
2O
5, BST or PZT.
8. the preparation method without the knot silicon nano line transistor based on the body silicon materials is characterized in that, comprising:
Step 1: adopt the Implantation mode that the body silicon substrate is mixed from the body surface of silicon, doping type is N-type or P type, then carries out quick thermal annealing process;
Step 2: again adopt the Implantation mode that the body silicon substrate is mixed from the body surface of silicon, doping type is P type or N-type, then carries out quick thermal annealing process;
Step 3: adopt low-pressure chemical vapor deposition to cover one deck silicon nitride hard mask in the body surface of silicon;
Step 4: by photoetching and silicon nitride etch, define source-drain area in the body surface of silicon, and expose channel region silicon;
Step 5: by thermal oxidation, the channel silicon Surface Creation SiO that is exposing
2, source region and drain region are not oxidized under the stopping of silicon nitride hard mask, and the silicon of oxidation consumption channel surface floats the SiO that generates except oxidation
2, the concavity structure in formation source region, channel region, drain region;
Step 6: define the channel region silicon nanowires by electron beam lithography and silicon inductively coupled plasma (ICP) etching;
Step 7: by thermal oxidation, generate SiO at surface of silicon nanowires
2, thermal oxidation reduces the cross sectional dimensions of silicon nanowires to the consumption of silicon;
Step 8: adopt phosphoric acid solution to remove the silicon chip surface silicon nitride hard mask;
Step 9: by thermal oxidation or chemical vapour deposition (CVD) in the source region, the superficial growth insulating medium layer of drain region and silicon nanowires;
Step 10: cover polycrystalline silicon grid layer at insulating medium layer by chemical vapour deposition (CVD);
Step 11: by photoetching be etched in and define the polysilicon grizzly bar on the conductive material layer;
Step 12: on source region, drain region and polysilicon grizzly bar, make respectively source electrode, drain electrode and gate electrode, finish the preparation of device.
9. the preparation method without the knot silicon nano line transistor based on the body silicon materials according to claim 8 is characterized in that described in the step 1 the body silicon substrate is mixed, doping content is 10
15-10
17Cm
-3, the Implantation junction depth is 1-2 μ m.
10. the preparation method without the knot silicon nano line transistor based on the body silicon materials according to claim 8 is characterized in that described in the step 2 the body silicon substrate is mixed, doping content is 10
19-10
20Cm
-3, the Implantation junction depth is 50-400nm.
11. the preparation method without the knot silicon nano line transistor based on the body silicon materials according to claim 8 is characterized in that the thickness of silicon nitride hard mask described in the step 3 is 50-200nm.
12. the preparation method without the knot silicon nano line transistor based on the body silicon materials according to claim 8 is characterized in that exposing channel region silicon length described in the step 4 is 50-1000nm.
13. the preparation method without the knot silicon nano line transistor based on the body silicon materials according to claim 8, it is characterized in that, the channel silicon thickness that thermal oxidation described in the step 5 consumes injects junction depth according to step 2 intermediate ion and decides, and injects the little 50-100nm of junction depth than step 2 intermediate ion.
14. the preparation method without the knot silicon nano line transistor based on the body silicon materials according to claim 8 is characterized in that the silicon nanowires width that defines described in the step 6 is 30-100nm, highly is 30-80nm.
15. the preparation method without the knot silicon nano line transistor based on the body silicon materials according to claim 8 is characterized in that the material of insulating medium layer described in the step 9 is SiO
2, nitrogen oxide, HfO
2, Si
3N
4, ZrO
2, Ta
2O
5, BST or PZT.
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