CN102842505B - Field-effect tube and field-effect tube manufacturing method - Google Patents
Field-effect tube and field-effect tube manufacturing method Download PDFInfo
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- CN102842505B CN102842505B CN201110166279.7A CN201110166279A CN102842505B CN 102842505 B CN102842505 B CN 102842505B CN 201110166279 A CN201110166279 A CN 201110166279A CN 102842505 B CN102842505 B CN 102842505B
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Abstract
The invention discloses a field-effect tube manufacturing method, to solve the problem that oxidation layers at some areas are slight thinner and are easy to be etched during a manufacturing process of a field-effect tube, and to meet the over-etching requirements during the manufacturing process of the field-effect tube. The method comprises the following steps: making a potential well on a substrate, and generating an N+region, a P+region and a gate region on the surfaces of a substrate region and a potential well region; generating first oxidation layers on the surfaces of the substrate region and the potential well region through a chemical vapor deposition process; etching the first oxidation layer on the surface of the gate region, and retaining the first oxidation layers on the surfaces of other regions except for the surface of the gate region; generating second oxidation layers on the surfaces of the substrate region and the potential well region after being etched; generating metal layers on the second oxidation layers; and etching the metal layers. The invention also discloses a system for realizing the method.
Description
Technical field
The present invention relates to semiconductor manufacturing and mechanical field, particularly a kind of field effect transistor and field effect transistor manufacture method.
Background technology
Manufacture the metal gate process (MG technique) of field effect transistor, when growth grid oxic horizon, due to the doping oxidation effect of semiconductor technology, the oxidated layer thickness grown out of N+ type doped region and P+ type doped region differs greatly, thick than P+ doped region of the thickness of N+ doped region, and the oxide layer grown out of P+ type doped region and the oxidated layer thickness in other regions close, as P well area (PW), N substrate region (NSUB), gate oxidation region etc.If Fig. 1 is field effect transistor schematic diagram in prior art.
For the metal gate process of thick grating oxide layer, because gate oxide is thicker, all region surface on chip have enough oxidated layer thickness, can resist the etching to metal.
But, for the metal gate process of thin gate oxide, because its gate oxide is thinner, if the oxide layer of some region surface is thinner, then due to too thin, and may be worn by quarter when carrying out metal etch.As the oxide layer in P+ region is carved the schematic diagram wearing rear field effect transistor by Fig. 2.If oxide layer was worn by quarter, directly can be carved into silicon substrate, this is unallowed in technique.
In order to solve the problem, a kind of method of current employing is, before growth grid oxic horizon, adopt the mode of chemical vapor deposition, the superficial growth layer of oxide layer (LPTEOS) in the first all regions of scene effect pipe, by etching, only leave the oxide layer of P+ doped region, and the oxide layer of other region surface is all etched away.During follow-up so again etching, just can ensure that P+ region is not etched and wear.This process is as shown in Fig. 3 A, Fig. 3 B, Fig. 3 C and Fig. 3 D.Wherein, Fig. 3 A is depicted as the schematic diagram of the field effect transistor after adopting chemical vapor deposition generation oxide layer, Fig. 3 B is depicted as except P+ doped region, the oxide layer in other region is all etched the schematic diagram of rear field effect transistor, Fig. 3 C is depicted as the schematic diagram of field effect transistor after growth grid oxic horizon, and Fig. 3 D is depicted as the schematic diagram carrying out field effect transistor after metal etch.
Although this method can ensure that the oxide layer of follow-up P+ doped region is enough thick and be unlikely to be carved to wear, also result in some problems:
1, at P+ doped region, oxide layer (LPTEOS) quality generated by chemical vapor deposition is comparatively loose, and the thermal oxide layer quality that other region is generated by thermal oxidation mode when growing grid oxic horizon is comparatively fine and close, then comparatively large to the etching speed difference of these two kinds of oxide layers, the etching speed to thermal oxide layer to be far longer than to the etching speed of LPTEOS.Ensure that etch period is identical, then the thickness of LPTEOS needs more a lot than the thermal oxidation thickness in other regions, and so just cause the difference in thickness of field effect transistor surface zones of different comparatively large, mutual step is too high, easily occurs metal residual when etching.
2, in some circuit design, N+ doped region and P+ doped region be not abut against together with, the oxide layer on both zone line surface equally can be very thin, also easily worn by quarter.
Summary of the invention
The embodiment of the present invention provides a kind of field effect transistor and field effect transistor manufacture method, for solving the partially thin problem of wearing that is easily etched of some zone oxidation layer in field effect transistor manufacture process, meets the over etching demand in field effect transistor manufacture process.
A kind of field effect transistor manufacture method, comprises the following steps:
Substrate makes potential well, and at substrate region and Surface Creation N+ region, potential well region, P+ region and area of grid;
By the process of chemical vapor deposition in described substrate zone field surface and described potential well region Surface Creation first oxide layer;
First oxide layer on described area of grid surface etched away, except area of grid surface, the first oxide layer of other region surface all retains;
Described substrate zone field surface after etching and described potential well region Surface Creation second oxide layer;
Described second oxide layer generates metal level;
Described metal level is etched.
A kind of field effect transistor, according to described method manufacture.
A kind of field effect transistor manufacturing system, comprising:
Producing device, for making potential well, and at substrate region and Surface Creation N+ region, potential well region, P+ region and area of grid on substrate;
First oxide layer generating apparatus, for the mode by chemical vapor deposition in described substrate zone field surface and described potential well region Surface Creation first oxide layer;
Etching device, for first oxide layer on described area of grid surface being etched away, except area of grid surface, the first oxide layer of other region surface all retains, and etches metal level;
Second oxide layer generating apparatus, for described substrate zone field surface after etching and described potential well region Surface Creation second oxide layer;
Metal level generating apparatus, for generating described metal level in described second oxide layer.
On substrate, potential well is made in the embodiment of the present invention, and at substrate region and Surface Creation N+ region, potential well region, P+ region and area of grid; By the process of chemical vapor deposition in described substrate zone field surface and described potential well region Surface Creation first oxide layer; First oxide layer on described area of grid surface etched away, except area of grid surface, the first oxide layer of other region surface all retains; Described substrate zone field surface after etching and described potential well region Surface Creation second oxide layer; Described second oxide layer generates metal level; Described metal level is etched.First the embodiment of the present invention by adopting the mode scene effect tube-surface of chemical vapor deposition to generate one deck first oxide layer, on all regions, the second oxide layer is generated again after first oxide layer in other region except area of grid all being etched, thus make the oxide layer in each region enough thick and be unlikely to be etched to wear, and the oxidated layer thickness difference in each region is not too large, be conducive to again etching.
Accompanying drawing explanation
Fig. 1 is field effect transistor schematic diagram in prior art;
The oxide layer in P+ region is carved the schematic diagram wearing rear field effect transistor in prior art by Fig. 2;
Fig. 3 A is the schematic diagram of the field effect transistor after adopting chemical vapor deposition generation oxide layer in prior art;
Fig. 3 B is in prior art except P+ doped region, the oxide layer in other region is all etched the schematic diagram of rear field effect transistor;
Fig. 3 C is the schematic diagram growing field effect transistor after grid oxic horizon in prior art;
Fig. 3 D is the schematic diagram carrying out field effect transistor after metal etch in prior art;
Fig. 4 is the main method flow chart of field effect pipe manufacturer in the embodiment of the present invention;
Fig. 5 A is the field effect transistor schematic diagram after generating the first oxide layer in the embodiment of the present invention;
Fig. 5 B is the schematic diagram in the embodiment of the present invention, first oxide layer on area of grid surface being etched away rear field effect transistor;
Fig. 5 C is the schematic diagram generating field effect transistor after the second oxide layer in the embodiment of the present invention;
Fig. 5 D is the schematic diagram generating field effect transistor after metal level in the embodiment of the present invention;
Fig. 5 E is the schematic diagram in the embodiment of the present invention, metal level being etched to rear field effect transistor;
Fig. 6 is the primary structure figure of field effect pipe manufacturer system in the embodiment of the present invention.
Embodiment
On substrate, potential well is made in the embodiment of the present invention, and at substrate region and Surface Creation N+ region, potential well region, P+ region and area of grid; By the process of chemical vapor deposition in described substrate zone field surface and described potential well region Surface Creation first oxide layer; First oxide layer on described area of grid surface etched away, except area of grid surface, the first oxide layer of other region surface all retains; Described substrate zone field surface after etching and described potential well region Surface Creation second oxide layer; Described second oxide layer generates metal level; Described metal level is etched.First the embodiment of the present invention by adopting the mode scene effect tube-surface of chemical vapor deposition to generate one deck first oxide layer, on all regions, the second oxide layer is generated again after first oxide layer in other region except area of grid all being etched, thus make the oxide layer of area of grid enough thick and be unlikely to be etched to wear, and the oxidated layer thickness difference in each region is not too large, be conducive to again etching.
See Fig. 4, in the embodiment of the present invention, the main method flow process of field effect pipe manufacturer is as follows:
Step 401: make potential well on substrate, and at substrate region 4016 and Surface Creation N+ region, potential well region 4014, P+ region 4015 and area of grid 4016.First on substrate (SUB), produce PW (P type potential well), the method injecting ion can be adopted to form potential well.For N-type substrate in the embodiment of the present invention, therefore need to make P type potential well, if P type substrate, then can make N-type potential well, namely the type of substrate is contrary with the type of potential well.If by the non-PW region that channel region is selected in substrate region, P type field effect transistor can be produced, if selected channel region in PW region, then N-type field effect transistor can be produced.(the region formed after namely injecting N-type ion, N+ region is produced at substrate surface (comprising P type potential well surface), described N-type ion can be phosphonium ion), P+ region (region namely formed after implanting p-type ion, described P type ion can be boron ion).
Step 402: by the mode of chemical vapor deposition in surface, described substrate region 4016 and described potential well region Surface Creation first oxide layer 4011.Adopt the mode of chemical vapor deposition, substrate surface (comprising P type potential well surface) after generating N+ region, P+ region generates the first oxide layer 4011, this first oxide layer 4011 can be described as LPTEOS, namely utilize the oxide layer that low-pressure chemical vapor phase deposition mode grows, its main component is silicon dioxide.Be the field effect transistor schematic diagram after generation first oxide layer 4011 as shown in Figure 5A.
Chemical vapor deposition (CVD), is one or more compounds of the element containing formation oxide layer or elementary gas supply substrate, generates required oxide layer by gas phase action or at on-chip chemical reaction.The feature of chemical vapor deposition is: can deposit all kinds of film; Film forming speed is fast; Plated film diffractive good; Residual stress is little, good crystallinity; Film purity is high; Obtain level and smooth deposition surface; Radiation damage is low.
Low-pressure chemical vapor phase deposition is basic with atmospheric pressure cvd, for improving the method that the oxide thickness and relative impedances value that generate and production are created.Gas for passing in reative cell containing Si (silicon) element, O (oxygen) element in the embodiment of the present invention, in surface, substrate region 4016 and potential well region Surface Creation first oxide layer 4011 after gas decomposes.Principal character is: (1) makes the mean free path of reacting gas and gas carrier and diffusion constant become large because reative cell internal pressure is reduced to 10-1000Pa, therefore, the oxide thickness that substrate generates and relative impedances distribution can be greatly improved, and also can reduce the consumption of reacting gas; (2) reative cell becomes the diffusion type of furnace, and temperature controls comparatively easy, and device can also simplify.
Can be decomposed by the gas containing Si (silicon), O (oxygen) in the embodiment of the present invention, generate the first oxide layer 4011 that main component is silicon dioxide, cover field effect transistor surface.The quality of this LPTEOS is relative to comparatively loose the oxide layer that thermal oxidation generates, and the etch period of needs is shorter.
Step 403: first oxide layer 4011 on described area of grid 4012 surface etched away, except area of grid 4012 surface, the first oxide layer 4011 of other region surface all retains.Only the first oxide layer 4011 of area of grid 4012 surface coverage is etched away, retain the first oxide layer 4011 that other region surface covers.Other region can comprise N+ region 4014, P+ region 4015, substrate region 4016 etc.As shown in Figure 5 B for only first oxide layer 4011 on area of grid 4012 surface being etched away the schematic diagram of rear field effect transistor.
Step 404: surface, described substrate region 4016 after etching and described potential well region Surface Creation second oxide layer 4013.The mode of thermal oxidation substrate region 4016 after etching main component that is surperficial and potential well region Surface Creation second oxide layer 4013, second oxide layer 4013 can be adopted can be silicon dioxide.When carrying out thermal oxidation, area of grid 4012 is exposed in oxygen, second oxide layer 4013 grows comparatively fast, but other region surface except area of grid 4012 is all coated with LPTEOS, oxygen will with LPTEO below silicon react, namely to react with the silicon covered by LPTEO, need through LPTEOS, the speed therefore generating the second oxide layer 4013 is slower.So the second oxide layer 4013 of area of grid 4012 grows comparatively fast, and the thickness of the second oxide layer 4013 is also thicker, and second oxide layer 4013 in other region except area of grid 4012 may be very thin.The speed growing oxide layer due to N+ region 4014 is slightly faster than P+ region, and therefore the thickness outline of the total oxide layer in possibility N+ region 4014 is thicker.Wherein, the thickness of total oxide layer is the thickness that the thickness of the first oxide layer 4011 adds the second oxide layer 4013.Be the schematic diagram of field effect transistor after generation second oxide layer 4013 as shown in Figure 5 C.
Thermal oxidation technology is also divided into two kinds: dry-oxygen oxidation and wet-oxygen oxidation.Its key reaction equation is as follows:
Si+2H2O → SiO2+2H2 wet-oxygen oxidation
Si+O2 → SiO2 dry-oxygen oxidation
Thermal oxidation is high-temperature technology, and high-quality silicon dioxide all generates at 800 DEG C-1200 DEG C, and its generating rate is extremely slow.Wherein wet-oxygen oxidation speed is higher than dry-oxygen oxidation.The second oxide layer 4013 in the embodiment of the present invention can adopt the mode of dry-oxygen oxidation to generate.
Step 405: generate metal level 4017 in described second oxide layer 4013.Wherein, described metal can be aluminium.As shown in Figure 5 D for generating the schematic diagram of the rear field effect transistor of metal level 4017.
Step 406: described metal level 4017 is etched.Second time etching is carried out on the surface of the field effect transistor after generating metal level 4017, is this time all etch the region that metal level 4017 covers.Except area of grid 4012, the thickness of total oxide layer in other region is thicker, also can not be etched and wear, and the difference of the thickness of total oxide layer in N+ region 4014 and P+ region 4015 is not too large, make the step between each region can not be too high, easy etching is clean, avoids metal residual.As shown in fig. 5e for etching the schematic diagram of rear field effect transistor to metal level 4017.Wherein, the schematic diagram after the metal level 4017 of subregion just etches by Fig. 5 E, actual carry out second time etching time be the region that metal level 4017 covers all will be etched, only retain gate metal.
See Fig. 6, in the embodiment of the present invention, field effect pipe manufacturer system comprises producing device 601, first oxide layer generating apparatus 602, etching device 603, second oxide layer generating apparatus 604 and metal level generating apparatus 605.
Producing device 601 for making potential well on substrate, and at substrate region 4016 and Surface Creation N+ region, potential well region 4014, P+ region 4015 and area of grid 4016.Producing device 601 can adopt the method injecting ion to form potential well.N-type ion is injected at substrate surface (comprising P type potential well surface), to generate N+ region 4014, described N-type ion can be phosphonium ion, at substrate surface (comprising P type potential well surface) implanting p-type ion, to generate P+ region 4015, described P type ion can be boron ion.
First oxide layer generating apparatus 602 is for passing through the mode of chemical vapor deposition in surface, described substrate region 4016 and described potential well region Surface Creation first oxide layer 4011.Can be in reative cell, pass into the gas containing Si (silicon) element, O (oxygen) element in the embodiment of the present invention, in surface, substrate region 4016 and potential well region Surface Creation first oxide layer 4011 after gas decomposes.
Etching device 603 is for etching away first oxide layer 4011 on described area of grid 4012 surface, and except area of grid 4012 surface, the first oxide layer 4011 of other region surface all retains, and etches metal level 4017.
Second oxide layer generating apparatus 604 is for surface, described substrate region 4016 after etching and described potential well region Surface Creation second oxide layer 4013.Second oxide layer generating apparatus 604 can adopt the mode of thermal oxidation substrate region 4016 after etching main component that is surperficial and potential well region Surface Creation second oxide layer 4013, second oxide layer 4013 can be silicon dioxide.In the embodiment of the present invention, the second oxide layer generating apparatus 604 can adopt the mode of dry-oxygen oxidation to generate the second oxide layer.
Metal level generating apparatus 605 for generating metal level 4017 in described second oxide layer 4013.
The embodiment of the present invention also provides a kind of field effect transistor, and the field effect transistor manufacture method manufacture adopting the embodiment of the present invention to provide forms, and wherein, described field effect transistor can be CMOS (CMOSFET pipe).Described field effect transistor can comprise N+ region 4014, P+ region 4015, area of grid 4012, substrate region 4016 etc.
On substrate, potential well is made in the embodiment of the present invention, and at substrate region 4016 and Surface Creation N+ region, potential well region 4014, P+ region 4015 and area of grid 4012; By the process of chemical vapor deposition in surface, described substrate region 4016 and described potential well region Surface Creation first oxide layer 4011; First oxide layer 4011 on described area of grid 4012 surface etched away, except area of grid 4012 surface, the first oxide layer 4011 of other region surface all retains; Surface, described substrate region 4016 after etching and described potential well region Surface Creation second oxide layer 4013; Described second oxide layer 4013 generates metal level 4017; Described metal level 4017 is etched.First the embodiment of the present invention by adopting the mode scene effect tube-surface of chemical vapor deposition to generate one deck first oxide layer 4011, on all regions, the second oxide layer 4013 is generated again after first oxide layer 4011 in other region except area of grid 4012 all being etched, thus make the oxide layer in each region enough thick and be unlikely to be etched to wear, and the oxidated layer thickness difference in each region is not too large, be conducive to carrying out metal etch, effectively can reduce metal residual.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a field effect transistor manufacture method, is characterized in that, comprises the following steps:
Substrate makes potential well, and at substrate region and Surface Creation N+ region, potential well region, P+ region and area of grid;
By the process of chemical vapor deposition in described substrate zone field surface and described potential well region Surface Creation first oxide layer;
First oxide layer on described area of grid surface etched away, except area of grid surface, the first oxide layer of other region surface all retains;
Described substrate zone field surface after etching and described potential well region Surface Creation second oxide layer;
Described second oxide layer generates metal level;
Described metal level is etched.
2. the method for claim 1, it is characterized in that, comprise in the step in substrate region and Surface Creation N+ region, potential well region and P+ region: inject N-type ion at described substrate surface, form N+ region, and at described substrate surface implanting p-type ion, form P+ region.
3. the method for claim 1, it is characterized in that, the step being generated the first oxide layer by the substrate zone field surface of process after generating N+ region and P+ region of chemical vapor deposition is comprised: in reative cell, pass into the gas containing element silicon and oxygen element, and the substrate zone field surface after gas decomposes after generating N+ region and P+ region generates described first oxide layer.
4. the method for claim 1, is characterized in that, the step that substrate zone field surface after etching generates the second oxide layer comprises: generate the second oxide layer by the mode substrate zone field surface after etching of thermal oxidation.
5. the method for claim 1, is characterized in that, comprises the step that described metal level etches: etch the described metal level that substrate zone field surface covers.
6. the method for claim 1, is characterized in that, described first oxide layer and the second oxide layer are silicon dioxide.
7. the method as described in claim 1 or 6, is characterized in that, described metal is aluminium.
8. a field effect transistor, is characterized in that, according to the method manufacture as described in claim 1-6 any one.
9. a field effect transistor manufacturing system, is characterized in that, comprising:
Producing device, for making potential well, and at substrate region and Surface Creation N+ region, potential well region, P+ region and area of grid on substrate;
First oxide layer generating apparatus, for the mode by chemical vapor deposition in described substrate zone field surface and described potential well region Surface Creation first oxide layer;
Etching device, for first oxide layer on described area of grid surface being etched away, except area of grid surface, the first oxide layer of other region surface all retains, and etches metal level;
Second oxide layer generating apparatus, for described substrate zone field surface after etching and described potential well region Surface Creation second oxide layer;
Metal level generating apparatus, for generating described metal level in described second oxide layer.
10. system as claimed in claim 9, it is characterized in that, described first oxide layer generating apparatus is used for the gas passed in reative cell containing element silicon and oxygen element, and the substrate zone field surface after gas decomposes after generating N+ region and P+ region generates described first oxide layer.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6310367B1 (en) * | 1999-02-22 | 2001-10-30 | Kabushiki Kaisha Toshiba | MOS transistor having a tensile-strained SI layer and a compressive-strained SI-GE layer |
| CN101621032A (en) * | 2008-07-02 | 2010-01-06 | 北大方正集团有限公司 | Method for realizing low-voltage aluminum gate process |
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| TW538500B (en) * | 2002-06-12 | 2003-06-21 | Nanya Technology Corp | Method of manufacturing gate of field effect transistor |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6310367B1 (en) * | 1999-02-22 | 2001-10-30 | Kabushiki Kaisha Toshiba | MOS transistor having a tensile-strained SI layer and a compressive-strained SI-GE layer |
| CN101621032A (en) * | 2008-07-02 | 2010-01-06 | 北大方正集团有限公司 | Method for realizing low-voltage aluminum gate process |
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Effective date of registration: 20220722 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |
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