CN102842505A - Field-effect tube and field-effect tube manufacturing method - Google Patents
Field-effect tube and field-effect tube manufacturing method Download PDFInfo
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- CN102842505A CN102842505A CN2011101662797A CN201110166279A CN102842505A CN 102842505 A CN102842505 A CN 102842505A CN 2011101662797 A CN2011101662797 A CN 2011101662797A CN 201110166279 A CN201110166279 A CN 201110166279A CN 102842505 A CN102842505 A CN 102842505A
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Abstract
The invention discloses a field-effect tube manufacturing method, to solve the problem that oxidation layers at some areas are slight thinner and are easy to be etched during a manufacturing process of a field-effect tube, and to meet the over-etching requirements during the manufacturing process of the field-effect tube. The method comprises the following steps: making a potential well on a substrate, and generating an N+region, a P+region and a gate region on the surfaces of a substrate region and a potential well region; generating first oxidation layers on the surfaces of the substrate region and the potential well region through a chemical vapor deposition process; etching the first oxidation layer on the surface of the gate region, and retaining the first oxidation layers on the surfaces of other regions except for the surface of the gate region; generating second oxidation layers on the surfaces of the substrate region and the potential well region after being etched; generating metal layers on the second oxidation layers; and etching the metal layers. The invention also discloses a system for realizing the method.
Description
Technical field
The present invention relates to semiconductor manufacturing and mechanical field, particularly a kind of FET and FET manufacturing approach.
Background technology
Make the metal gate process (MG technology) of FET; In the growth grid oxic horizon; Because the doping oxidation effect of semiconductor technology, the oxidated layer thickness that grows out of N+ type doped region and P+ type doped region differs greatly, and the thickness of N+ doped region is thicker than P+ doped region; And the oxide layer that grows out of P+ type doped region and other regional oxidated layer thickness are approaching, like P well area (PW), N area (NSUB), gate oxidation zone etc.Like Fig. 1 is FET sketch map in the prior art.
For the metal gate process of thick grating oxide layer, because gate oxide is thicker, all there are enough oxidated layer thickness on the All Ranges surface on the chip, can resist the etching to metal.
But, for the metal gate process of thin gate oxide, because its gate oxide is thinner, if the oxide layer of some region surface is thinner, then may be thin when carrying out metal etch owing to too, worn and carve.Carve the sketch map of wearing the back FET for the oxide layer that P+ is regional like Fig. 2.If oxide layer was worn by quarter, can directly be carved into silicon substrate, this is unallowed on technology.
In order to address the above problem; A kind of method that adopts at present is before the growth grid oxic horizon, to adopt the mode of chemical vapor deposition; Elder generation is in the superficial growth layer of oxide layer (LPTEOS) of FET All Ranges; Through etching, only stay the oxide layer of P+ doped region, and the oxide layer of other region surface is all etched away.During follow-up so again etching, just can guarantee that the P+ zone is not etched to wear.This process is shown in Fig. 3 A, Fig. 3 B, Fig. 3 C and Fig. 3 D.Wherein, Fig. 3 A is depicted as the sketch map of the FET after the employing chemical vapor deposition generation oxide layer; Fig. 3 B is depicted as except that the P+ doped region; The sketch map of FET after the equal etching of the oxide layer that other is regional, Fig. 3 C are depicted as the sketch map of FET behind the growth grid oxic horizon, and Fig. 3 D is depicted as the sketch map that carries out FET behind the metal etch.
Be unlikely to be carved to wear though this method can guarantee that the oxide layer of follow-up P+ doped region is enough thick, also caused some problems:
1, at the P+ doped region; Oxide layer (LPTEOS) quality that generates through chemical vapor deposition is comparatively loose; And other zone is comparatively fine and close through the thermal oxide layer quality that the thermal oxidation mode generates when the growth grid oxic horizon; Then the etching speed difference to these two kinds of oxide layers is bigger, will be far longer than the etching speed to thermal oxide layer to the etching speed of LPTEOS.Guarantee that etch period is identical, then the thickness of LPTEOS need be more a lot of than other regional thermal oxidation bed thickness, so just cause the difference in thickness of FET surface zones of different bigger, and step is too high each other, when etching, occurs metal residual easily.
2, in some circuit design, the N+ doped region does not abut against with the P+ doped region, and the oxide layer on the two zone line surface equally can be very thin, also worn by quarter easily.
Summary of the invention
The embodiment of the invention provides a kind of FET and FET manufacturing approach, is used for solving the thin partially problem that is prone to be etched and wears of some regional oxide layer of FET manufacture process, satisfies the over etching demand in the FET manufacture process.
A kind of FET manufacturing approach may further comprise the steps:
On substrate, make potential well, and generate the N+ zone at area and potential well area field surface, P+ is regional and area of grid;
Process through chemical vapor deposition generates first oxide layer on said area surface and said potential well area field surface;
First oxide layer on said area of grid surface is etched away, and first oxide layer of other region surface all keeps except that the area of grid surface;
Said area surface and said potential well area field surface after etching generate second oxide layer;
On said second oxide layer, generate metal level;
Said metal level is carried out etching.
A kind of FET is according to described method manufacturing.
A kind of FET manufacturing system comprises:
Producing device is used on substrate, making potential well, and generate the N+ zone at area and potential well area field surface, P+ is regional and area of grid;
The first oxide layer generating apparatus is used for generating first oxide layer through the mode of chemical vapor deposition on said area surface and said potential well area field surface;
Etching device is used for first oxide layer on said area of grid surface is etched away, and first oxide layer of other region surface all keeps except that the area of grid surface, and metal level is carried out etching;
The second oxide layer generating apparatus, the said area surface and the said potential well area field surface that are used for after etching generate second oxide layer;
The metal level generating apparatus is used on said second oxide layer, generating said metal level.
On substrate, make potential well in the embodiment of the invention, and generate the N+ zone at area and potential well area field surface, P+ is regional and area of grid; Process through chemical vapor deposition generates first oxide layer on said area surface and said potential well area field surface; First oxide layer on said area of grid surface is etched away, and first oxide layer of other region surface all keeps except that the area of grid surface; Said area surface and said potential well area field surface after etching generate second oxide layer; On said second oxide layer, generate metal level; Said metal level is carried out etching.The embodiment of the invention generates one deck first oxide layer through the mode that at first adopts chemical vapor deposition at the field effect tube-surface; To except that area of grid, on All Ranges, generate second oxide layer after other regional equal etching of first oxide layer again; Thereby make each regional oxide layer enough thick and be unlikely to be etched and wear; And each regional oxidated layer thickness difference is not too large, helps carrying out etching once more.
Description of drawings
Fig. 1 is a FET sketch map in the prior art;
Fig. 2 is for carving the sketch map of wearing the back FET with the oxide layer in P+ zone in the prior art;
Fig. 3 A generates the sketch map of the FET after the oxide layer for the available technology adopting chemical vapor deposition;
Fig. 3 B be in the prior art except that the P+ doped region, the sketch map of FET after the equal etching of the oxide layer that other is regional;
Fig. 3 C is the sketch map of FET behind the growth grid oxic horizon in the prior art;
Fig. 3 D is the sketch map that carries out FET behind the metal etch in the prior art;
Fig. 4 is the main method flow chart of field effect pipe manufacturer in the embodiment of the invention;
Fig. 5 A is the FET sketch map after generation first oxide layer in the embodiment of the invention;
Fig. 5 B is the sketch map that first oxide layer in the embodiment of the invention that area of grid is surperficial etches away the back FET;
Fig. 5 C is the sketch map that generates FET after second oxide layer in the embodiment of the invention;
Fig. 5 D is the sketch map that generates FET behind the metal level in the embodiment of the invention;
Fig. 5 E is the sketch map that in the embodiment of the invention metal level is carried out FET after the etching;
Fig. 6 is the primary structure figure of field effect pipe manufacturer system in the embodiment of the invention.
Embodiment
On substrate, make potential well in the embodiment of the invention, and generate the N+ zone at area and potential well area field surface, P+ is regional and area of grid; Process through chemical vapor deposition generates first oxide layer on said area surface and said potential well area field surface; First oxide layer on said area of grid surface is etched away, and first oxide layer of other region surface all keeps except that the area of grid surface; Said area surface and said potential well area field surface after etching generate second oxide layer; On said second oxide layer, generate metal level; Said metal level is carried out etching.The embodiment of the invention generates one deck first oxide layer through the mode that at first adopts chemical vapor deposition at the field effect tube-surface; To except that area of grid, on All Ranges, generate second oxide layer after other regional equal etching of first oxide layer again; Be unlikely to be etched thereby the oxide layer that makes area of grid is enough thick and wear; And each regional oxidated layer thickness difference is not too large, helps carrying out etching once more.
Referring to Fig. 4, the main method flow process of field effect pipe manufacturer is following in the embodiment of the invention:
Step 401: on substrate, make potential well, and generate N+ zone 4014, P+ zone 4015 and area of grid 4016 in area 4016 and potential well area field surface.At first on substrate (SUB), produce PW (P type potential well), can adopt the method for injecting ion to form potential well.Be example with N type substrate in the embodiment of the invention, therefore need to make P type potential well, if P type substrate then can be made N type potential well, i.e. the type opposite of the type of substrate and potential well.If channel region is chosen in the non-PW zone in the area, can produce P type FET, if channel region is chosen in the PW zone, then can produce N type FET.Produce N+ zone (promptly inject the zone that forms behind the N type ion, said N type ion can be a phosphonium ion), P+ zone (promptly inject the zone that forms behind the P type ion, said P type ion can be the boron ion) at substrate surface (comprising P type potential well surface).
Step 402: the mode through chemical vapor deposition generates first oxide layer 4011 on said area 4016 surfaces and said potential well area field surface.Adopt the mode of chemical vapor deposition; Substrate surface after, P+ regional at generation N+ is regional (comprising P type potential well surface) generates first oxide layer 4011; This first oxide layer 4011 can be described as LPTEOS; The oxide layer of promptly utilizing the low-pressure chemical vapor phase deposition mode to grow, its main component are silicon dioxide.Be depicted as the FET sketch map that generates after first oxide layer 4011 like Fig. 5 A.
Chemical vapor deposition (CVD) is to supply with substrate to one or more compounds that contain the element that constitutes oxide layer or elementary gas, generates required oxide layer by gas phase action or at on-chip chemical reaction.The characteristics of chemical vapor deposition are: can deposit all kinds of films; Film forming speed is fast; The diffraction property of plated film is good; Little, the good crystallinity of residual stress; Film purity is high; Obtain level and smooth deposition surface; Radiation damage is low.
Low-pressure chemical vapor phase deposition is to be basic with the atmospheric pressure cvd, the method that oxide thickness that the desire improvement generates and relative resistance value and production are created.In the embodiment of the invention in reative cell, feeding the gas contain Si (silicon) element, O (oxygen) element, after the decomposing gas on area 4016 surfaces and the potential well area field surface generate first oxide layer 4011.Principal character is: (1) makes the mean free path of reacting gas and gas carrier and diffusion constant become big owing to the reative cell internal pressure is reduced to 10-1000Pa; Therefore; Oxide thickness that generates on the substrate and relative distribution of impedance can be greatly improved, and also can reduce the consumption of reacting gas; (2) reative cell becomes the diffusion type of furnace, and temperature control is comparatively easy, and device can also be simplified.
Can be through containing the decomposing gas of Si (silicon), O (oxygen) in the embodiment of the invention, generating main component be first oxide layer 4011 of silicon dioxide, covers the FET surface.The oxide layer that the quality relatively hot oxidation of this LPTEOS generates is comparatively loose, and the etch period that needs is shorter.
Step 403: first oxide layer 4011 on said area of grid 4012 surfaces is etched away, and first oxide layer 4011 of other region surface all keeps except that area of grid 4012 surfaces.Only first oxide layer 4011 with area of grid 4012 surface coverage etches away, and keeps first oxide layer 4011 that other region surface covers.Other zone can comprise N+ zone 4014, P+ zone 4015, area 4016 etc.Be depicted as the sketch map that only first oxide layer 4011 on area of grid 4012 surfaces is etched away the back FET like Fig. 5 B.
Step 404: said area 4016 surfaces and said potential well area field surface after etching generate second oxide layer 4013.The main component that area 4016 surfaces and the potential well area field surface of the mode that can adopt thermal oxidation after etching generates second oxide layer, 4013, the second oxide layers 4013 can be a silicon dioxide.When carrying out thermal oxidation; Area of grid 4012 is exposed in the oxygen, and 4013 growths of second oxide layer are very fast, but other region surface except that area of grid 4012 all is coated with LPTEOS; Oxygen will react by the silicon below LPTEO; Promptly will react with the silicon that is covered by LPTEO, need pass LPTEOS, the speed that therefore generates second oxide layer 4013 is slower.So second oxide layer, 4013 growths of area of grid 4012 are very fast, the thickness of second oxide layer 4013 is also thicker, and second oxide layer 4013 in other zone except that area of grid 4012 maybe be very thin.Because the speed of N+ zone 4014 growth oxide layers is faster slightly than P+ zone, therefore possibility N+ zone 4014 total thickness of oxide layer outlines are thicker.Wherein, total thickness of oxide layer is the thickness that the thickness of first oxide layer 4011 adds second oxide layer 4013.Be depicted as the sketch map that generates second oxide layer, 4013 back FETs like Fig. 5 C.
Thermal oxidation technology also is divided into two kinds: dry-oxygen oxidation and wet-oxygen oxidation.Its key reaction equation is following:
Si+2H2O → SiO2+2H2 wet-oxygen oxidation
Si+O2 → SiO2 dry-oxygen oxidation
Thermal oxidation is a high-temperature technology, and high-quality silicon dioxide all generates down at 800 ℃-1200 ℃, and its generating rate is extremely slow.Wherein wet-oxygen oxidation speed will be higher than dry-oxygen oxidation.Second oxide layer 4013 in the embodiment of the invention can adopt the mode of dry-oxygen oxidation to generate.
Step 405: on said second oxide layer 4013, generate metal level 4017.Wherein, said metal can be an aluminium.Be depicted as the sketch map that generates metal level 4017 back FETs like Fig. 5 D.
Step 406: said metal level 4017 is carried out etching.The etching second time is carried out on the surface of the FET after generating metal level 4017, this time is that metal level 4017 region covered are all carried out etching.Total thickness of oxide layer in other zone is thicker except that area of grid 4012; Also can not be etched and wear, and N+ zone 4014 is not too large with the difference of total thickness of oxide layer in P+ zone 4015, make the step between each zone can be too not high; Etching is clean easily, avoids metal residual.Be depicted as the sketch map that metal level 4017 is carried out FET after the etching like Fig. 5 E.Wherein, Fig. 5 E just carries out the sketch map after the etching with the metal level 4017 of subregion, and actual to carry out the second time be will metal level 4017 region covered all be carried out etching during etching, only keeps gate metal.
Referring to Fig. 6, field effect pipe manufacturer system comprises producing device 601, the first oxide layer generating apparatus 602, etching device 603, the second oxide layer generating apparatus 604 and metal level generating apparatus 605 in the embodiment of the invention.
Producing device 601 is used on substrate, making potential well, and generates N+ zone 4014, P+ zone 4015 and area of grid 4016 in area 4016 and potential well area field surface.Producing device 601 can adopt the method for injecting ion to form potential well.Inject N type ion at substrate surface (comprising P type potential well surface); To generate N+ zone 4014, said N type ion can be a phosphonium ion, injects P type ion at substrate surface (comprising P type potential well surface); To generate P+ zone 4015, said P type ion can be the boron ion.
The first oxide layer generating apparatus 602 is used for generating first oxide layer 4011 through the mode of chemical vapor deposition on said area 4016 surfaces and said potential well area field surface.Can be in reative cell, to feed the gas contain Si (silicon) element, O (oxygen) element in the embodiment of the invention, after the decomposing gas on area 4016 surfaces and the potential well area field surface generate first oxide layer 4011.
Said area 4016 surfaces and said potential well area field surface that the second oxide layer generating apparatus 604 is used for after etching generate second oxide layer 4013.The main component that area 4016 surfaces and the potential well area field surface of the mode that the second oxide layer generating apparatus 604 can adopt thermal oxidation after etching generates second oxide layer, 4013, the second oxide layers 4013 can be a silicon dioxide.The second oxide layer generating apparatus 604 can adopt the mode of dry-oxygen oxidation to generate second oxide layer in the embodiment of the invention.
Metal level generating apparatus 605 is used on said second oxide layer 4013, generating metal level 4017.
The embodiment of the invention also provides a kind of FET, adopts the FET manufacturing approach manufacturing that the embodiment of the invention provided to form, and wherein, said FET can be CMOS (a CMOSFET pipe).Said FET can comprise N+ zone 4014, P+ zone 4015, area of grid 4012, area 4016 etc.
On substrate, make potential well in the embodiment of the invention, and generate N+ zone 4014, P+ zone 4015 and area of grid 4012 in area 4016 and potential well area field surface; Process through chemical vapor deposition generates first oxide layer 4011 on said area 4016 surfaces and said potential well area field surface; First oxide layer 4011 on said area of grid 4012 surfaces is etched away, and first oxide layer 4011 of other region surface all keeps except that area of grid 4012 surfaces; Said area 4016 surfaces and said potential well area field surface after etching generate second oxide layer 4013; On said second oxide layer 4013, generate metal level 4017; Said metal level 4017 is carried out etching.The embodiment of the invention generates one deck first oxide layer 4011 through the mode that at first adopts chemical vapor deposition at the field effect tube-surface; To except that area of grid 4012, on All Ranges, generate second oxide layer 4013 after other regional first oxide layer, 4011 equal etchings again; Thereby make each regional oxide layer enough thick and be unlikely to be etched and wear; And each regional oxidated layer thickness difference is not too large, helps carrying out metal etch, can effectively reduce metal residual.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. a FET manufacturing approach is characterized in that, may further comprise the steps:
On substrate, make potential well, and generate the N+ zone at area and potential well area field surface, P+ is regional and area of grid;
Process through chemical vapor deposition generates first oxide layer on said area surface and said potential well area field surface;
First oxide layer on said area of grid surface is etched away, and first oxide layer of other region surface all keeps except that the area of grid surface;
Said area surface and said potential well area field surface after etching generate second oxide layer;
On said second oxide layer, generate metal level;
Said metal level is carried out etching.
2. the method for claim 1; It is characterized in that the step in area and potential well area field surface generation N+ zone and P+ zone comprises: inject N type ion at said substrate surface, form the N+ zone; And, form the P+ zone at said substrate surface injection P type ion.
3. the method for claim 1; It is characterized in that; The surperficial step that generates first oxide layer of the area of process after generating N+ zone and P+ zone through chemical vapor deposition comprises: in reative cell, feed the gas that contains element silicon and oxygen element, said first oxide layer of area surface generation after the decomposing gas after generating N+ zone and P+ zone.
4. the method for claim 1 is characterized in that, the step that generates second oxide layer on the surface of the area after the etching comprises: the area surface of mode after etching through thermal oxidation generates second oxide layer.
5. the method for claim 1 is characterized in that, the step of said metal level being carried out etching comprises: the said metal level to the area surface coverage carries out etching.
6. the method for claim 1 is characterized in that, said first oxide layer and second oxide layer are silicon dioxide.
7. like claim 1 or 6 described methods, it is characterized in that said metal is an aluminium.
8. a FET is characterized in that, according to like any described method manufacturing of claim 1-6.
9. a FET manufacturing system is characterized in that, comprising:
Producing device is used on substrate, making potential well, and generate the N+ zone at area and potential well area field surface, P+ is regional and area of grid;
The first oxide layer generating apparatus is used for generating first oxide layer through the mode of chemical vapor deposition on said area surface and said potential well area field surface;
Etching device is used for first oxide layer on said area of grid surface is etched away, and first oxide layer of other region surface all keeps except that the area of grid surface, and metal level is carried out etching;
The second oxide layer generating apparatus, the said area surface and the said potential well area field surface that are used for after etching generate second oxide layer;
The metal level generating apparatus is used on said second oxide layer, generating said metal level.
10. system as claimed in claim 9; It is characterized in that; The said first oxide layer generating apparatus is used in reative cell, feeding the gas that contains element silicon and oxygen element, and the area surface after the decomposing gas after generating N+ zone and P+ zone generates said first oxide layer.
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| CN201110166279.7A CN102842505B (en) | 2011-06-20 | 2011-06-20 | Field-effect tube and field-effect tube manufacturing method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6310367B1 (en) * | 1999-02-22 | 2001-10-30 | Kabushiki Kaisha Toshiba | MOS transistor having a tensile-strained SI layer and a compressive-strained SI-GE layer |
| US20030232285A1 (en) * | 2002-06-12 | 2003-12-18 | Nanya Technology Corporation | Manufacturing method of a MOSFET gate |
| CN101621032A (en) * | 2008-07-02 | 2010-01-06 | 北大方正集团有限公司 | Method for realizing low-voltage aluminum gate process |
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2011
- 2011-06-20 CN CN201110166279.7A patent/CN102842505B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6310367B1 (en) * | 1999-02-22 | 2001-10-30 | Kabushiki Kaisha Toshiba | MOS transistor having a tensile-strained SI layer and a compressive-strained SI-GE layer |
| US20030232285A1 (en) * | 2002-06-12 | 2003-12-18 | Nanya Technology Corporation | Manufacturing method of a MOSFET gate |
| CN101621032A (en) * | 2008-07-02 | 2010-01-06 | 北大方正集团有限公司 | Method for realizing low-voltage aluminum gate process |
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Effective date of registration: 20220722 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |
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