CN102651319A - Manufacturing method of transistor - Google Patents
Manufacturing method of transistor Download PDFInfo
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- CN102651319A CN102651319A CN2011100454161A CN201110045416A CN102651319A CN 102651319 A CN102651319 A CN 102651319A CN 2011100454161 A CN2011100454161 A CN 2011100454161A CN 201110045416 A CN201110045416 A CN 201110045416A CN 102651319 A CN102651319 A CN 102651319A
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Abstract
The invention discloses a manufacturing method of a transistor, which comprises that: a substrate is provided, the transistor is formed on the substrate, and the transistor comprises a grid electrode positioned on the substrate; a stop layer is covered on the transistor; a medium layer structure is covered on the stop layer; a first leveling process is carried out on the medium layer structure until the stop layer on the grid electrode is exposed; the stop layer on the grid electrode and the remaining medium layer structure are removed until the grid electrode is exposed to enable upper surfaces of the stop layer and the medium layer structure are below the upper surface of the grid electrode; a insulation material is deposited on the grid electrode, the stop layer and the medium layer structure to form an interlaminating medium layer; and a second leveling process is carried out on the interlaminating medium layer until the grid electrode is exposed. According to the manufacturing method, a bucktooth effect of the transistor can be avoided.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of transistorized manufacturing approach.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach arithmetic speed faster, bigger data storage amount and more function, and semiconductor chip develops to high integration direction more.And the integrated level of semiconductor chip is high more, and (CD, Critical Dimension) is more little for the characteristic size of semiconductor device.At present, in the very lagre scale integrated circuit (VLSIC), characteristic size has entered into tens scopes to the hundreds of nanometer.
For the semiconductor device of characteristic size less than 32nm, adopting the transistor of high-K metal grid is mainstream technology, with reference to figure 1～show with reference to figure 4 sketch map of prior art transistor fabrication process one embodiment.
At first, please refer to Fig. 1, on substrate 10, form a plurality of transistors; Said transistor comprises grid 14, surrounds the side wall of said grid 14, and said grid 14 is polysilicon dummy grids; At said grid 14 and side wall 15, and form barrier layer 11, first silicon oxide layer 12 and second silicon oxide layer 13 on the unlapped substrate 10 of transistor successively, wherein; The material on barrier layer 11 is a silicon nitride; First silicon oxide layer 12 is filled out ditch through the high depth ratio of high-aspect-ratio, and (High Aspect Ratio Polymer, HARP) technology formation have good filling characteristic owing to form silica through HARP technology; And since formed first silicon oxide layer 12 of HARP technology is follow-up can annealed technology, so formed first silicon oxide layer 12 of HARP technology is softer; Said second silicon oxide layer 13 forms through tetraethoxysilane (TEOS) mode.
Please refer to Fig. 2, remove body silica (Bulk OX) part through a CMP technology, in the present embodiment, a said CMP technology has been removed part second silicon oxide layer 13.
Continuation is with reference to figure 3; Remove the silica on grid 14 and the side wall 15 through the 2nd CMP technology; Particularly, said the 2nd CMP technology has been removed second silica 13 and part first silicon oxide layer 12, said the 2nd CMP technology with grid 14 for stopping layer; After the 2nd CMP technology, the flush of the silicon nitride and first silica 12.
Continuation is with reference to figure 4; Remove the silicon nitride on the grid 14 through the 3rd CMP technology, in the 3rd CMP technology, grinding agent (slurry) accumulates in the interface place on the barrier layer 11 of first silicon oxide layer 12 and silicon nitride material easily; Thereby the junction on first silicon oxide layer 12 and barrier layer 11 forms depression 17; Said depression 17 can influence successive process, and for example: the back extended meeting is carried out CMP technology to AL, in CMP technology; Aluminum can remain in the depression 17, also can cause problem that gate height reduces or the like simultaneously.This in said the 3rd CMP technology, the phenomenon that around grid, forms depression in the industry cycle is called as " long,sharp,protruding teeth effect (Fang Issue) ".
, publication number can find more manufacture methods in being the one Chinese patent application of CN101393894A about existing MOS transistor.
Become those skilled in the art's problem demanding prompt solution and how to solve " Fang Issue ".
Summary of the invention
The problem that the present invention solves provides a kind of transistorized manufacturing approach, reduces the influence of " Fang Issue ".
For addressing the above problem, the present invention provides a kind of transistorized manufacturing approach, comprising: substrate is provided, on said substrate, forms transistor, said transistor comprises the grid that is positioned on the substrate; Covering barrier layer on said transistor; Blanket dielectric layer structure on said barrier layer; Said dielectric layer structure is carried out first flatening process, until the barrier layer of exposing on the grid; Removal is positioned at barrier layer and the remaining dielectric layer structure on the grid, until exposing grid, makes the upper surface of barrier layer and dielectric layer structure all be positioned at the below of gate upper surface; Deposition of insulative material on grid, barrier layer and dielectric layer structure forms interlayer dielectric layer; Said interlayer dielectric layer is carried out second flatening process, until exposing grid.
Compared with prior art, the present invention has the following advantages: the silicon nitride as the barrier layer is positioned at the below of gate upper surface, and also is coated with oxide layer on the silicon nitride; Therefore, in second flatening process, can the intersection of silicon nitride and silica not ground, therefore can not form depression, thereby reduce " Fang Issue ", and then improve formed transistorized performance at the intersection of silicon nitride and silica.
Description of drawings
Fig. 1～Fig. 4 is the transistorized manufacture method cross-sectional view of prior art;
Fig. 5 is the schematic flow sheet of transistor fabrication process one execution mode of the present invention;
Fig. 6～Figure 12 is the formed transistorized cross-sectional view of transistor fabrication process one embodiment of the present invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth a lot of details in the following description so that make much of the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not received the restriction of following disclosed specific embodiment.
Described like background technology, the transistorized manufacturing approach of prior art can form depression around grid, thereby causes the decline of transistor performance.To the problems referred to above, inventor of the present invention has proposed a kind of transistorized manufacturing approach, please refer to the schematic flow sheet of transistor fabrication process of the present invention one execution mode shown in Figure 5.Said method roughly may further comprise the steps:
Step S1 provides substrate, on said substrate, forms transistor, and said transistor comprises the grid that is positioned on the substrate;
Step S2, covering barrier layer on said transistor;
Step S3, blanket dielectric layer structure on the barrier layer;
Step S4 carries out first flatening process to the dielectric layer structure, until the barrier layer of exposing on the grid;
Step S5 removes and to be positioned at barrier layer and the remaining dielectric layer structure on the grid, until exposing grid, makes the upper surface of barrier layer and dielectric layer structure all be positioned at the below of gate upper surface;
Step S6, deposition of insulative material on grid, barrier layer and dielectric layer structure forms interlayer dielectric layer;
Step S7 carries out second flatening process to said interlayer dielectric layer, until exposing grid.
Below in conjunction with concrete embodiment technical scheme of the present invention is carried out detailed explanation.For technical scheme of the present invention is described better, please refer to the transistor fabrication process cross-sectional view of the one embodiment of the invention of Fig. 6～shown in Figure 12.
At first, please refer to Fig. 6, execution in step S1 provides substrate 100, forms a plurality of MOS transistors on the said substrate 100, is formed with NMOS pipe, PMOS pipe on the substrate described in the present embodiment 100.Said metal-oxide-semiconductor comprises the side wall 108 on grid oxic horizon 107, grid 103, the said grid 103 of encirclement and grid oxic horizon 107 sidewalls that are positioned at successively on the substrate; Be formed at the source region (drain region) 102 on the grid 103 both sides substrates; Particularly, the thickness of grid described in the present embodiment 103 is in the scope of
.It is identical with prior art with technology on substrate 100, to form the employed material of metal-oxide-semiconductor, repeats no more at this.
Wherein, said substrate 100 can be monocrystalline silicon or SiGe; Also can be silicon-on-insulator (Siliconon insulator, SOI); Perhaps can also comprise it being other material, for example: III-V compounds of group such as GaAs.Said substrate 100 can also have certain isolation structure 101, is used to isolate NMOS pipe and PMOS pipe, and said isolation structure 101 can be isolated (LOCOS) from (STI) or local field oxidation for shallow trench isolation.
With reference to figure 7, execution in step S2, deposition of insulative material on the substrate 100 that nmos pass transistor, PMOS transistor and transistor expose, to form barrier layer 106, said barrier layer 106 is used for the layer that stops of subsequent planarization technology.
The material on barrier layer described in the present embodiment 106 is a silicon nitride, but the present invention is not restricted to this.Particularly, the thickness of said silicon nitride is in the scope of
.
With reference to figure 8, execution in step S3, deposition of insulative material on the basis on barrier layer 106 is to form the dielectric layer structure.
In the present embodiment; Said dielectric layer structure comprises first silicon oxide layer 109 and second silicon oxide layer 110 that is positioned at successively on the barrier layer 106; Wherein, Said first silicon oxide layer 109 for fill out through high depth ratio ditch (HighAspect Ratio Polymer, HARP) technology forms, second silicon oxide layer 110 forms through tetraethoxysilane (TEOS); Because the nmos pass transistor and the PMOS transistor that are positioned on the substrate 100 have certain height, the upper surface that therefore is covered in the dielectric layer structure on nmos pass transistor and the PMOS transistor is uneven.
The gross thickness of said first silicon oxide layer 109 and second silicon oxide layer 110 is in the scope of
.
Need to prove; In the present embodiment; Said dielectric layer structure comprises second silicon oxide layer 110 that formed first silicon oxide layer 109 of the HARP that is positioned on the barrier layer 106 and TEOS form, but the present invention is not restricted to this, and said dielectric layer structure can also include only the HARP that is positioned on the barrier layer 106 and form first silicon oxide layer 109; Can reduce processing step, economical with materials so on the one hand, and then reduce manufacturing cost; On the other hand, can also reduce follow-up difficulty of the dielectric layer structure being carried out planarization.
With reference to figure 9, execution in step S4 carries out first flatening process to the dielectric layer structure; Expose the barrier layer 106 on the grid 103, in the present embodiment, said first flatening process is removed second silicon oxide layer 110 earlier; Continue afterwards first silicon oxide layer 109 is carried out flatening process; Said first flatening process for stopping layer, stops flatening process with the barrier layer on the grid 103 106 when exposing barrier layer 106, thereby makes the flush on first silicon oxide layer 109 and barrier layer 106.
Particularly, in the present embodiment, said first flatening process is cmp (ChemicalMechanical Polishing, CMP) method.
With reference to Figure 10, execution in step S5 through first silicon oxide layer 109 is carried out etching with barrier layer 106, is positioned at barrier layer and remaining dielectric layer structure on the grid with removal, and then exposes grid 103, particularly, may further comprise the steps:
Carry out first etching, removal is positioned at first silicon oxide layer 109 on the grid;
Carry out second etching, be positioned at the part barrier layer 106 on the grid with removal.
After first etching and second etching, the upper surface that has exposed grid 103, the first silicon oxide layers 109 and barrier layer 106 all is positioned at the below of grid 103 upper surfaces.
In the present embodiment; The material on said barrier layer 106 is a silicon nitride; When first silicon oxide layer 109 is carried out first etching; The selection of 109 pairs of silicon nitrides of first silicon oxide layer ratio is greater than 2 in first etching; Make said first etching be primarily aimed at first silicon oxide layer 109, particularly, said first etching to the etched thickness of first silicon oxide layer 109 in the scope of
.
Silicon nitride compares greater than 15 the selection of grid 103 in second etching; Silicon nitride compares greater than 1 the selection of silica; To avoid the influence of second etching to grid 103; After second etching; Particularly, the flush of the upper surface on said barrier layer 106 and said first silicon oxide layer 109 and with the distance of grid 103 upper surfaces in the scope of
.
Particularly, said first etching and second etching can be to do to carve or wet the quarter.
With reference to Figure 11, execution in step S6 forms interlayer dielectric layer 111 on the upper surface of upper surface, barrier layer 106 and the dielectric layer structure of grid 103; In the present embodiment, on grid 103, barrier layer 106 and first silicon oxide layer 109, deposit TEOS, form the interlayer dielectric layer 111 of silica material, but the present invention is not restricted to this.
Need to prove that preferably, the thickness of said interlayer dielectric layer 111 needs the distance greater than upper surface tool grid 103 upper surfaces on said first silicon oxide layer 109, barrier layer 106, so that the follow-up planarization of carrying out.
With reference to Figure 12; Execution in step S7; Said interlayer dielectric layer 111 is carried out second flatening process, until exposing grid 103, said second flatening process with grid 103 for stopping layer; Can avoid on the one hand exposing barrier layer 106, can also make the flush of the upper surface and the grid 103 of interlayer dielectric layer 111 on the other hand because of continuing to grind grid 103 surfaces.
In the present embodiment; Owing to be positioned at the below of grid 103 upper surfaces as the silicon nitride on barrier layer 106; Therefore in said second flatening process; Can not carry out cmp, therefore can not form depression, and then avoid the problem of " FangIssue " at the intersection of silicon nitride and silica to the intersection of silicon nitride and silica.
Transistor fabrication process of the present invention also comprises the step of follow-up formation high-K metal grid etc., and is identical with prior art, repeats no more at this.
To sum up, the present invention provides a kind of transistorized manufacturing approach, can avoid the problem of " Fang Issue ", and then has improved the formed transistorized performance of said manufacturing approach.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (10)
1. a transistorized manufacturing approach is characterized in that, comprising: substrate is provided, on said substrate, forms transistor, said transistor comprises the grid that is positioned on the substrate; Covering barrier layer on said transistor; Blanket dielectric layer structure on said barrier layer; Said dielectric layer structure is carried out first flatening process, until the barrier layer of exposing on the grid; Removal is positioned at barrier layer and the remaining dielectric layer structure on the grid, until exposing grid, makes the upper surface of barrier layer and dielectric layer structure all be positioned at the below of gate upper surface; Deposition of insulative material on grid, barrier layer and dielectric layer structure forms interlayer dielectric layer; Said interlayer dielectric layer is carried out second flatening process, until exposing grid.
2. transistorized manufacturing approach as claimed in claim 1; It is characterized in that; Said dielectric layer structure comprises first silicon oxide layer, second silicon oxide layer that is positioned at successively on the barrier layer, and said first silicon oxide layer forms through the HARP mode, and said second silicon oxide layer forms through the TEOS mode.
3. transistorized manufacturing approach as claimed in claim 1 is characterized in that, said dielectric layer structure comprises first silicon oxide layer that is positioned on the barrier layer, and said first silicon oxide layer forms through the HARP mode.
4. like claim 2 or 3 described transistorized manufacturing approaches; It is characterized in that; Said remaining dielectric layer structure is first oxide layer, and barrier layer and remaining dielectric layer structure that said removal is positioned on the grid comprise: carry out first etching, removal is positioned at first silicon oxide layer on the grid; Carry out second etching, removal is positioned at the barrier layer on the grid.
5. transistorized manufacturing approach as claimed in claim 4 is characterized in that, the material on said barrier layer is a silicon nitride, and said first etching is compared greater than 2 the selection of first silicon oxide layer and silicon nitride.
6. transistorized manufacturing approach as claimed in claim 4 is characterized in that, the material on said barrier layer is a silicon nitride, and silicon nitride compares greater than 15 the selection of grid in said second etching, and silicon nitride compares greater than 1 the selection of silica.
7. like claim 2 or 3 described transistorized manufacturing approaches; It is characterized in that; Said etching is carried out on barrier layer and dielectric layer structure; After the step of exposing gate upper surface is accomplished, the flush of the upper surface on said barrier layer and first silicon oxide layer and with the distance of gate upper surface in the scope of
.
8. transistorized manufacturing approach as claimed in claim 1; It is characterized in that; In the said step that on the upper surface of gate upper surface, barrier layer and dielectric layer structure, forms interlayer dielectric layer, the thickness of said interlayer dielectric layer is greater than the upper surface on said dielectric layer structure, barrier layer and the distance of gate upper surface.
9. transistorized manufacturing approach as claimed in claim 1; It is characterized in that; On said transistor in the step of covering barrier layer; The material on said barrier layer is a silicon nitride, and thickness is in the scope of
.
10. like claim 2 or 3 described transistorized manufacturing approaches; It is characterized in that; Carry out first etching; Removal is arranged in the step of first silicon oxide layer on the grid, to the etched thickness of first silicon oxide layer in the scope of
.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110045416.1A CN102651319B (en) | 2011-02-24 | 2011-02-24 | Manufacturing method of transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110045416.1A CN102651319B (en) | 2011-02-24 | 2011-02-24 | Manufacturing method of transistor |
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| Publication Number | Publication Date |
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| CN102651319A true CN102651319A (en) | 2012-08-29 |
| CN102651319B CN102651319B (en) | 2014-09-03 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090149012A1 (en) * | 2004-09-30 | 2009-06-11 | Brask Justin K | Method of forming a nonplanar transistor with sidewall spacers |
| CN101714508A (en) * | 2008-10-06 | 2010-05-26 | 台湾积体电路制造股份有限公司 | Method for fabricating semiconductor device |
| CN101840862A (en) * | 2009-10-15 | 2010-09-22 | 中国科学院微电子研究所 | Forming method of high-performance semiconductor device |
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2011
- 2011-02-24 CN CN201110045416.1A patent/CN102651319B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090149012A1 (en) * | 2004-09-30 | 2009-06-11 | Brask Justin K | Method of forming a nonplanar transistor with sidewall spacers |
| CN101714508A (en) * | 2008-10-06 | 2010-05-26 | 台湾积体电路制造股份有限公司 | Method for fabricating semiconductor device |
| CN101840862A (en) * | 2009-10-15 | 2010-09-22 | 中国科学院微电子研究所 | Forming method of high-performance semiconductor device |
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| CN102651319B (en) | 2014-09-03 |
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