CN102646589B - Manufacturing method of MOSFET (metal-oxide-semiconductor field effect transistor) - Google Patents
Manufacturing method of MOSFET (metal-oxide-semiconductor field effect transistor) Download PDFInfo
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- CN102646589B CN102646589B CN201110039626.XA CN201110039626A CN102646589B CN 102646589 B CN102646589 B CN 102646589B CN 201110039626 A CN201110039626 A CN 201110039626A CN 102646589 B CN102646589 B CN 102646589B
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Abstract
The invention provides a manufacturing method of an MOSFET (metal-oxide-semiconductor field effect transistor). The manufacturing method is characterized in that a sacrificial side wall of amorphous carbon is removed by adopting oxygen or carbon dioxide plasma oxidation method to form a side wall hole; and the dielectric constant of the side wall hole is 1 and is only one seventh of a silicon nitride side wall, so that the capacitance between the grid and a contact plug of a source-drain region can be obviously reduced, and the speed and the switching power consumption performance of a short-grid-length MOSFET device can be effectively improved. The manufacturing method provided by the invention has the advantages that the process is simple, the cost is saved, the formed side wall cavity can exist permanently, and the service life of the device can be prolonged.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to the manufacture method of a kind of MOSFET.
Background technology
When grid length is shorter, the electric capacity of MOSFET (metal oxide semiconductor field effect tube) is mainly derived from the electric capacity between grid and source-drain area contact plunger, reduce this electric capacity, effectively can improve speed and the switching power loss performance of the long MOSFET element of short grid.Reduce the electric capacity between grid and source-drain area contact plunger, most effective method reduces the dielectric constant between grid and source-drain area.
The manufacture of current high density mosfet memory device generally adopts self-aligned contacts (self-alignedcontact, SAC) the silicon nitride spacer structure under technology realizes, the dielectric constant comparatively large (K=7) of silicon nitride spacer, effectively can prevent high concentration source-drain area ion implantation from entering raceway groove, avoid the short circuit between grid and source-drain area in self-aligned silicide electrode formation process.Obviously this autoregistration MOSFET manufacturing technology having silicon nitride spacer structure, can not be satisfied with the requirement of the long MOSFET manufacture of short grid to low-k sidewall structure.
Therefore, be badly in need of a kind of manufacturing technology with the autoregistration MOSFET of low-k sidewall structure, the dielectric constant between grid and source-drain area can be reduced, reduce the electric capacity between grid and source-drain area contact plunger, effectively improve speed and the switching power loss performance of the long MOSFET element of short grid.
Summary of the invention
The object of the present invention is to provide a kind of MOSFET manufacture method, the dielectric constant between grid and source-drain area can be reduced, reduce the electric capacity between grid and source-drain area contact plunger, effectively improve speed and the switching power loss performance of the long MOSFET element of short grid
For solving the problem, the present invention proposes a kind of MOSFET manufacture method, and the method comprises the steps:
There is provided Semiconductor substrate, described Semiconductor substrate is formed sacrificial gate electrode structure, described sacrificial gate electrode structure comprises the sacrifice grid of gate dielectric layer and top thereof;
Deposited sacrificial side wall layer and silicon nitride layer successively in described Semiconductor substrate and sacrificial gate electrode structure;
In the Semiconductor substrate of described sacrificial gate electrode structure both sides, carry out ion implantation, form source/drain region;
Remove described silicon nitride layer, and etch described sacrifice side wall layer formation sacrifice side wall;
At above-mentioned device architecture disposed thereon first interlayer dielectric layer, and the first interlayer dielectric layer described in planarization is to exposing described sacrifice top portions of gates;
Remove described sacrifice grid and obtain grid perforate, in grid perforate, fill grid;
Molecular sieve process deposits second interlayer dielectric layer is adopted above above-mentioned device architecture;
Etch the first interlayer dielectric layer above described source/drain region and the second interlayer dielectric layer, form the self-aligned contact hole exposing described source/drain region, in described self-aligned contact hole, fill contact plunger;
Plasma oxidation method removes described sacrifice side wall, forms side wall cavity;
Described second interlayer dielectric layer deposits dielectric layer between third layer.
Further, described sacrifice grid comprises polysilicon.
Further, remove described sacrifice grid and adopt wet-etching technology.
Further, the material of described sacrifice side wall is amorphous carbon.
Further, plasma oxidation method removes the gas of described sacrifice side wall employing is oxygen or carbon dioxide.
Further, the deposit thickness of described silicon nitride layer is 100 ~ 200 dusts.
Further, remove described silicon nitride layer and adopt dry etching or wet-etching technology.
Further, described grid is metal or high K dielectric material.
Further, also comprise before described deposition second interlayer dielectric layer and etching is carried out back to described grid, return perforate at quarter to form grid, and return at described grid and carve the sidewall of perforate and form supplementary side wall.
Further, described supplementary side wall is amorphous carbon, is together removed by plasma oxidation method with described sacrifice side wall.
Further, the material of described contact plunger is one or more in tungsten, metal nitride, titanium nitride and nitrogenize thallium.
Compared with prior art, the present invention is removed by plasma oxidation method and sacrifices side wall to form side wall cavity, the dielectric constant in side wall cavity is 1, be only 1/7th of silicon nitride spacer, significantly can reduce the electric capacity between grid and source-drain area contact plunger, effectively improve speed and the switching power loss performance of the long MOSFET element of short grid.
Accompanying drawing explanation
Fig. 1 is the process chart of the embodiment of the present invention;
Fig. 2 A to 2K is the cross-sectional view of the embodiment of the present invention.
Embodiment
Be described in further detail below in conjunction with the manufacture method of the drawings and specific embodiments to the MOSFET that the present invention proposes.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form simplified very much, only for object that is convenient, the aid illustration embodiment of the present invention lucidly.
As shown in Figure 1, the invention provides the manufacture method of a kind of MOSFET, completed by ten steps of S1 to S10, be explained in detail below in conjunction with the manufacture method of MO5FET manufacturing process cross-sectional view to above-mentioned MOSFET shown in the MOSFET manufacturing process flow diagram shown in Fig. 1 and Fig. 2 A ~ 2K.
S1, provides Semiconductor substrate, described Semiconductor substrate is formed sacrificial gate electrode structure, and described sacrificial gate electrode structure comprises the sacrifice grid of gate dielectric layer and top thereof.
Please refer to Fig. 2 A, Semiconductor substrate 100 is provided, chemical vapor deposition method and etching technics is adopted to form gate dielectric layer 101 and sacrifice grid 102 on a semiconductor substrate 100, described sacrifice grid 102 is formed at above gate dielectric layer 101, gate dielectric layer 101 and sacrifice grid 102 form sacrificial gate electrode structure, wherein, sacrifice grid 102 will be removed gate dielectric layer 101 then retain all the time in follow-up technique.In the present embodiment, sacrifice grid 102 and comprise polysilicon, gate dielectric layer 101 can be silica or silicon oxynitride, below 65nm technology node, and preferred high-k (high K) material, as aluminium oxide, zirconia, hafnium oxide etc.
S2, deposited sacrificial side wall layer and silicon nitride layer successively in described Semiconductor substrate and sacrificial gate electrode structure.
Please refer to Fig. 2 B, deposited sacrificial side wall layer 103 and silicon nitride layer 104 successively in described Semiconductor substrate 100 and sacrificial gate electrode structure.The material of described sacrifice side wall layer 103 is amorphous carbon.The deposit thickness of described silicon nitride layer 104 is 100 ~ 200 dusts.
S3, carries out ion implantation in the Semiconductor substrate of described sacrificial gate electrode structure both sides, forms source/drain region.
Please refer to Fig. 2 C, with photoresist (not shown) for mask, in described gate dielectric layer 101 with the Semiconductor substrate of sacrifice grid 102 both sides, carry out ion implantation, and short annealing process is carried out to Semiconductor substrate 100, make injection ion diffuse even, form source/drain region 105.In this step, silicon nitride layer 104 protection is sacrificed when side wall layer 103 photoresist is after ion implantation removed and is not stripped.
S4, removes described silicon nitride layer, and etches described sacrifice side wall layer formation sacrifice side wall.
Please refer to Fig. 2 D, adopt the dry etching of high selectivity or wet-etching technology to remove described silicon nitride layer 104.Please refer to Fig. 2 E, sacrifice side wall layer 103 is etched, is formed and sacrifice side wall 103a.
S5, at above-mentioned device architecture disposed thereon first interlayer dielectric layer, and is planarized to and exposes described sacrifice top portions of gates.
Please refer to Fig. 2 F, in Semiconductor substrate 100, sacrifice side wall 103a and sacrifice grid 102 disposed thereon first interlayer dielectric layer 106, and described first interlayer dielectric layer 106 of chemical-mechanical planarization (CMP), until expose described sacrifice grid 102 top.
S6, removes described sacrifice grid and obtains grid perforate, in grid perforate, fill grid.
Please refer to Fig. 2 G, remove described sacrifice grid 102 and obtain grid perforate, in grid perforate, fill grid 102a.Remove the wet-etching technology that described sacrifice grid 102 adopts high selectivity, the grid 102a of filling is metal or high K dielectric material.In the present embodiment, after having filled grid 102a, also further etching is carried out back to described grid 102a, form grid and return perforate at quarter (namely removing by etching the perforate that a part of grid 102a forms certain depth), and the sidewall adopting amorphous carbon to return perforate at quarter at described grid forms supplementary side wall 103b, increase the side wall pore size of follow-up formation, reduce the electric capacity between grid and source-drain area contact plunger further.
S7, adopts molecular sieve process deposits second interlayer dielectric layer above above-mentioned device architecture.
Please refer to Fig. 2 H, adopt molecular sieve process deposits second interlayer dielectric layer 107, many ducts or hole is had in second interlayer dielectric layer 107 of such formation, can expose and sacrifice side wall 103a and supplementary side wall 103b top, the gas be convenient in follow-up S8 step enters, and oxidation removal sacrifices side wall 103a and supplementary side wall 103b.Further CMP is carried out to the second interlayer dielectric layer 107, make its surface planarisation and above the first interlayer dielectric layer 106, retain certain thickness second interlayer dielectric layer 107.
S8, etches the first interlayer dielectric layer above described source/drain region and the second interlayer dielectric layer, forms the self-aligned contact hole in source of exposure drain region, in described self-aligned contact hole, fills contact plunger.
Please refer to Fig. 2 I, employing self-aligned contacts technology etches the first interlayer dielectric layer 106 and the second interlayer dielectric layer 107 above described source/drain region 105, forms the self-aligned contact hole exposing source/drain region, fills contact plunger 108 in described self-aligned contact hole.The material of described contact plunger 108 is one or more in tungsten, metal nitride, titanium nitride and nitrogenize thallium.
S9, plasma oxidation method removes described sacrifice side wall, forms side wall cavity.
Please refer to Fig. 2 J, using plasma oxidizing process is removed and is sacrificed side wall 103a and supplementary side wall 103b, forms side wall cavity 103c.In the present embodiment, because sacrifice side wall 103a and supplementary side wall 103b is amorphous carbon, so preferably adopt oxygen or carbon dioxide, by in the second interlayer dielectric layer 107 duct or hole, plasma oxidation removal is carried out to sacrifice side wall 103a and supplementary side wall 103b, to form side wall cavity 103c.This method, while removing sacrifice side wall 103a and supplementary side wall 103b completely, can not cause the first interlayer dielectric layer 106, contact plunger 108, the isostructural damage of grid 102a, improves device performance, simple to operate, saves process costs.
S10, described second interlayer dielectric layer deposits dielectric layer between third layer.
Please refer to Fig. 2 K, described second interlayer dielectric layer 107 deposits dielectric layer 109 between third layer, side wall cavity is preserved to seal, described second interlayer dielectric layer 107 avoids in this step when dielectric layer 109 deposits between third layer and inserts side wall cavity 103c, thus maintain the permanent existence of side wall cavity 103c, extend device useful life.
In sum, the present invention is removed by plasma oxidation method and sacrifices side wall to form side wall cavity, the dielectric constant in side wall cavity is 1, be only 1/7th of silicon nitride spacer, significantly can reduce the electric capacity between grid and source-drain area contact plunger, effectively improve speed and the switching power loss performance of the long MOSFET element of short grid; Manufacturing approach craft provided by the invention is simple, and cost-saving, the side wall cavity of formation can forever exist, and can extend the useful life of device.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a MOSFET manufacture method, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate is formed sacrificial gate electrode structure, described sacrificial gate electrode structure comprises the sacrifice grid of gate dielectric layer and top thereof;
Deposited sacrificial side wall layer and silicon nitride layer successively in described Semiconductor substrate and sacrificial gate electrode structure;
In the Semiconductor substrate of described sacrificial gate electrode structure both sides, carry out ion implantation, form source/drain region;
Remove described silicon nitride layer, and etch described sacrifice side wall layer formation sacrifice side wall;
At above-mentioned device architecture disposed thereon first interlayer dielectric layer, and the first interlayer dielectric layer described in planarization is to exposing described sacrifice top portions of gates;
Remove described sacrifice grid and obtain grid perforate, in grid perforate, fill grid;
Molecular sieve process deposits second interlayer dielectric layer is adopted above above-mentioned device architecture;
Etch the first interlayer dielectric layer above described source/drain region and the second interlayer dielectric layer, form the self-aligned contact hole exposing described source/drain region, in described self-aligned contact hole, fill contact plunger;
Plasma oxidation method removes described sacrifice side wall, forms side wall cavity;
Described second interlayer dielectric layer deposits dielectric layer between third layer.
2. MOSFET manufacture method as claimed in claim 1, it is characterized in that, described sacrifice grid comprises polysilicon.
3. MOSFET manufacture method as claimed in claim 1, is characterized in that, removes described sacrifice grid and adopts wet-etching technology.
4. MOSFET manufacture method as claimed in claim 1, it is characterized in that, the material of described sacrifice side wall is amorphous carbon.
5. MOSFET manufacture method as claimed in claim 4, is characterized in that, the gas that plasma oxidation method removes the employing of described sacrifice side wall is oxygen or carbon dioxide.
6. MOSFET manufacture method as claimed in claim 1, it is characterized in that, the deposit thickness of described silicon nitride layer is 100 ~ 200 dusts.
7. MOSFET manufacture method as claimed in claim 1, is characterized in that, removes described silicon nitride layer and adopts dry etching or wet-etching technology.
8. MOSFET manufacture method as claimed in claim 1, is characterized in that, also comprises and carries out back etching to described grid, return perforate at quarter to form grid before described deposition second interlayer dielectric layer, and forms supplementary side wall at the sidewall that described grid returns perforate at quarter.
9. MOSFET manufacture method as claimed in claim 8, it is characterized in that, described supplementary side wall is amorphous carbon, is together removed by plasma oxidation method with described sacrifice side wall.
10. MOSFET manufacture method as claimed in claim 1, is characterized in that, the material of described contact plunger is one or more in tungsten, metal nitride, titanium nitride and nitrogenize thallium.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103050438B (en) * | 2012-12-18 | 2016-08-03 | 深圳深爱半导体股份有限公司 | The lithographic method of contact hole |
| JP6625200B2 (en) * | 2016-03-24 | 2019-12-25 | 東京エレクトロン株式会社 | Method for manufacturing semiconductor device |
| US10170616B2 (en) * | 2016-09-19 | 2019-01-01 | Globalfoundries Inc. | Methods of forming a vertical transistor device |
| US10529826B1 (en) * | 2018-08-13 | 2020-01-07 | Globalfoundries Inc. | Forming self-aligned gate and source/drain contacts using sacrificial gate cap spacer and resulting devices |
| CN115910795B (en) * | 2022-11-30 | 2023-08-15 | 上海功成半导体科技有限公司 | Shielding grid power device and preparation method thereof |
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| US6054355A (en) * | 1997-06-30 | 2000-04-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device which includes forming a dummy gate |
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| JP4971559B2 (en) * | 2001-07-27 | 2012-07-11 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| TWM405167U (en) * | 2010-09-29 | 2011-06-11 | kai-mou Cai | Structure of hair organizer device to make long hair into short hair |
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| US6054355A (en) * | 1997-06-30 | 2000-04-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device which includes forming a dummy gate |
| TW405167B (en) * | 1998-04-21 | 2000-09-11 | Shr Min | Method for manufacturing a self-aligned T-type gate electrode semiconductor with air spacer |
| CN1624885A (en) * | 2003-10-22 | 2005-06-08 | 国际商业机器公司 | Method of manufacture thin silicon on insulator (SOI) with recessed channel and devices manufactured thereby |
| US7435636B1 (en) * | 2007-03-29 | 2008-10-14 | Micron Technology, Inc. | Fabrication of self-aligned gallium arsenide MOSFETs using damascene gate methods |
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| CN101971323A (en) * | 2008-03-14 | 2011-02-09 | 先进微装置公司 | Integrated circuit long and short channel metal gate devices and method of manufacture |
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