CN102646589A - Manufacturing method of MOSFET (metal-oxide-semiconductor field effect transistor) - Google Patents

Manufacturing method of MOSFET (metal-oxide-semiconductor field effect transistor) Download PDF

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CN102646589A
CN102646589A CN201110039626XA CN201110039626A CN102646589A CN 102646589 A CN102646589 A CN 102646589A CN 201110039626X A CN201110039626X A CN 201110039626XA CN 201110039626 A CN201110039626 A CN 201110039626A CN 102646589 A CN102646589 A CN 102646589A
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side wall
sacrifice
grid
dielectric layer
manufacturing approach
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CN102646589B (en
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李凡
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

The invention provides a manufacturing method of an MOSFET (metal-oxide-semiconductor field effect transistor). The manufacturing method is characterized in that a sacrificial side wall of amorphous carbon is removed by adopting oxygen or carbon dioxide plasma oxidation method to form a side wall hole; and the dielectric constant of the side wall hole is 1 and is only one seventh of a silicon nitride side wall, so that the capacitance between the grid and a contact plug of a source-drain region can be obviously reduced, and the speed and the switching power consumption performance of a short-grid-length MOSFET device can be effectively improved. The manufacturing method provided by the invention has the advantages that the process is simple, the cost is saved, the formed side wall cavity can exist permanently, and the service life of the device can be prolonged.

Description

A kind of MOSFET manufacturing approach
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to the manufacturing approach of a kind of MOSFET.
Background technology
When grid length more in short-term, the electric capacity of MOSFET (metal oxide semiconductor field effect tube) is mainly derived from the electric capacity between grid and the source-drain area contact plunger, reduces this electric capacity, can effectively improve the speed and the switch power consumption performance of the long MOSFET device of short grid.Reduce the electric capacity between grid and the source-drain area contact plunger, effective method is the dielectric constant that reduces between grid and the source-drain area.
Self-aligned contacts (self-alignedcontact is generally adopted in high density mosfet memory device manufacturing at present; SAC) the silicon nitride sidewall structure under the technology is realized; The dielectric constant of silicon nitride side wall is big (K=7); Can prevent effectively that high concentration source-drain area ion from inject getting into raceway groove, avoid the short circuit between the grid and source-drain area in the self-aligned silicide electrode forming process.Obviously this autoregistration MOSFET manufacturing technology that the silicon nitride sidewall structure is arranged can not be satisfied with the long MOSFET of short grid and make the requirement to the low-k sidewall structure.
Therefore; Be badly in need of a kind of manufacturing technology with autoregistration MOSFET of low-k sidewall structure; Can reduce the dielectric constant between grid and the source-drain area, reduce the electric capacity between grid and the source-drain area contact plunger, effectively improve the speed and the switch power consumption performance of the long MOSFET device of short grid.
Summary of the invention
The object of the present invention is to provide a kind of MOSFET manufacturing approach, can reduce the dielectric constant between grid and the source-drain area, reduce the electric capacity between grid and the source-drain area contact plunger, effectively improve the speed and the switch power consumption performance of the long MOSFET device of short grid
For addressing the above problem, the present invention proposes a kind of MOSFET manufacturing approach, and this method comprises the steps:
Semiconductor substrate is provided, forms the sacrifice gates structure on the said Semiconductor substrate, said sacrifice gates structure comprises the sacrifice gates of gate dielectric layer and top thereof;
Deposited sacrificial side wall layer and silicon nitride layer successively on said Semiconductor substrate and sacrifice gates structure;
In the Semiconductor substrate of said sacrifice gates structure both sides, carry out ion and inject formation source/drain region;
Remove said silicon nitride layer, and the said sacrifice side wall layer of etching forms the sacrifice side wall;
Deposition first interlayer dielectric layer above above-mentioned device architecture, and said first interlayer dielectric layer of planarization is to exposing said sacrifice gates top;
Remove said sacrifice gates and obtain the grid perforate, in the grid perforate, fill grid;
Above above-mentioned device architecture, adopt molecular sieve process deposits second interlayer dielectric layer;
First interlayer dielectric layer and second interlayer dielectric layer of the said source of etching/top, drain region form the self-aligned contact hole that exposes said source/drain region, in said self-aligned contact hole, fill contact plunger;
The plasma oxidation method is removed said sacrifice side wall, forms the side wall cavity;
Deposition the 3rd interlayer dielectric layer on said second interlayer dielectric layer.
Further, said sacrifice gates comprises polysilicon.
Further, remove said sacrifice gates and adopt wet-etching technology.
Further, the material of said sacrifice side wall is an amorphous carbon.
Further, to remove the gas that said sacrifice side wall adopts be oxygen or carbon dioxide to the plasma oxidation method.
Further, the deposit thickness of said silicon nitride layer is 100~200 dusts.
Further, remove said silicon nitride layer and adopt dry etching or wet-etching technology.
Further, said grid is metal or high K dielectric material.
Further, also comprise before said deposition second interlayer dielectric layer said grid is returned etching, return the perforate at quarter, and form additional side wall at the sidewall that said grid returns the perforate at quarter to form grid.
Further, said additional side wall is an amorphous carbon, is together removed by the plasma oxidation method with said sacrifice side wall.
Further, the material of said contact plunger is one or more in tungsten, metal nitride, titanium nitride and the nitrogenize thallium.
Compared with prior art; The present invention removes through the plasma oxidation method and sacrifices side wall to form the side wall cavity; The dielectric constant in side wall cavity is 1; Be merely 1/7th of silicon nitride side wall, can significantly reduce the electric capacity between grid and the source-drain area contact plunger, effectively improve the speed and the switch power consumption performance of the long MOSFET device of short grid.
Description of drawings
Fig. 1 is the process chart of the embodiment of the invention;
Fig. 2 A to 2K is the cross-sectional view of the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the manufacturing approach of the MOSFET of the present invention's proposition is done further explain.According to following explanation and claims, advantage of the present invention and characteristic will be clearer.What need explanation is, accompanying drawing all adopts the form of simplifying very much, only is used for conveniently, the purpose of the aid illustration embodiment of the invention lucidly.
As shown in Figure 1; The present invention provides the manufacturing approach of a kind of MOSFET; Ten steps by S1 to S10 are accomplished, and are explained in detail below in conjunction with MOSFET manufacturing process flow diagram shown in Figure 1 and the MO5FET manufacturing process cross-sectional view shown in Fig. 2 A~2K manufacturing approach to above-mentioned MOSFET.
S1 provides Semiconductor substrate, forms the sacrifice gates structure on the said Semiconductor substrate, and said sacrifice gates structure comprises the sacrifice gates of gate dielectric layer and top thereof.
Please refer to Fig. 2 A; Semiconductor substrate 100 is provided; On Semiconductor substrate 100, adopt chemical vapor deposition method and etching technics to form gate dielectric layer 101 and sacrifice gates 102, said sacrifice gates 102 is formed at gate dielectric layer 101 tops, and gate dielectric layer 101 constitutes the sacrifice gates structure with sacrifice gates 102; Wherein, sacrifice gates 102 will be removed then reservation all the time of gate dielectric layer 101 in follow-up technology.In the present embodiment, sacrifice gates 102 comprises polysilicon, and gate dielectric layer 101 can be silica or silicon oxynitride, below the 65nm technology node, and preferred high-k (high K) material, like aluminium oxide, zirconia, hafnium oxide etc.
S2, deposited sacrificial side wall layer and silicon nitride layer successively on said Semiconductor substrate and sacrifice gates structure.
Please refer to Fig. 2 B, deposited sacrificial side wall layer 103 and silicon nitride layer 104 successively on said Semiconductor substrate 100 and sacrifice gates structure.The material of said sacrifice side wall layer 103 is an amorphous carbon.The deposit thickness of said silicon nitride layer 104 is 100~200 dusts.
S3 carries out ion and injects formation source/drain region in the Semiconductor substrate of said sacrifice gates structure both sides.
Please refer to Fig. 2 C; With photoresist (not shown) is mask, in the Semiconductor substrate of said gate dielectric layer 101 and sacrifice gates 102 both sides, carries out ion and injects, and Semiconductor substrate 100 is carried out short annealing handle; Make the injection ions diffusion even, formation source/drain region 105.In this step, silicon nitride layer 104 protections are sacrificed when the photoresist of side wall layer 103 after ion injects removed and are not stripped from.
S4 removes said silicon nitride layer, and the said sacrifice side wall layer of etching forms the sacrifice side wall.
Please refer to Fig. 2 D, adopt the dry etching or the wet-etching technology of high selectivity to remove said silicon nitride layer 104.Please refer to Fig. 2 E, carry out etching, form and sacrifice side wall 103a sacrificing side wall layer 103.
S5, deposition first interlayer dielectric layer above above-mentioned device architecture, and be planarized to and expose said sacrifice gates top.
Please refer to Fig. 2 F, deposition first interlayer dielectric layer 106 above Semiconductor substrate 100, sacrifice side wall 103a and sacrifice gates 102, and said first interlayer dielectric layer 106 of chemical-mechanical planarization (CMP) are until exposing said sacrifice gates 102 tops.
S6 removes said sacrifice gates and obtains the grid perforate, in the grid perforate, fills grid.
Please refer to Fig. 2 G, remove said sacrifice gates 102 and obtain the grid perforate, in the grid perforate, fill grid 102a.Remove the wet-etching technology that said sacrifice gates 102 adopts high selectivity, the grid 102a of filling is metal or high K dielectric material.In the present embodiment; After having filled grid 102a; Also further said grid 102a is returned etching, form grid and return perforate (promptly removing the perforate that a part of grid 102a forms certain depth) at quarter, and adopt amorphous carbon to form additional side wall 103b at the sidewall that said grid returns the perforate at quarter through etching; Increase the side wall cavity size of follow-up formation, further reduce the electric capacity between grid and the source-drain area contact plunger.
S7 adopts molecular sieve process deposits second interlayer dielectric layer above above-mentioned device architecture.
Please refer to Fig. 2 H; Adopt molecular sieve process deposits second interlayer dielectric layer 107; In second interlayer dielectric layer 107 that forms so many ducts or hole are arranged; Can expose and sacrifice side wall 103a and additional side wall 103b top, the gas of being convenient in the follow-up S8 step gets into, and oxidation removal is sacrificed side wall 103a and additional side wall 103b.Further second interlayer dielectric layer 107 is carried out CMP, make its flattening surface and above first interlayer dielectric layer 106, keep certain thickness second interlayer dielectric layer 107.
S8, first interlayer dielectric layer and second interlayer dielectric layer of the said source of etching/top, drain region, the self-aligned contact hole in formation source of exposure drain region is filled contact plunger in said self-aligned contact hole.
Please refer to Fig. 2 I, adopt first interlayer dielectric layer 106 and second interlayer dielectric layer 107 of 105 tops, the self-aligned contacts technology said source/drain region of etching, form the self-aligned contact hole in source of exposure/drain region, in said self-aligned contact hole, fill contact plunger 108.The material of said contact plunger 108 is one or more in tungsten, metal nitride, titanium nitride and the nitrogenize thallium.
S9, the plasma oxidation method is removed said sacrifice side wall, forms the side wall cavity.
Please refer to Fig. 2 J, the using plasma oxidizing process is removed and is sacrificed side wall 103a and additional side wall 103b, forms side wall cavity 103c.In the present embodiment; Because sacrificing side wall 103a and additional side wall 103b all is amorphous carbon; So preferably adopt oxygen or carbon dioxide; Through in second interlayer dielectric layer 107 duct or hole, carry out plasma oxidation and remove sacrificing side wall 103a and additional side wall 103b, to form side wall cavity 103c.This method can not cause first interlayer dielectric layer 106 when removing sacrifice side wall 103a and additional side wall 103b fully, contact plunger 108, and the isostructural damage of grid 102a improves device performance, and is simple to operate, practices thrift the technology cost.
S10, deposition the 3rd interlayer dielectric layer on said second interlayer dielectric layer.
Please refer to Fig. 2 K; Deposition the 3rd interlayer dielectric layer 109 on said second interlayer dielectric layer 107; Preserve the side wall cavity with sealing; Insert side wall cavity 103c when said second interlayer dielectric layer 107 has been avoided the 3rd interlayer dielectric layer 109 deposition in this step, thereby kept the permanent existence of side wall cavity 103c, prolong device useful life.
In sum; The present invention removes through the plasma oxidation method and sacrifices side wall to form the side wall cavity; The dielectric constant in side wall cavity is 1; Be merely 1/7th of silicon nitride side wall, can significantly reduce the electric capacity between grid and the source-drain area contact plunger, effectively improve the speed and the switch power consumption performance of the long MOSFET device of short grid; Manufacturing approach craft provided by the invention is simple, practices thrift cost, and the side wall cavity of formation can forever exist, and can prolong the useful life of device.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.

Claims (11)

1. a MOSFET manufacturing approach is characterized in that, comprising:
Semiconductor substrate is provided, forms the sacrifice gates structure on the said Semiconductor substrate, said sacrifice gates structure comprises the sacrifice gates of gate dielectric layer and top thereof;
Deposited sacrificial side wall layer and silicon nitride layer successively on said Semiconductor substrate and sacrifice gates structure;
In the Semiconductor substrate of said sacrifice gates structure both sides, carry out ion and inject formation source/drain region;
Remove said silicon nitride layer, and the said sacrifice side wall layer of etching forms the sacrifice side wall;
Deposition first interlayer dielectric layer above above-mentioned device architecture, and said first interlayer dielectric layer of planarization is to exposing said sacrifice gates top;
Remove said sacrifice gates and obtain the grid perforate, in the grid perforate, fill grid;
Above above-mentioned device architecture, adopt molecular sieve process deposits second interlayer dielectric layer;
First interlayer dielectric layer and second interlayer dielectric layer of the said source of etching/top, drain region form the self-aligned contact hole that exposes said source/drain region, in said self-aligned contact hole, fill contact plunger;
The plasma oxidation method is removed said sacrifice side wall, forms the side wall cavity;
Deposition the 3rd interlayer dielectric layer on said second interlayer dielectric layer.
2. MOSFET manufacturing approach as claimed in claim 1 is characterized in that said sacrifice gates comprises polysilicon.
3. MOSFET manufacturing approach as claimed in claim 1 is characterized in that, removes said sacrifice gates and adopts wet-etching technology.
4. MOSFET manufacturing approach as claimed in claim 1 is characterized in that, the material of said sacrifice side wall is an amorphous carbon.
5. MOSFET manufacturing approach as claimed in claim 4 is characterized in that, the gas that the plasma oxidation method is removed said sacrifice side wall employing is oxygen or carbon dioxide.
6. MOSFET manufacturing approach as claimed in claim 1 is characterized in that, the deposit thickness of said silicon nitride layer is 100~200 dusts.
7. MOSFET manufacturing approach as claimed in claim 1 is characterized in that, removes said silicon nitride layer and adopts dry etching or wet-etching technology.
8. MOSFET manufacturing approach as claimed in claim 1 is characterized in that, said grid is metal or high K dielectric material.
9. MOSFET manufacturing approach as claimed in claim 1 is characterized in that, also comprises before said deposition second interlayer dielectric layer said grid is returned etching, returns the perforate at quarter to form grid, and forms additional side wall at the sidewall that said grid returns the perforate at quarter.
10. MOSFET manufacturing approach as claimed in claim 9 is characterized in that, said additional side wall is an amorphous carbon, is together removed by the plasma oxidation method with said sacrifice side wall.
11. MOSFET manufacturing approach as claimed in claim 1 is characterized in that, the material of said contact plunger is one or more in tungsten, metal nitride, titanium nitride and the nitrogenize thallium.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103050438A (en) * 2012-12-18 2013-04-17 深圳深爱半导体股份有限公司 Etching method of contact hole
CN107845578A (en) * 2016-09-19 2018-03-27 格芯公司 The method for forming vertical transistor devices
CN107924844A (en) * 2016-03-24 2018-04-17 东京毅力科创株式会社 The manufacture method of semiconductor device
CN110828554A (en) * 2018-08-13 2020-02-21 格芯公司 Forming self-aligned gate and source/drain contacts and resulting devices
CN115910795A (en) * 2022-11-30 2023-04-04 上海功成半导体科技有限公司 Shielding gate power device and preparation method thereof

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CN101681841A (en) * 2007-06-27 2010-03-24 国际商业机器公司 High-k/metal gate mosfet with reduced parasitic capacitance
CN101971323A (en) * 2008-03-14 2011-02-09 先进微装置公司 Integrated circuit long and short channel metal gate devices and method of manufacture
TWM405167U (en) * 2010-09-29 2011-06-11 kai-mou Cai Structure of hair organizer device to make long hair into short hair

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US6054355A (en) * 1997-06-30 2000-04-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device which includes forming a dummy gate
TW405167B (en) * 1998-04-21 2000-09-11 Shr Min Method for manufacturing a self-aligned T-type gate electrode semiconductor with air spacer
US20030022422A1 (en) * 2001-07-27 2003-01-30 Kazuyoshi Torii Semiconductor device and its manufacturing method
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103050438A (en) * 2012-12-18 2013-04-17 深圳深爱半导体股份有限公司 Etching method of contact hole
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CN107845578A (en) * 2016-09-19 2018-03-27 格芯公司 The method for forming vertical transistor devices
CN110828554A (en) * 2018-08-13 2020-02-21 格芯公司 Forming self-aligned gate and source/drain contacts and resulting devices
CN115910795A (en) * 2022-11-30 2023-04-04 上海功成半导体科技有限公司 Shielding gate power device and preparation method thereof
CN115910795B (en) * 2022-11-30 2023-08-15 上海功成半导体科技有限公司 Shielding grid power device and preparation method thereof

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