CN102468342A - Semiconductor storage unit and device, and manufacturing method for semiconductor storage device - Google Patents
Semiconductor storage unit and device, and manufacturing method for semiconductor storage device Download PDFInfo
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- CN102468342A CN102468342A CN2010105411562A CN201010541156A CN102468342A CN 102468342 A CN102468342 A CN 102468342A CN 2010105411562 A CN2010105411562 A CN 2010105411562A CN 201010541156 A CN201010541156 A CN 201010541156A CN 102468342 A CN102468342 A CN 102468342A
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Abstract
The invention discloses a semiconductor storage unit and a semiconductor storage device, and a manufacturing method for the semiconductor storage device. In the semiconductor storage unit and the semiconductor storage device, P-type doping, carbon doping and other treatment processes are adopted by a polycrystalline silicon float gate of the conventional float gate device so as to obtain deeper electronic storage potential wells; therefore, data retention capacity of the device is improved. Tunneling layer barrier engineering that multiple layers of tunneling media are stacked is introduced, and a band structure of the device is adjusted so as to obtain high erasing speed; therefore, the comprehensive storage characteristic of the device is improved.
Description
Technical field
The present invention relates to microelectronics technology, relate in particular to a kind of semiconductor memory cell, device and preparation method thereof.
Background technology
The FGS floating gate structure memory is at present by a large amount of uses and universally recognized main flow type of memory, is a kind of crucial semiconductor components and devices, is widely used in electronics and computer industry.Traditional FGS floating gate structure memory is because himself structure and material chosen cause the quick write/erase operation of requirement to store afoul limitation with long-time high stability; And along with technology node dwindle this contradiction not be improved significantly, limited the development of floating-gate memory.Traditional floating gate memory cell is the storage that the polysilicon membrane floating boom of employing n type doping is used for information.Fig. 1 adopts the sketch map of n type doped polycrystalline silicon floating gate as the memory cell of accumulation layer for prior art.Fig. 2 can be with sketch map as the memory cell of accumulation layer for prior art adopts n type doped polycrystalline silicon floating gate under the electric charge hold mode.
Along with characteristic size enters into nanoscale; How to adapt to the development of technology; When reducing memory cell size, improving the storage data writes, reads, wipes and keep performance; Become the key issue that present floating-gate memory development faces, this just requires on material or structure, traditional floating-gate memory further to be improved.Fig. 3 can be with sketch map for prior art adopts multi-crystal silicon floating bar memory cell that individual layer wears layer then under erase status.Because high tunneled holes potential barrier mainly is that electronics gets into substrate from the multi-crystal silicon floating bar tunnelling so wipe, the hole is difficult to get into floating boom from substrate, therefore needs very big erasing voltage.The increase of erasing voltage can bring the degeneration of tunnel layer, and then can make data residence characteristics variation.
In realizing process of the present invention, the inventor recognizes that there is following defective in prior art: adopt n type doped polycrystalline silicon floating gate as the memory cell of accumulation layer under the more and more littler situation of device feature size, the resident performance of its data is variation gradually.
Summary of the invention
The technical problem that (one) will solve
The object of the invention be exactly solve available technology adopting n type doped polycrystalline silicon floating gate as the memory cell of accumulation layer under the more and more littler situation of device feature size; The resident performance of its data is the technical problem of variation gradually, and proposes a kind of semiconductor storage unit and preparation method thereof.
(2) technical scheme
The inventor through discovering adopt n type doped polycrystalline silicon floating gate as the memory cell of accumulation layer under the more and more littler situation of device feature size, the resident performance of its data is variation gradually.On the other hand, can know that if the potential barrier energy level of floating boom deepens, then electronics is many more from floating gate tunneling or heat emission entering substrate energy needed, so just can suppress the leakage of electronics from theory analysis.For this reason, can consider to change the Fermi level degree of depth of multi-crystal silicon floating bar.Therefore, the present invention reduces the Fermi level of floating boom material through adopting several different methods, thereby has improved the data residence characteristics in the memory device.
To adopting the Fermi level that reduces the floating boom material; Deepen the data parameters difficult technologies problem that the electronics potential well is caused; The present invention adopts by a plurality of tunnellings sublayer and makes up the tunnel layer potential barrier; The substrate hole that increases when wiping is injected, and through the band structure of comprehensive modulation device, under the prerequisite that improves the device retention performance, has also obtained high erasing speed.
(3) beneficial effect
Follow-on semiconductor memory cell disclosed by the invention and device adopt the P type to mix to the multi-crystal silicon floating bar of traditional floating-gate device, and treatment process such as carbon C doping are stored potential well to obtain darker electronics, thereby effectively improved the data holding ability of device.
Introduce the tunnel layer potential barrier engineering of multilayer tunnelling medium stacking simultaneously, the band structure of modulation device obtains high erasing speed, thereby has comprehensively improved the storage characteristics of device.
Description of drawings
Fig. 1 adopts the sketch map of n type doped polycrystalline silicon floating gate as the memory cell of accumulation layer for prior art;
Fig. 2 can be with sketch map as the memory cell of accumulation layer for prior art adopts n type doped polycrystalline silicon floating gate under the electric charge hold mode;
Fig. 3 can be with sketch map for prior art adopts multi-crystal silicon floating bar memory cell that individual layer wears layer then under erase status;
Fig. 4 is the structural representation according to embodiment of the invention semiconductor memory cell;
Fig. 5 is the barrier junction composition according to the embodiment of the invention two semiconductor memory cells;
Fig. 6 is the barrier junction composition according to the embodiment of the invention three semiconductor memory cells;
Fig. 7 is the barrier junction composition according to the embodiment of the invention four semiconductor memory cells
Fig. 8 a is according to the embodiment of the invention five semiconductor storage unit preparation method SiO
2The sketch map of tunnel layer depositing step;
Fig. 8 b is according to the embodiment of the invention five semiconductor storage unit preparation method Si
3N
4The sketch map of tunnel layer depositing step;
Fig. 8 c is according to the embodiment of the invention five semiconductor storage unit preparation method SiO
2The sketch map of tunnel layer depositing step;
Fig. 8 d is the sketch map according to the embodiment of the invention five semiconductor storage unit preparation method multi-crystal silicon floating bar depositing steps;
Fig. 8 e injects according to the embodiment of the invention five semiconductor storage unit preparation method B ions, carries out the sketch map of P type doping step;
Fig. 8 f is the sketch map according to the embodiment of the invention five semiconductor storage unit preparation method ONO blocking layer depositing steps;
Fig. 8 g is the sketch map according to the embodiment of the invention five semiconductor storage unit preparation method gate electrode depositing steps;
Fig. 8 h is the sketch map according to the embodiment of the invention five semiconductor storage unit preparation method grid storehouse etch step;
Fig. 8 i is the sketch map that leaks implantation step according to the embodiment of the invention five semiconductor storage unit preparation method sources.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, to further explain of the present invention.
To available technology adopting n type doped polycrystalline silicon floating gate as the memory cell of accumulation layer under the more and more littler situation of device feature size; The resident performance of its data is the technical problem of variation gradually; The multi-crystal silicon floating bar that can adopt P type doping means to handle; Its Fermi level is lower than the Fermi level that n type mixes, and in electronic energy storage and the darker potential well, the resident performance of data is improved a lot.In addition, traditional multi-crystal silicon floating bar is carried out the carbon doping treatment, perhaps use SiC material (having the advantages that band gap is wide, conduction band is dark) to substitute polysilicon membrane and also can play the purpose that increases electronics storage potential well, improves the data residence characteristics as floating gate layer.But because floating boom adopts the P type to mix, the electronics potential well is darker, if adopt conventional SiO
2The tunnel layer structure, erased is difficulty very.Therefore, must be to improving erased speed, the contradiction of compromise data maintenance and program/erase efficient is comprehensively improved memory property.
The invention discloses a kind of follow-on semiconductor memory cell.Fig. 4 is the structural representation according to embodiment of the invention semiconductor memory cell.As shown in Figure 4, this semiconductor memory cell comprises: substrate; The channel region two ends form on substrate source region and drain region; The tunnel layer that above channel region, forms successively from bottom to top, floating boom accumulation layer, barrier layer with dark electronics storage potential well; The control gate that above the barrier layer, forms.Wherein, above-mentioned control gate comprises control gate dielectric layer and gate electrode.
In traditional semiconductor memory cell, the multi-crystal silicon floating bar of employing is as accumulation layer.The present invention does following improvement for the n type multi-crystal silicon floating bar in traditional floating-gate memory spare (Flash): adopt the P type to mix; Carbon C mixes perhaps with means such as carborundum SiC material replacement N type multi-crystal silicon floating bars; Drag down being with of storage medium; Obtain darker electronics storage potential well, thereby effectively improve the data holding ability of device.
In the technique scheme, the polysilicon that polysilicon that the material selection P type of the multi-crystal silicon floating bar layer that has excellent charge retention properties mixes or carbon mix.The multi-crystal silicon floating bar that perhaps C is mixed further carries out the P type and mixes, and its P type dopant is B, BF
2, B
2H
6Can also adopt the SiC material to replace multi-crystal silicon floating bar, and carry out P type doping treatment, the material that the SiC material is carried out the doping of P type is Al, B, Be, Ga, O etc.
The improvement project that the present invention proposes; Be not limited to the above-mentioned case of enumerating; Also comprise to multi-crystal silicon floating bar other processing modes of employing or with other materials replacement multi-crystal silicon floating bar and regulate and to be with, obtain dark electronics storage potential well, strengthen the technical scheme of data retention characteristics.
Deepen the problem that causes the erased difficulty to electronics storage potential well; Introduce tunnel layer potential barrier engineering; The substrate hole that increases when wiping is injected, and through the band structure of comprehensive modulation device, under the prerequisite that improves the device retention performance, has also obtained high erasing speed.According to above-mentioned thought, the invention also discloses a kind of semiconductor memory cell, this memory cell comprises: silicon substrate; Conduction region and leakage conduction region in the source of silicon substrate upper heavy doping; The source is leaked the employing multilayer material that covers on the carrier channels between the conduction region and is piled up the composite tunnel layer that carries out being with modulation in order; The multi-crystal silicon floating bar layer with dark conduction level (dark electronics storage potential well) of process doping treatment that covers on the tunneling medium layer or material replacement; The blocking layer that on floating boom, covers; And the gate electrode that on the control gate dielectric layer, covers.
In the technique scheme, composite tunnel layer is piled up in order by multilayer dielectricity and constitutes, and wherein the first tunnelling sublayer is by SiO
2Perhaps HfSiO, HfLaON etc. can with broad and with Si substrate interface characteristic good material form, the second tunnelling sublayer is Si
3N
4Or SiO
xN
yDeng being with narrower and material that valence band location is higher constitutes, the 3rd tunnelling sublayer is by SiO
2Perhaps HfSiO, HfLaON, HfAlO etc. can constitute with the material of broad.Fig. 5 is the barrier junction composition according to the embodiment of the invention two semiconductor memory cells.As shown in Figure 5, it is high that three layers of tunnelling medium stacking of tunnel layer form both sides, middle low tunneling barrier structure.
Composite tunnel dielectric layer in the technique scheme also can be selected layers of material to pile up to form both sides low, and middle high crown tunneling barrier structure is like Fig. 6.Wherein, the first tunnelling sublayer is Si
3N
4Or SiO
xN
yDeng being with narrower and material that valence band location is higher constitutes, the second tunnelling sublayer is by SiO
2Perhaps HfSiO, HfLaON etc. can form with the material of broad, and the 3rd tunnelling sublayer is Si
3N
4Or SiO
xN
yDeng being with narrower and material that valence band location is higher constitutes.Perhaps remove the 3rd layer of tunnel layer, adopt the device architecture of Si substrate → high potential barrier tunnel layer → low potential barrier (high valence band location) tunnel layer → floating boom → blocking layer → gate electrode, as shown in Figure 7.Wherein, the first tunnelling sublayer is by SiO
2Perhaps HfSiO, HfLaON etc. can form with the material of broad and with the good material of Si substrate interface characteristic, and the second tunnelling sublayer is Si
3N
4Or SiO
xN
yDeng being with narrower and material that valence band location is higher constitutes.
In the technique scheme, the control gate dielectric layer can be by individual layer SiO
2Material constitutes, perhaps by SiO
2, Si
3N
4, SiO
2Three layers of dielectric layer (ONO) material stacks is made; Perhaps by Al
2O
3, HfO
2, HfAl
xO
y, HfSi
xO
y, ZrO
2, ZrSi
xO
y, La
2O
3, Y
2O
3, LaAl
xO
y, Ta
2O
5, TiO
2Any or suitable several kinds Deng in the hafnium constitute.
In the technique scheme, control gate material layer (7) can adopt any perhaps several kinds the combination in metal, metal nitride, metal silicide, metallic silicon nitrogen compound, metal carbides, metal carbonitride compound, the polysilicon.
The invention also discloses a kind of preparation method of semiconductor storage unit, comprising:
The tunnel layer of step 1, preparation is made up of two-layer at least tunnelling sublayer on the silicon substrate of technology formerly that is finished tunneling barrier structure;
Step 2, on tunnel layer preparation by floating boom accumulation layer with dark electronics storage potential well;
Step 3, on the floating boom accumulation layer, prepare blocking layer;
Step 4, polygate electrodes deposit, etching forms gate patterns;
Step 5, execution source are leaked and are injected, source-and-drain junction activates annealing, technology for preparing electrode, accomplish the preparation of whole memory device.
In addition, maturing material and technology based on present CMOS technology have prepared follow-on semiconductor storage unit, and preparation technology is shown in Fig. 8 a to 8i:
Step a, on the silicon substrate of technologies such as ion injection that is finished with the method for thermal oxidation growth 1.5nm SiO
2, as the first tunnelling sublayer layer, shown in Fig. 8 a;
Step b is at SiO
2The Si of deposit 2.5 nanometers on the tunnel layer
3N
4Film is as the second tunnelling sublayer layer, shown in Fig. 8 b;
Step c is at Si
3N
4Deposit 2 nanometer SiO on the tunnel layer
2Film as the 3rd tunnelling sublayer layer, is accomplished the preparation of composite tunnel layer, shown in Fig. 8 c;
Steps d is captured growing polycrystalline silicon floating boom on the tunnel layer at O/N/O, shown in Fig. 8 d;
Step e carries out the P type to multi-crystal silicon floating bar and injects, and the annealing activation, shown in Fig. 8 e;
Step f carries out the growth of O/N/O blocking layer, shown in Fig. 8 f on the multi-crystal silicon floating bar layer;
Step g, the polygate electrodes deposit, etching forms gate patterns, shown in Fig. 8 g;
Step h, grid storehouse etching is shown in Fig. 8 h;
Step I, injection is leaked in the execution source on this basis, source-and-drain junction activates technologies such as annealing, electrode preparation, accomplishes the preparation of whole memory device, shown in Fig. 8 i.
In the such scheme; This preparation technology and traditional floating-gate device technology of improving storage scheme is compatible fully; Only need to increase steps necessary at relevant processing procedure, be adjusted into the plural layers growth like the tunnel layer growth by the single thin film growth, the polysilicon deposit is transformed to the other materials deposit; Perhaps keep multi-crystal silicon floating bar, change its doping condition etc.The technology that the device preparation relates to comprises thermal oxidation; But the technology of chemical vapor deposition method, sputtering technology, atomic layer deposition technology, thermal evaporation technology, pulsed laser deposition technology, electron beam evaporation process or other implementation structure is like conventional methods such as photoetching, etching, flattening surface, annealing.
Can find out that from technique scheme the present invention has following beneficial effect:
1) follow-on floating-gate memory spare of pointing out of the present invention adopts the P type to mix to the multi-crystal silicon floating bar of traditional floating-gate device, and C the dopings treatment process of etc.ing is stored potential well with the electronics that acquisition is darker, thereby effectively improves the data holding ability of device;
2) adopt C doped polycrystalline silicon technology can increase the charge storage density of floating boom, effectively increase memory window.
3) introduce the tunnel layer potential barrier engineering of multilayer tunnelling medium stacking simultaneously, the band structure of modulation device obtains high erasing speed, thereby has comprehensively improved the storage characteristics of device;
4) this modified model floating-gate memory spare manufacturing process is simple, and compatible fully with the floating-gate memory technology of routine, cost is low, is beneficial to extensive use.
Above specific embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, the above specific embodiment of the present invention that is merely that it should be understood that; Be not limited to the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (12)
1. a semiconductor memory cell is characterized in that, comprising:
Substrate;
The channel region two ends form on said substrate source region and drain region;
The tunnel layer that above said channel region, forms successively, has the floating boom accumulation layer of dark electronics storage potential well from bottom to top;
The control gate that above said floating boom accumulation layer, forms.
2. semiconductor memory cell according to claim 1 is characterized in that, said floating boom accumulation layer with dark electronics storage potential well is made up of a kind of in the following material:
The multi-crystal silicon floating bar that adopts P type doping means to handle;
The multi-crystal silicon floating bar that adopts carbon C to mix;
Carborundum SiC;
The multi-crystal silicon floating bar that adopts C to mix is carried out the material that the P type mixes and forms again;
SiC is carried out the material that the P type mixes and forms.
3. semiconductor memory cell according to claim 2 is characterized in that, saidly the multi-crystal silicon floating bar that adopts C to mix is further carried out the P type mixes in the material that forms, and carries out material that the P type mixes and be at least a in the following material: be B, BF
2, B
2H
6
4. semiconductor memory cell according to claim 2 is characterized in that, said SiC is further carried out in the material that the P type mix to form, carries out material that the P type mixes and be at least a in the following material: Al, B, Be, Ga, O.
5. semiconductor memory cell according to claim 1 is characterized in that, the said tunnel layer tunneling barrier structure that two-layer at least tunnelling sublayer is constituted of serving as reasons.
6. semiconductor memory cell according to claim 5 is characterized in that, said tunneling barrier structure is made up of three layers of tunnelling sublayer, is followed successively by from channel region is bottom-up:
By can be with broad and the first tunnelling sublayer that forms with the good material of substrate interface characteristic, said can with broad and with the good material of substrate interface characteristic be a kind of in the following material: SiO
2, HfSiO, HfLaON, Al
2O
3;
The second tunnelling sublayer that can band is narrower and material that valence band location is higher constitutes, said can band narrower and material that valence band location is higher be a kind of in the following material: Si
3N
4, HfO
2, SiO
xN
y
By constituting the 3rd tunnelling sublayer with the material of broad, said can be a kind of in the following material with the material of broad: SiO
2, HfSiO, HfLaON, HfAlO, Al
2O
3.
7. semiconductor memory cell according to claim 5 is characterized in that, said tunneling barrier structure is made up of three layers of tunnelling sublayer, is followed successively by from channel region is bottom-up:
The first tunnelling sublayer that can band is narrower and material that valence band location is higher constitutes, said can band narrower and material that valence band location is higher be a kind of in the following material: Si
3N
4, HfO
2, SiO
xN
y
By constituting the second tunnelling sublayer with the material of broad, said can be a kind of in the following material with the material of broad: SiO
2, Al
2O
3, HfSiO, HfLaON, HfAlO.
The 3rd tunnelling sublayer that can band is narrower and material that valence band location is higher constitutes, said can band narrower and material that valence band location is higher be a kind of in the following material: Si
3N
4, HfO
2, SiO
xN
y
8. semiconductor memory cell according to claim 5 is characterized in that, said substrate is silicon Si, and said tunneling barrier structure is for to be made up of two-layer tunnelling sublayer, is followed successively by from channel region is bottom-up:
By can be with broad and the first tunnelling sublayer that forms with the good material of substrate interface characteristic, said can with broad and with the good material of substrate interface characteristic be a kind of in the following material: SiO
2, Al
2O
3, HfSiO, HfLaON;
The second tunnelling sublayer that can band is narrower and material that valence band location is higher constitutes, said can band narrower and material that valence band location is higher be a kind of in the following material: Si
3N
4, Al
2O
3, HfO
2, SiO
xN
y
9. a semiconductor storage unit is characterized in that, comprises each said semiconductor memory cell in a plurality of claims 1 to 8.
10. the preparation method of a semiconductor storage unit is characterized in that, comprising:
The tunnel layer of the tunneling barrier structure that preparation is made up of two-layer at least tunnelling sublayer on the silicon substrate of technology formerly that is finished;
Preparation is by the floating boom accumulation layer with dark electronics storage potential well on said tunnel layer;
On said floating boom accumulation layer, prepare blocking layer;
The polygate electrodes deposit, etching forms gate patterns;
The execution source is leaked and is injected, source-and-drain junction activates annealing, technology for preparing electrode, accomplishes the preparation of whole memory device.
11. the preparation method of semiconductor storage unit according to claim 10 is characterized in that, comprises said on tunnel layer, the preparation by the floating boom accumulation layer with dark electronics storage potential well:
Growing polycrystalline silicon floating boom on tunnel layer;
Multi-crystal silicon floating bar is carried out the doping of P type inject, and annealing activates.
12. the preparation method of semiconductor storage unit according to claim 10 is characterized in that, the tunnel layer of the said tunneling barrier structure that preparation is made up of two-layer at least tunnelling sublayer on the silicon substrate of technology formerly that is finished comprises:
On the silicon substrate of ion implantation technology that is finished with the method for thermal oxidation growth 1.5nmSiO
2, as the first tunnelling sublayer;
At SiO
2The Si of deposit 2.5 nanometers on the tunnel layer
3N
4Film is as the second tunnelling sublayer;
At Si
3N
4Deposit 2 nanometer SiO on the tunnel layer
2Film is as the 3rd tunnelling sublayer.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425226A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Floating gate and forming method thereof, and flash memory unit and forming method thereof |
| CN105390450A (en) * | 2014-08-28 | 2016-03-09 | 瑞萨电子株式会社 | Manufacturing method of semiconductor device and semiconductor device |
| CN106611796A (en) * | 2015-10-22 | 2017-05-03 | 中芯国际集成电路制造(北京)有限公司 | A P-type MOS flash memory memory cell, a memory and a manufacturing method thereof |
| WO2018032407A1 (en) * | 2016-08-17 | 2018-02-22 | 华为技术有限公司 | Storage device and manufacturing method therefor, and data read-write method |
| CN111477625A (en) * | 2020-04-27 | 2020-07-31 | 复旦大学 | Semi-floating gate memory based on defect trapping material and preparation method thereof |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5801401A (en) * | 1997-01-29 | 1998-09-01 | Micron Technology, Inc. | Flash memory with microcrystalline silicon carbide film floating gate |
| US5901084A (en) * | 1997-03-10 | 1999-05-04 | Mitsubishi Denki Kabushiki Kaisha | Nonvolatile semiconductor memory device having floating gate electrode |
| JP2000299395A (en) * | 1999-04-14 | 2000-10-24 | Nec Corp | Nonvolatile semiconductor storage device and manufacture thereof |
| US20080149991A1 (en) * | 2006-12-22 | 2008-06-26 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device and method for manufacturing the same |
| CN101383379A (en) * | 2007-09-05 | 2009-03-11 | 中国科学院微电子研究所 | Nanocrystalline floating gate memory of multi-medium composite tunnel layer and manufacturing method |
| CN101399289A (en) * | 2007-09-26 | 2009-04-01 | 中国科学院微电子研究所 | Nanocrystalline floating gate non-vaporability memory with double layer tunneling medium structure and manufacturing method |
| CN101414479A (en) * | 2007-10-18 | 2009-04-22 | 旺宏电子股份有限公司 | One-transistor memory cell on insulator random access memory |
| US20090140317A1 (en) * | 2007-12-03 | 2009-06-04 | Interuniversitair Microelektronica Centrum (Imec) | Multiple Layer floating gate non-volatile memory device |
| CN101494224A (en) * | 2009-02-23 | 2009-07-29 | 中国科学院微电子研究所 | Memory and method for producing the same |
-
2010
- 2010-11-10 CN CN2010105411562A patent/CN102468342A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5801401A (en) * | 1997-01-29 | 1998-09-01 | Micron Technology, Inc. | Flash memory with microcrystalline silicon carbide film floating gate |
| US5901084A (en) * | 1997-03-10 | 1999-05-04 | Mitsubishi Denki Kabushiki Kaisha | Nonvolatile semiconductor memory device having floating gate electrode |
| JP2000299395A (en) * | 1999-04-14 | 2000-10-24 | Nec Corp | Nonvolatile semiconductor storage device and manufacture thereof |
| US20080149991A1 (en) * | 2006-12-22 | 2008-06-26 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device and method for manufacturing the same |
| CN101383379A (en) * | 2007-09-05 | 2009-03-11 | 中国科学院微电子研究所 | Nanocrystalline floating gate memory of multi-medium composite tunnel layer and manufacturing method |
| CN101399289A (en) * | 2007-09-26 | 2009-04-01 | 中国科学院微电子研究所 | Nanocrystalline floating gate non-vaporability memory with double layer tunneling medium structure and manufacturing method |
| CN101414479A (en) * | 2007-10-18 | 2009-04-22 | 旺宏电子股份有限公司 | One-transistor memory cell on insulator random access memory |
| US20090140317A1 (en) * | 2007-12-03 | 2009-06-04 | Interuniversitair Microelektronica Centrum (Imec) | Multiple Layer floating gate non-volatile memory device |
| CN101494224A (en) * | 2009-02-23 | 2009-07-29 | 中国科学院微电子研究所 | Memory and method for producing the same |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425226A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Floating gate and forming method thereof, and flash memory unit and forming method thereof |
| CN104425226B (en) * | 2013-08-20 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | Floating boom and forming method thereof, flash cell and forming method thereof |
| CN105390450A (en) * | 2014-08-28 | 2016-03-09 | 瑞萨电子株式会社 | Manufacturing method of semiconductor device and semiconductor device |
| CN105390450B (en) * | 2014-08-28 | 2020-09-29 | 瑞萨电子株式会社 | Method for manufacturing semiconductor device and semiconductor device |
| CN106611796A (en) * | 2015-10-22 | 2017-05-03 | 中芯国际集成电路制造(北京)有限公司 | A P-type MOS flash memory memory cell, a memory and a manufacturing method thereof |
| WO2018032407A1 (en) * | 2016-08-17 | 2018-02-22 | 华为技术有限公司 | Storage device and manufacturing method therefor, and data read-write method |
| CN111771259A (en) * | 2018-02-28 | 2020-10-13 | Abb电网瑞士股份公司 | Method for co-injecting p-type doped silicon carbide through Al/Be |
| CN111771259B (en) * | 2018-02-28 | 2021-07-02 | Abb电网瑞士股份公司 | Method for co-injecting p-type doped silicon carbide through Al/Be |
| US11211248B2 (en) | 2018-02-28 | 2021-12-28 | Abb Power Grids Switzerland Ag | SiC electronic device fabricated by Al/Be co-implantation |
| CN111477625A (en) * | 2020-04-27 | 2020-07-31 | 复旦大学 | Semi-floating gate memory based on defect trapping material and preparation method thereof |
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