CN102437048A - Method and device for improving etching of through holes in double-through-hole etching stop layer crossover region - Google Patents
Method and device for improving etching of through holes in double-through-hole etching stop layer crossover region Download PDFInfo
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- CN102437048A CN102437048A CN2011102220892A CN201110222089A CN102437048A CN 102437048 A CN102437048 A CN 102437048A CN 2011102220892 A CN2011102220892 A CN 2011102220892A CN 201110222089 A CN201110222089 A CN 201110222089A CN 102437048 A CN102437048 A CN 102437048A
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Abstract
The invention discloses a method for improving etching of through holes in a double-through-hole etching stop layer crossover region and a CMOS (complementary metal oxide semiconductor) device provided with a double-through-hole etching stop layer so as to enhance the carrier migration rate. The width of the double-through-hole etching stop layer crossover region is changed to prevent the through holes in the double-through-hole etching stop layer crossover region from incapability of being completely opened. The invention provides a method capable of being perfectly combined with the prior art.
Description
Technical field
The present invention relates to the semiconductor fabrication technical field, relate in particular to and a kind ofly improve dual via etch and stop layer method of crossover region via etch and a kind of device that stops to have on layer crossover region through hole in dual via etch.
Background technology
Along with the development of semiconductor related manufacturing process and the IC chip trend of dimension shrinks proportionally; Stress engineering role aspect semiconductor technology and performance of semiconductor device is more and more obvious, and stress engineering is on the semiconductor device that improves transistor carrier mobility.At present, just there are some to be applied on some special chip types, like complementary metal oxide semiconductors (CMOS) (CMOS, Complementary Metal-Oxide-Semiconductor) device.
Usually, in complicated preparation technology's flow process of cmos device, have various stress, because progressively the dwindling of device size, and the stress of finally staying in the device channel region has bigger influence to the performance of device.A lot of stress have improvement to the performance of device, and different types of stress has different influence to the charge carrier in the device (being electronics and hole) mobility.For example, tensile stress is useful to the NMOS electron mobility on the cmos device channel direction, and compression is useful to the PMOS hole mobility.
Via etch stops layer (Contact-Etch-Stop-Layer; Be CESL) stress engineering is to stop in the layer film deposition process in via etch, through the adjustment sedimentary condition; At the inner adding of film stress (can be compression; Also can be tensile stress), this stress is transmitted in the cmos device raceway groove, can exert an influence to the mobility of charge carrier rate.For example for nmos device (as shown in Figure 1), when the deposition via etch stops layer film, through the adjustment sedimentary condition; In the inner compression that produces of film; This stress is transmitted in the nmos device raceway groove, and raceway groove is formed tensile stress, because the tensile stress on the channel direction helps to improve the electron mobility of nmos device; So the inner via etch of compression that keeps stops layer, and is useful to the electron mobility that improves nmos device.
Because the stress in the raceway groove can cause different influences to NMOS and PMOS, for example, tensile stress is useful to the NMOS electron mobility on the cmos device channel direction, and compression is useful to the PMOS hole mobility.So when the stress engineering of utilizing single via etch to stop layer is improved the performance of a kind of device (such as NMOS), the performance that always will sacrifice another kind of device (such as PMOS).In order to improve this negative influence, can adopt dual via etch stop layer process.The flow process of dual via etch stop layer process is shown in Fig. 2 a ~ 2d.At first deposit the layer of silicon dioxide film; As removing first protective film 101 that via etch stops layer; Then deposit one deck can form tensile stress in raceway groove silicon nitride film and stop layer 102 (a) like Fig. 2 as first via etch; This electron mobility to nmos device has the raising effect, but the hole mobility of PMOS device is had the reduction effect.Then adopt and do the silicon nitride film that the method for carving is removed the PMOS device area.Can stop (like Fig. 2 b) dried quarter when etching into first protective film 101 of silicon dioxide.Deposit the layer of silicon dioxide protective film afterwards again as second protective film 201; So that after dried quarter in the process silicon nitride film in nmos area territory is protected; Next be that deposition one deck can form compression in raceway groove silicon nitride film stops layer 202 (like Fig. 2 c) as second via etch, this helps improving the hole mobility of PMOS device.At last, utilize the method for doing quarter to remove the silicon nitride film (like Fig. 2 d) in nmos area territory.In the final device architecture that forms, form tensile stress in the NMOS raceway groove, form compression in the PMOS raceway groove.Dual via etch stops the ply stress engineering, promptly can improve the electron mobility in the nmos device, can improve the hole mobility in the PMOS device again.
In dual via etch stop layer process, can bring the problem in the follow-up via etch process in the overlapping part of (compression and tensile stress) etching stop layers of two kinds of stress, such as Fig. 3 a ~ 3b description.Among Fig. 3 a, accomplished dual via etch stop layer process, follow-up layer insulation medium 4 (generally adopting phosphorosilicate glass, i.e. PSG) deposition and chemico-mechanical polishing are also accomplished.The silicon nitride film of two kinds of different stress has overlapping above the polysilicon on the shallow trench.Next can carry out via etch process.
Shown in Fig. 3 b; For through hole 302, because it is positioned at the crossover region of two kinds of different stress nitride silicon thin films, after carrying out the second step via etch process; Through hole only can be parked in above the crossover region on the layer of silicon dioxide protective film; This can cause the 3rd step etching to carve fully and wear a layer silicon nitride film, and promptly first via etch among Fig. 3 b stops layer 102, causes final through hole 302 to open fully.
Therefore, provide a kind of and can improve dual via etch and stop a layer crossover region via etch, and stop layer method that the through hole of overlapping region top is opened fully and just seem particularly important being positioned at dual via etch.
Summary of the invention
The object of the invention stops etching through hole on the device of layer crossover region having dual via etch, and opens through hole fully, with the problem of avoiding causing because overlapping region is narrow in the prior art that can not open through hole fully.
The present invention discloses a kind of method of improving doubled via etching stop layer crossover region via etch, provides to have at least one the first transistor and at least one transistor seconds semiconductor substrate; First protective film covers on said the first transistor and the transistor seconds; First via etch stops layer, covers on said first protective film, and said first via etch stops layer and is positioned at the vertical top of said the first transistor, said first via etch stop layer and said transistor seconds in the vertical direction do not have overlap regional; Second protective film covers said first via etch and stops upper surface and the sidewall of layer and first protective film is not stopped layer covering by said first via etch a part; Second via etch stops layer, covers on said second protective film, it is characterized in that, carries out following steps:
Etching is removed second via etch and is stopped the part that layer is positioned at said the first transistor vertical direction top; The part that makes second protective film be positioned at said the first transistor vertical direction top exposes; Part second via etch stops layer and stops the overlapping of layer at vertical direction with part first via etch; Form first via etch and stop the overlapping region that layer and second via etch stop the coincidence of layer in the vertical direction; Said overlapping region is positioned at the vertical top of the shallow trench of said semiconductor substrate; The top of said shallow ditch groove structure is provided with polysilicon, said first via etch stop overlap width that layer and second via etch stop layer overlapping region greater than follow-up above said overlapping region the diameter of the through hole of etching;
Dielectric covers upper surface and the sidewall that the said second protective film exposed portions, said second via etch stop layer remainder between the deposition cambium layer;
The said layer insulation medium of chemical-mechanical planarization;
Position above said layer insulation medium is positioned at said overlapping region, adopt different selection to stop than the said layer insulation medium of etching, second via etch successively that layer, second protective film, first via etch stop layer and first protective film to form first through hole of a said polysilicon.
Above-mentioned method; Wherein, Be formed with first active area or first polysilicon on the said semiconductor substrate; Said first active area or first polysilicon and said second via etch stop a layer in the vertical direction zero lap, adopt different selection to stop layer and first protective film to form second through hole that contacts said first active area or first polysilicon than the said layer insulation medium of etching, second protective film, first via etch successively.
Above-mentioned method; Wherein, Be formed with second active area or second polysilicon on the said semiconductor substrate; Said second active area or second polysilicon and said first via etch stop a layer in the vertical direction zero lap, adopt different selections than the said layer insulation medium of etching, second via etch stop layer, second protective film and first protective film to form a third through-hole that contacts said second active area or second polysilicon successively.
Above-mentioned method, wherein, said first protective film and said second protective film are silicon dioxide.
Above-mentioned method, wherein, said the first transistor is the NMOS pipe, said first via etch stops layer in NMOS pipe trench road, producing the silicon nitride film of tensile stress.
Above-mentioned method, wherein, said transistor seconds is the PMOS pipe, said second via etch stops layer in PMOS pipe trench road, producing the silicon nitride film of compression.
Above-mentioned method, wherein, said layer insulation medium is a phosphorosilicate glass.
Above-mentioned method, wherein, the etching of said first through hole comprises:
The first step adopts dielectric between high level/silicon nitride to select dielectric between the lithographic method etch layer of ratio, and etching at first terminates in second via etch and stops layer;
Second step, adopt high silicon nitride/silicon dioxide to select the lithographic method of ratio to carve to wear second via etch to stop layer, etching terminates in second protective film;
The 3rd step, adopt high silicon dioxide/silicon nitride to select the lithographic method of ratio to carve and wear second protective film, etching terminates in first via etch and stops layer;
The 4th step, adopt high silicon nitride/silicon dioxide to select the lithographic method of ratio to carve to wear first via etch to stop layer, etching terminates in first protective film;
The 5th step, adopt high silicon dioxide/silicon to select the lithographic method of ratio to carve and wear first protective film, etching terminates in polysilicon, accomplishes etching process to form first through hole of contact polysilicon.
Above-mentioned method, wherein, the etching of said second through hole comprises:
The first step adopts dielectric between high level/silicon dioxide to select dielectric between the lithographic method etch layer of ratio, and etching at first terminates in second protective film;
Second step, adopt high silicon dioxide/silicon nitride to select the lithographic method of ratio to carve and wear second protective film, etching terminates in first via etch and stops layer;
The 3rd step, adopt high silicon nitride/silicon dioxide to select the lithographic method of ratio to carve to wear first via etch to stop layer, etching terminates in first protective film;
The 4th step, adopt high silicon dioxide/silicon to select the lithographic method of ratio to carve and wear first protective film, etching terminates in first active area or first polysilicon, accomplishes etching process to form second through hole of contact first active area or first polysilicon.
Above-mentioned method, wherein, the etching of said third through-hole comprises:
The first step adopts dielectric between high level/silicon nitride to select dielectric between the lithographic method etch layer of ratio, and etching terminates in second via etch and stops layer;
Second step, adopt high silicon nitride/silicon dioxide to select the lithographic method of ratio to carve to wear second via etch to stop layer, etching terminates in second protective film;
The 3rd step, adopt silica/silicon to select the lithographic method of ratio to carve and wear second protective film and first protective film, etching terminates in second active area or second polysilicon, accomplishes etching process to form the third through-hole of contact second active area or second polysilicon.
According to another aspect of the present invention, also disclose a kind of cmos device, comprising with doubled via etching stop layer with raising carrier mobility speed:
Have at least one the first transistor and at least one transistor seconds semiconductor substrate;
First protective film covers on said the first transistor and the transistor seconds;
First via etch stops layer, covers on said first protective film, and said first via etch stops layer and is positioned at the vertical top of said the first transistor, said first via etch stop layer and said transistor seconds in the vertical direction do not have overlap regional;
Second protective film covers said first via etch and stops upper surface and the sidewall of layer and first protective film is not stopped layer covering by said first via etch a part;
Second via etch stops layer; Cover on said second protective film; Said second via etch stops the vertical top that layer is positioned at said transistor seconds; Said second via etch stops layer and said the first transistor in the vertical direction not to be had and overlaps regionally, and said second via etch stops layer and said first via etch stops a layer in the vertical direction and has overlapping region, and said overlapping region is positioned at the top of the shallow trench of said semiconductor substrate;
The layer insulation medium covers said second via etch and stops on the layer and second protective film;
Wherein, the top of the shallow trench of said semiconductor substrate has polysilicon, and said overlapping region is positioned on the said polysilicon;
First through hole; In the vertical direction overlaps with said overlapping region; The diameter of said first through hole stops layer less than said first via etch and stops the overlap width of layer overlapping region with second via etch, and said first through hole runs through said layer insulation medium, second via etch to be stopped layer, second protective film, first via etch and stop layer with first protective film and contact said polysilicon.
Above-mentioned cmos device wherein, is formed with first active area or first polysilicon on the said semiconductor substrate, said first active area or first polysilicon and said second via etch stop a layer in the vertical direction zero lap,
Second through hole runs through said layer insulation medium, second protective film, first via etch and stops layer with first protective film and contact said first active area or first polysilicon.
Above-mentioned cmos device wherein, is formed with second active area or second polysilicon on the said semiconductor substrate, said second active area or second polysilicon and said first via etch stop a layer in the vertical direction zero lap;
Third through-hole runs through that said layer insulation medium, second via etch stop layer, second protective film is with first protective film and contact said second active area or second polysilicon.
Above-mentioned cmos device, wherein, said first protective film and said second protective film are silicon dioxide.
Above-mentioned cmos device, wherein, said the first transistor is the NMOS pipe, said first via etch stops layer in NMOS pipe trench road, producing the silicon nitride film of tensile stress.
Above-mentioned cmos device, wherein, said transistor seconds is the PMOS pipe, said second via etch stops layer in PMOS pipe trench road, producing the silicon nitride film of compression.
Above-mentioned cmos device, wherein, said layer insulation medium is a phosphorosilicate glass.
The present invention stops the overlapping part of layer through the via etch of widening two kinds of stress; Then on this basis; Respectively the through hole that is positioned at crossover region and the through hole that is positioned at normal areas are carried out etching, solve the defective that to open all through holes in the device of the etching stop layer that has two kinds of stress in the prior art fully.
Description of drawings
Through reading the detailed description of non-limiting example being done with reference to following accompanying drawing, it is more obvious that the present invention and characteristic thereof, profile and advantage will become.Mark identical in whole accompanying drawings is indicated identical part.Painstakingly proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, the part parts have been amplified.
Fig. 1 shows in the prior art, covers via etch on a kind of NMOS pipe and stops layer in raceway groove, to produce the sketch map of tensile stress;
Fig. 2 a shows in the prior art, covers via etch on a kind of cmos device and stops layer in the raceway groove of NMOS pipe and PMOS pipe, to produce the sketch map of tensile stress;
Fig. 2 b shows in the prior art,, only stop layer only in the raceway groove of NMOS pipe, to produce the sketch map of tensile stress in a kind of cmos device in covering via etch on the NMOS pipe;
Fig. 2 c shows in the prior art, only on the NMOS pipe, covers via etch in a kind of cmos device and stops layer only in raceway groove, to produce tensile stress at the NMOS pipe, also covers a via etch in addition and stops layer in the raceway groove of PMOS pipe, to produce compression;
Fig. 2 d stops layer with the via etch that is used for producing compression among Fig. 2 c and covers the sketch map after remove on NMOS pipe top;
Fig. 3 a illustrates in the prior art, is provided with the sketch map of polysilicon between shallow trench in semiconductor and the two through hole etching stop layer overlapping region;
Fig. 3 b illustrates the sketch map that can't open the overlapping region through hole in the prior art fully;
Fig. 4 a illustrates according to of the present invention, and a kind of shallow trench in semiconductor has the sketch map of the two through hole etching stop layer overlapping region of broad;
Fig. 4 b illustrates according to of the present invention, at the sketch map of non-overlapping region etching through hole;
Fig. 4 c illustrates according to of the present invention, at the sketch map of the overlapping region etching through hole of widening.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is further elaborated.Embodiment described herein only is used to explain the present invention, and is not used in qualification protection scope of the present invention.
In conjunction with Fig. 2 c, shown in figure 4a to Fig. 4 c, the disclosed a kind of method of improving doubled via etching stop layer crossover region via etch of the present invention; This method is the device fabrication that is used to have doubled via etching stop layer overlapping region; Shown in Fig. 2 c, said device has at least one the first transistor and at least one transistor seconds semiconductor substrate, preferably; Said the first transistor is NMOS, and transistor seconds is PMOS; First protective film 101 covers on said the first transistor and the transistor seconds; First via etch stops layer 102; Cover on said first protective film 101; Said first via etch stops the vertical top that layer 102 is positioned at said the first transistor, said first via etch stop layer 102 and said transistor seconds in the vertical direction do not have overlap regional; Second protective film 201 covers said first via etch and stops layer 102 upper surface and sidewall and first protective film 101 are not stopped layer 102 covering by said first via etch a part; Second via etch stops layer 202, covers on said second protective film 201, in conjunction with reference to figure 4a; Fig. 4 a has amplified the structure in shallow trench zone; The first transistor and the transistor seconds on not shown said shallow trench both sides, the inventive method are characterised in that, carry out following steps:
Etching is removed second via etch and is stopped the part that layer 202 is arranged in said the first transistor (Fig. 4 a is not shown) vertical direction top; The part that makes second protective film 201 be positioned at said the first transistor vertical direction top exposes; Part second via etch stops layer 202 and stops layer 102 overlapping at vertical direction with part first via etch; Form first via etch and stop the overlapping region 5 that layer 102 and second via etch stops the coincidence of layer 202 in the vertical direction; Said overlapping region 5 is positioned at the vertical top of the shallow trench of said semiconductor substrate; The top of said shallow ditch groove structure is provided with polysilicon 601, said first via etch stop overlap width that layer and second via etch stop layer overlapping region 5 greater than follow-up above said overlapping region 5 diameter of the through hole of etching;
Said second protective film, 201 exposed portions of dielectric 4 coverings, said second via etch stop the upper surface and the sidewall of layer 202 remainder between the deposition cambium layer;
The said layer insulation medium 4 of chemical-mechanical planarization;
With reference to figure 4c; Position above said layer insulation medium 4 is positioned at said overlapping region 5, adopt different selection than the said layer insulation medium of etching successively 4, second via etch stop layer 202, second protective film 201, first via etch stops layer 102 and first protective film 101 to form first through hole 304 of a said polysilicon 601.
Further; With reference to being formed with first active area 602 or the first polysilicon (not shown) on figure 4b and the said semiconductor substrate of Fig. 4 c; Said first active area 602 or first polysilicon and said second via etch stop layer 202 an in the vertical direction zero lap, adopts different selection than the said layer insulation medium of etching successively 4, second protective film 201, first via etch stop layers 102 with first protective film 101 to form second through hole 301 that contacts said first active area 602 or first polysilicon.This step is the method that is applied in the normal areas except that doubled via etching stop layer overlapping region in the device with doubled via etching stop layer, and wherein, said first active area 602 or first polysilicon are positioned on the first transistor.
In a variant; Be different from first active area 602 or first polysilicon on the first transistor; Be formed with second active area (not indicating among the figure) or second polysilicon (not indicating among the figure) on the said semiconductor substrate; It will be apparent to those skilled in the art that; Corresponding first active area 602 or first polysilicon; Said second active area or second polysilicon are positioned on the transistor seconds, and said second active area or second polysilicon and said first via etch stop a layer in the vertical direction zero lap, adopt different selection to stop layer 202, second protective film and first protective film to form a third through-hole that contacts said second active area or second polysilicon than the said layer insulation medium of etching successively 4, second via etch.
In a specific embodiment, the material of said first protective film 101 and said second protective film 201 is silicon dioxide.
In another specific embodiment, said the first transistor is the NMOS pipe, and said first via etch stops layer 102 in NMOS pipe trench road, producing the silicon nitride film of tensile stress.
Further, said transistor seconds is the PMOS pipe, and said second via etch stops layer 202 in PMOS pipe trench road, producing the silicon nitride film of compression.
Further, said layer insulation medium 4 is a phosphorosilicate glass.
With reference to figure 4c, below specify the etching process of said first through hole 304, comprising:
The first step adopts dielectric between high level/silicon nitride to select dielectric 4 between the lithographic method etch layer of ratio, and etching at first terminates in second via etch and stops layer 202;
Second step, adopt high silicon nitride/silicon dioxide to select the lithographic method of ratio to carve to wear second via etch to stop layer 202, etching terminates in second protective film 201;
The 3rd step, adopt high silicon dioxide/silicon nitride to select the lithographic method of ratio to carve and wear second protective film 201, etching terminates in first via etch and stops layer 102;
The 4th step, adopt high silicon nitride/silicon dioxide to select the lithographic method of ratio to carve to wear first via etch to stop layer 102, etching terminates in first protective film 101;
The 5th step, adopt high silicon dioxide/silicon to select the lithographic method of ratio to carve and wear first protective film 101, etching terminates in polysilicon 601, accomplishes etching process to form first through hole 304 of contact polysilicon 601.In this step, the diameter of first through hole 304 is less than the width 5 of said overlapping region.
For the said etching that is positioned at second through hole 301 of the first transistor side, carry out through following steps:
The first step adopts dielectric between high level/silicon dioxide to select dielectric between the lithographic method etch layer of ratio, and etching at first terminates in second protective film 201;
Second step, adopt high silicon dioxide/silicon nitride to select the lithographic method of ratio to carve and wear second protective film 201, etching terminates in first via etch and stops layer 102;
The 3rd step, adopt high silicon nitride/silicon dioxide to select the lithographic method of ratio to carve to wear first via etch to stop layer 102, etching terminates in first protective film 101;
The 4th step, adopt high silicon dioxide/silicon to select the lithographic method of ratio to carve and wear first protective film 101, etching terminates in first active area or first polysilicon, accomplishes etching process to form second through hole 301 of contact first active area or first polysilicon.Because second through hole 301 is common through holes, it does not contact with said overlapping region 5.
For the said etching that is positioned at the third through-hole of transistor seconds side, carry out through following steps:
The first step adopts dielectric between high level/silicon nitride to select dielectric 4 between the lithographic method etch layer of ratio, and etching terminates in second via etch and stops layer 202;
Second step, adopt high silicon nitride/silicon dioxide to select the lithographic method of ratio to carve to wear second via etch to stop layer 202, etching terminates in second protective film 201;
Wherein, Second protective film 201 is the identical silicon dioxide of material with first protective film 101; Therefore can carry out etching to second protective film 201 and first protective film 101 simultaneously, carry out for the 3rd step, adopt silica/silicon to select the lithographic method of ratio to carve and wear second protective film and first protective film; Etching terminates in second active area or second polysilicon, accomplishes etching process to form the third through-hole of contact second active area or second polysilicon.The structure of said third through-hole and second through hole are similar, and those skilled in the art can combine second through hole 301 to make third through-hole, and are therefore not shown in the accompanying drawings.
According to another aspect of the present invention, also disclose a kind of cmos device, comprising with doubled via etching stop layer with raising carrier mobility speed:
Have at least one the first transistor and at least one transistor seconds semiconductor substrate; With reference to figure 4c, amplified the shallow trench zone among the figure, therefore not shown the first transistor and transistor seconds; These are prior art, are not technical characterictics of the present invention, the restriction of the accompanying drawing size of consideration; Therefore in same accompanying drawing, do not show, can combine Fig. 2 d to understand;
First protective film 101 covers on said the first transistor and the transistor seconds;
First via etch stops layer 102; Cover on said first protective film 101; Said first via etch stops the vertical top that layer 102 is positioned at said the first transistor, said first via etch stop layer 102 and said transistor seconds in the vertical direction do not have overlap regional;
Second protective film 201 covers said first via etch and stops layer 102 upper surface and sidewall and first protective film 101 are not stopped layer covering by said first via etch a part;
With reference to figure 4b and Fig. 4 c; Second via etch stops layer 202; Cover on said second protective film 201; Said second via etch stops the vertical top that layer 202 is positioned at said transistor seconds; Said second via etch stops layer 202 not to be had with said the first transistor in the vertical direction and overlaps the zone, and said second via etch stops layer 202 and said first via etch and stops layer 102 in the vertical direction and have overlapping region 5, and said overlapping region 5 is positioned at the top of the shallow trench of said semiconductor substrate;
Wherein, the top of the shallow trench of said semiconductor substrate has polysilicon 601, and said overlapping region 5 is positioned on the said polysilicon 601;
First through hole 304; In the vertical direction overlaps with said overlapping region 5; The diameter of said first through hole 304 stops the overlap width that layer 102 and second via etch stops layer 202 overlapping region 5 less than said first via etch, and said first through hole 304 runs through said layer insulation medium 4, second via etch to be stopped layer 202, second protective film 201, first via etch and stop layers 102 with first protective film 101 and contact said polysilicon 601.
Preferably, be formed with first active area 602 or first polysilicon (not indicating in the accompanying drawings) on the said semiconductor substrate, said first active area 601 or first polysilicon and said second via etch stop layer 202 in the vertical direction zero lap;
Second through hole 301 runs through said layer insulation medium 4, second protective film 201, first via etch and stops layer 102 with first protective film 101 and contact said first active area 602 or first polysilicon.
Further; Be formed with second active area (not indicating in the accompanying drawings) or second polysilicon (not indicating in the accompanying drawings) on the said semiconductor substrate, said second active area or second polysilicon and said first via etch stop a layer in the vertical direction zero lap;
Third through-hole (in the accompanying drawings indicate) runs through said layer insulation medium 4, second via etch and stops layer 202, second protective film 201 with first protective film 101 and contact said second active area or second polysilicon.
In a specific embodiment, said first protective film 101 is a silicon dioxide with said second protective film 201.
In another preference, said the first transistor is the NMOS pipe, and said first via etch stops layer 102 in NMOS pipe trench road, producing the silicon nitride film of tensile stress.
Further, said transistor seconds is the PMOS pipe, and said second via etch stops layer 202 in PMOS pipe trench road, producing the silicon nitride film of compression.
Preferably, said layer insulation medium 4 is a phosphorosilicate glass.
Etching method for forming through hole of having illustrated doubled via etching stop layer overlapping structure that above-mentioned explanation is detailed and device with this structure; It will be appreciated by those skilled in the art that the first transistor also can be the PMOS pipe, correspondingly; Transistor seconds is the NMOS pipe; Said first via etch stops layer and is used to produce the device channel internal pressure stress, and said second via etch stops layer and is used to produce tensile stress in the device channel, and such variation does not influence enforcement of the present invention.
It should be appreciated by those skilled in the art that those skilled in the art combine prior art and the foregoing description can realize said variant, such variant does not influence flesh and blood of the present invention, does not repeat them here.
More than preferred embodiment of the present invention is described.It will be appreciated that the present invention is not limited to above-mentioned specific implementations, equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention; Or being revised as the equivalent embodiment of equivalent variations, this does not influence flesh and blood of the present invention.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (17)
1. a method of improving doubled via etching stop layer crossover region via etch provides to have at least one the first transistor and at least one transistor seconds semiconductor substrate; First protective film covers on said the first transistor and the transistor seconds; First via etch stops layer, covers on said first protective film, and said first via etch stops layer and is positioned at the vertical top of said the first transistor, said first via etch stop layer and said transistor seconds in the vertical direction do not have overlap regional; Second protective film covers said first via etch and stops upper surface and the sidewall of layer and first protective film is not stopped layer covering by said first via etch a part; Second via etch stops layer, covers on said second protective film, it is characterized in that, carries out following steps:
Etching is removed second via etch and is stopped the part that layer is positioned at said the first transistor vertical direction top; The part that makes second protective film be positioned at said the first transistor vertical direction top exposes; Part second via etch stops layer and stops the overlapping of layer at vertical direction with part first via etch; Form first via etch and stop the overlapping region that layer and second via etch stop the coincidence of layer in the vertical direction; Said overlapping region is positioned at the vertical top of the shallow trench of said semiconductor substrate; The top of said shallow ditch groove structure is provided with polysilicon, said first via etch stop overlap width that layer and second via etch stop layer overlapping region greater than follow-up above said overlapping region the diameter of the through hole of etching;
Dielectric covers upper surface and the sidewall that the said second protective film exposed portions, said second via etch stop layer remainder between the deposition cambium layer;
The said layer insulation medium of chemical-mechanical planarization;
Position above said layer insulation medium is positioned at said overlapping region, adopt different selection to stop than the said layer insulation medium of etching, second via etch successively that layer, second protective film, first via etch stop layer and first protective film to form first through hole of a said polysilicon.
2. method according to claim 1; It is characterized in that; Be formed with first active area or first polysilicon on the said semiconductor substrate; Said first active area or first polysilicon and said second via etch stop a layer in the vertical direction zero lap, adopt different selection to stop layer and first protective film to form second through hole that contacts said first active area or first polysilicon than the said layer insulation medium of etching, second protective film, first via etch successively.
3. method according to claim 1; It is characterized in that; Be formed with second active area or second polysilicon on the said semiconductor substrate; Said second active area or second polysilicon and said first via etch stop a layer in the vertical direction zero lap, adopt different selections than the said layer insulation medium of etching, second via etch stop layer, second protective film and first protective film to form a third through-hole that contacts said second active area or second polysilicon successively.
4. according to any described method in the claim 1 to 3, it is characterized in that said first protective film and said second protective film are silicon dioxide.
5. method according to claim 4 is characterized in that, said the first transistor is the NMOS pipe, and said first via etch stops layer in NMOS pipe trench road, producing the silicon nitride film of tensile stress.
6. method according to claim 5 is characterized in that, said transistor seconds is the PMOS pipe, and said second via etch stops layer in PMOS pipe trench road, producing the silicon nitride film of compression.
7. method according to claim 6 is characterized in that, said layer insulation medium is a phosphorosilicate glass.
8. method according to claim 7 is characterized in that, the etching of said first through hole comprises:
The first step adopts dielectric between high level/silicon nitride to select dielectric between the lithographic method etch layer of ratio, and etching at first terminates in second via etch and stops layer;
Second step, adopt high silicon nitride/silicon dioxide to select the lithographic method of ratio to carve to wear second via etch to stop layer, etching terminates in second protective film;
The 3rd step, adopt high silicon dioxide/silicon nitride to select the lithographic method of ratio to carve and wear second protective film, etching terminates in first via etch and stops layer;
The 4th step, adopt high silicon nitride/silicon dioxide to select the lithographic method of ratio to carve to wear first via etch to stop layer, etching terminates in first protective film;
The 5th step, adopt high silicon dioxide/silicon to select the lithographic method of ratio to carve and wear first protective film, etching terminates in polysilicon, accomplishes etching process to form first through hole of contact polysilicon.
9. method according to claim 7 is characterized in that, the etching of said second through hole comprises:
The first step adopts dielectric between high level/silicon dioxide to select dielectric between the lithographic method etch layer of ratio, and etching at first terminates in second protective film;
Second step, adopt high silicon dioxide/silicon nitride to select the lithographic method of ratio to carve and wear second protective film, etching terminates in first via etch and stops layer;
The 3rd step, adopt high silicon nitride/silicon dioxide to select the lithographic method of ratio to carve to wear first via etch to stop layer, etching terminates in first protective film;
The 4th step, adopt high silicon dioxide/silicon to select the lithographic method of ratio to carve and wear first protective film, etching terminates in first active area or first polysilicon, accomplishes etching process to form second through hole of contact first active area or first polysilicon.
10. method according to claim 7 is characterized in that, the etching of said third through-hole comprises:
The first step adopts dielectric between high level/silicon nitride to select dielectric between the lithographic method etch layer of ratio, and etching terminates in second via etch and stops layer;
Second step, adopt high silicon nitride/silicon dioxide to select the lithographic method of ratio to carve to wear second via etch to stop layer, etching terminates in second protective film;
The 3rd step, adopt silica/silicon to select the lithographic method of ratio to carve and wear second protective film and first protective film, etching terminates in second active area or second polysilicon, accomplishes etching process to form the third through-hole of contact second active area or second polysilicon.
11. one kind has the doubled via etching stop layer to improve the cmos device of carrier mobility speed, comprising:
Have at least one the first transistor and at least one transistor seconds semiconductor substrate;
First protective film covers on said the first transistor and the transistor seconds;
First via etch stops layer, covers on said first protective film, and said first via etch stops layer and is positioned at the vertical top of said the first transistor, said first via etch stop layer and said transistor seconds in the vertical direction do not have overlap regional;
Second protective film covers said first via etch and stops upper surface and the sidewall of layer and first protective film is not stopped layer covering by said first via etch a part;
Second via etch stops layer; Cover on said second protective film; Said second via etch stops the vertical top that layer is positioned at said transistor seconds; Said second via etch stops layer and said the first transistor in the vertical direction not to be had and overlaps regionally, and said second via etch stops layer and said first via etch stops a layer in the vertical direction and has overlapping region, and said overlapping region is positioned at the top of the shallow trench of said semiconductor substrate;
The layer insulation medium covers said second via etch and stops on the layer and second protective film;
It is characterized in that the top of the shallow trench of said semiconductor substrate has polysilicon, said overlapping region is positioned on the said polysilicon;
First through hole; In the vertical direction overlaps with said overlapping region; The diameter of said first through hole stops layer less than said first via etch and stops the overlap width of layer overlapping region with second via etch, and said first through hole runs through said layer insulation medium, second via etch to be stopped layer, second protective film, first via etch and stop layer with first protective film and contact said polysilicon.
12. cmos device according to claim 11 is characterized in that, is formed with first active area or first polysilicon on the said semiconductor substrate, said first active area or first polysilicon and said second via etch stop a layer in the vertical direction zero lap;
Second through hole runs through said layer insulation medium, second protective film, first via etch and stops layer with first protective film and contact said first active area or first polysilicon.
13. cmos device according to claim 11 is characterized in that, is formed with second active area or second polysilicon on the said semiconductor substrate, said second active area or second polysilicon and said first via etch stop a layer in the vertical direction zero lap;
Third through-hole runs through that said layer insulation medium, second via etch stop layer, second protective film is with first protective film and contact said second active area or second polysilicon.
14., it is characterized in that said first protective film and said second protective film are silicon dioxide according to any described cmos device in the claim 11 to 13.
15., it is characterized in that said the first transistor is the NMOS pipe according to any described cmos device in the claim 11 to 13, said first via etch stops layer in NMOS pipe trench road, producing the silicon nitride film of tensile stress.
16., it is characterized in that said transistor seconds is the PMOS pipe according to any described cmos device in the claim 11 to 13, said second via etch stops layer in PMOS pipe trench road, producing the silicon nitride film of compression.
17. cmos device according to claim 11 is characterized in that, said layer insulation medium is a phosphorosilicate glass.
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