CN102365392A - Plasma etching method - Google Patents

Plasma etching method Download PDF

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Publication number
CN102365392A
CN102365392A CN2010800139349A CN201080013934A CN102365392A CN 102365392 A CN102365392 A CN 102365392A CN 2010800139349 A CN2010800139349 A CN 2010800139349A CN 201080013934 A CN201080013934 A CN 201080013934A CN 102365392 A CN102365392 A CN 102365392A
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Prior art keywords
etching
width
pattern
substrate
measured
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金高裕树
小津俊久
高桥正彦
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/3244—Gas supply means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/3244—Gas supply means
    • H01J37/32449—Gas control, e.g. control of the gas flow
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for processing a substrate to form a desired pattern by an etching process after forming a mask pattern over the substrate includes the steps of forming two layers over the substrate; measuring a width of the mask pattern or an etched pattern of one of the two layers; and adjusting a flow rate of any one of HBr and other gases, used in the etching process, based on the measured width. The two layers may include a silicon nitride layer and an organic dielectric layer.

Description

Plasma-etching method
The application requires the U.S. Provisional Application sequence number No.61/210 that submitted on March 24th, 2009; 990, the U.S. Provisional Application sequence number No.61/211 that submitted on March 31st, 2009; 573, the U.S. Provisional Application sequence number No.61/211 that submitted on March 31st, 2009; 614 right of priority, this three's title all are " Plasma Etching Method (plasma-etching method) ", by reference its content all are combined in here.
Technical field
The present invention relates to semiconductor device and method of manufacture thereof.More specifically, it relates to the etch plasma body method of the high resolution design that is used to provide critical size (CD) value with expectation.
Background technology
In semiconductor fabrication processing, photoetching technique is used to form the resist pattern.In photoetching technique, resist solution at first is coated on semi-conductor or liquid-crystal display (LCD) substrate.Use photomask, resist film is made public for the pattern of high light and is developed afterwards.Therefore, on semi-conductor or LCD substrate, form the resist pattern of expectation.After the resist pattern that forms expectation, will be used for the etch processes of etching semiconductor or LCD substrate.
Known owing to there is the factor of not expecting; For example; The fluctuation of the condition of substrate surface, normal atmosphere and temperature and relative humidity is so even under the constant process condition, carry out each above-mentioned treatment step, such processing causes them may not satisfy target value.
Traditionally, after the substrate of handling fixed number, substrate is drawn out to check.In checking process, measure various parameters and whether suitable based on check result judgment processing condition.The example of these parameters can be included in live width or the critical size (CD) of thickness, the resist pattern development treatment after of the resist film after the coated, with the tolerance range of fundamental design and resist pattern match, through the defective of lip-deep inconsistent, the development of development and through live width or the critical size (CD) and the lip-deep defective after etch processes of etched substrate.
Can revise the treatment condition that are used for each treatment step according to the judgement of carrying out based on check result afterwards.Can carry out this operation modification (this bothers very much) through experienced operator.For the ease of retouching operation, in Japanese Patent Application No.2002-190446, proposed a kind of resist pattern and formed processing.In this is handled, at first confirm predetermined group the modification parameter relevant with each concrete measuring parameter.Revise the modification parameter of predetermined group afterwards according to automatic detected result.
For example, be considered under the situation of concrete measuring parameter, can revise following modification parameter to realize target value: (1) light exposure intensity in the live width or the critical size (CD) of etch substrate; (2) heat-up time; (3) development time; (4) etching period; (5) etching gas is formed ratio.Yet above-mentioned communique does not explain that the gas composition ratio is the etch processes that how to influence the expectation target value that is used to realize critical size (CD).
In addition, in Japanese Patent Application No.2003-209093, disclose a kind of like this substrate processing technology, wherein, the critical size of resist pattern (CD) is accurately measured after etching step, to form the circuit pattern of expectation.In this technology, at first measure the critical size (CD) of resist pattern.The measuring result quilt is to the etch processes unit feedback that is used to adjust treatment condition afterwards.Through optimum process condition is set, can after etch processes, obtain accurately and the ideal circuit pattern.This technology provides the feed forward method that is used for coming based on measured resist film critical size (CD) pattern of etching expectation.Yet similar with communique before, it is not pointed out about the etching gas type of the critical size (CD) that is used to realize expect and the actual conditions of their composition ratio.
The present invention considers the problems referred to above and proposes.The invention provides and be used to use the etching gas of particular type and the technology that their composition ratio forms high resolution design.
Summary of the invention
According to an aspect of the present invention, a kind of method that substrate is handled is provided, it is used for after on said substrate, forming mask pattern forming through etch processes the pattern of expectation.This method may further comprise the steps: on substrate, form two layers, these two layers comprise silicon nitride layer and organic dielectric layer; Measure in mask pattern and two layers width of one etched pattern; And the flow velocity of adjusting in HBr and other gases any one based on measured width.HBr is used in the etch processes with other gases.
According to a second aspect of the invention; A kind of method that substrate is handled is provided; It is used for after on substrate, forming mask pattern forming through etch processes the pattern of expectation; This method may further comprise the steps: on substrate, form three layers, three layers comprise silicon nitride layer, organic dielectric layer and contain the anti-reflection coating of silicon; Measure in mask pattern and three layers width of one etched pattern; And adjust CF based on measured width 4And CHF 3In any one flow velocity.CF 4And CHF 3Be used in the etch processes.
Description of drawings
Fig. 1 is shown schematically in before carrying out plasma etch process and the embodiment of object construction afterwards.
Fig. 2 is shown schematically in the alternative embodiment of object construction and the sectional view of the test sample after silicon nitride (SiN) layer is carried out patterning.
Fig. 3 has described the synoptic diagram of the embodiment of plasma processing apparatus.
Fig. 4 has described to be attached to the synoptic diagram of the embodiment that is coated with the wire width measuring device in the developing machine.
Fig. 5 has described to be attached to the synoptic diagram of the alternative embodiment of the wire width measuring device in the etching system.
Fig. 6 shows the embodiment of the processing of the live width that is used to adjust pattern.
Fig. 7 has described the exemplary plot of the alternative embodiment of independent wire width measuring device.
Fig. 8 shows the sectional view of test sample, and this test sample shows when intensive pattern and isolated patterns after each concrete layer place has carried out plasma etch process.
Fig. 9 shows the sectional view of test sample and handles the critical size (CD) that changes with spending etching (OE) time.
Figure 10 shows the sectional view of test sample and with the critical size (CD) of HBr change in flow.
Figure 11 shows the sectional view of test sample, and it shows intensive pattern and isolated patterns for various etching gas types.
Figure 12 shows the sectional view of test sample and with Ar/HBr/O 2The critical size (CD) of series change in flow.
Figure 13 shows the sectional view and their critical size (CD) of test sample.
Figure 14 shows microwave power, RF power and the funtcional relationship of RF voltage and time of each mask layer.
Figure 15 shows the sectional view and their critical size (CD) of test sample.
Figure 16 shows the sectional view and their critical size (CD) of test sample.
Embodiment
Hereinafter will embodiment of the invention will be described with reference to drawings, wherein show the preferred embodiments of the present invention.Ensuing description is not in order to limit scope of the present invention, flexibility and structure.On the contrary, the following description of preferred illustrative embodiment will be provided for making it possible to implement the description of preferred illustrative embodiment of the present disclosure to those skilled in the art.Should be noted that the present invention may be implemented as different forms, and do not leave the spirit and scope of the present invention of stating by claim.
The disclosure relates generally to semiconductor device and their manufacturing processed.More specifically, it relates to the etch plasma body method of the high resolution design that is used to provide critical size (CD) value with expectation.
Embodiments of the invention relate to and are used to control the live width of silicon (Si) pattern or the etch processes of critical size (CD).Use silicon nitride (SiN) hard mask pattern to form silicon (Si) pattern.The hard mask of silicon nitride (SiN) transfers to use the tri-layer mask pattern to form.The tri-layer mask pattern includes dynamo-electric medium layer (ODL).For silicon (Si) pattern of the expectation that obtains to have predetermined critical size (CD) value, should accurately control the live width or the critical size of the hard mask of silicon nitride (SiN) that is formed on silicon (Si) substrate.This can through in to organic dielectric layer (ODL) patterning at the mixed atmosphere (N of nitrogen and oxygen 2/ O 2) in add hydrogen bromide (HBr) and realize.
Through adding hydrogen bromide (HBr) and increasing its flow velocity, because the extraction of oxygen (O) can reduce hydrogen (H) concentration on the surface of ODL layer.Therefore produced organic dielectric layer (ODL) with high carbon content.The high-carbon content of ODL layer produces and makes the more firm C-C of organic dielectric layer (ODL).Particularly when CD value during less than target value, the fastness properties of ODL is for through reducing the critical size (CD) that horizontal etch-rate obtains preset value better controllability being provided.
In addition, the high-carbon content of ODL layer has produced a plurality of bromo-carbon bonds on the surface of ODL pattern.Therefore, the veneer of bromination carbon (CBrx) is protected as sidewall on the ODL pattern.This has caused critical size (CD) thickening of ODL.
According to embodiments of the invention, realize the critical size of expecting (CD) through adjustment hydrogen bromide (HBr) flow velocity when carrying out main etching (ME) step for organic dielectric layer (ODL).Through increasing hydrogen bromide (HBr) flow velocity, the value of the critical size of ODL pattern (CD) trends towards increasing.
According to another embodiment, also can be through after accomplishing main etching (ME) step, carrying out the critical size (CD) that etching (OE) step realizes the ODL pattern.In crossing etching (OE) step, can be through the ratio (N of adjustment nitrogen and oxygen 2/ O 2) and the hydrogen bromide (HBr) that increases appropriate amount realize critical size (CD) value expected.Therefore,, can handle for main etching (ME) so and adjust, and the out-phase of being on duty is to hour, can handle and adjust for crossing etching (OE) if the difference between actual CD value and the target value is relatively large.
In one embodiment, can be set to the fixed value through hydrogen bromide (HBr) flow velocity when prolonging the etching period section and increase critical size (CD) value.In alternative embodiment, can thicken critical size (CD) value through increasing hydrogen bromide (HBr) flow velocity.This makes hydrogen bromide (HBr) gas higher with the component ratio of other gases in whole atmosphere.
According to another embodiment, can be through crossing at ODL in etching (OE) step through adjusting the ratio (N of nitrogen and oxygen 2/ O 2) and add chlorine (Cl 2) realize critical size (CD) value expected.
According to another embodiment, can be through when organic dielectric layer (ODL) be carried out patterning, at argon gas and oxygen (Ar/O 2) rather than nitrogen and oxygen (N 2/ O 2) mixed atmosphere in add hydrogen bromide (HBr) and realize critical size (CD) value expected.In this embodiment, can be through reducing oxygen (O 2) flow velocity increases the critical size (CD) of ODL layer.
According to alternative embodiment of the present invention, can, the anti-reflection coating (Si-ARC) that contains silicon realize having the desired pattern of predetermined critical size (CD) value when being carried out patterning.In the present embodiment, can pass through the ratio (CF of the gas of adjustment tetrafluoro-methane and trifluoromethane 4/ CHF 3) increase or reduce the live width or the critical size of Si-ARC layer.
According to another embodiment, can realize having the desired pattern of predetermined critical size (CD) value through the level of adjustment RF bias power source.In the present embodiment, critical size (CD) value is proportional with the RF bias level (power) that is applied.This means that the RF bias level is high more, critical size (CD) value is thick more.On the contrary, lower RF bias level provides thinner critical size (CD) value.
Confirm the parameter adjusted in the above-described embodiments based on the measuring result of the critical size (CD) of resist pattern or any mask pattern, such as the hydrogen bromide in the ODL step (HBr) the flow velocity, (CF in the Si-ARC patterning step 4/ CHF 3) ratio and RF bias level.
According to an embodiment; The observed value of the resist pattern after development treatment in semiconducter substrate is used to confirm to be used to carry out the condition that suitably is provided with lower floor's etching step (for example, the organic dielectric layer (ODL) in the identical semiconducter substrate or contain the anti-reflection coating (Si-ARC) of silicon).
According to another embodiment, resist pattern or organic dielectric layer (ODL) in a semiconducter substrate and the observed value of etched pattern that contains the anti-reflection coating (Si-ARC) of silicon are used to confirm to be used for carrying out in another semiconducter substrate the condition that suitably is provided with of etching step.
According to another embodiment, when being used in identical semiconducter substrate, carry out etching step, organic dielectric layer (ODL) in a semiconducter substrate and the observed value of etched pattern that contains the anti-reflection coating (Si-ARC) of silicon confirm suitably to be provided with condition.
With reference to Fig. 1, show before carrying out plasma etch process and the embodiment of object construction 10 afterwards.As shown in the figure, object construction 10 can comprise silicon (Si) substrate 12, hard mask silicon nitride (SiN) layer 14 and three-decker 16.Three-decker 16 includes dynamo-electric medium layer (ODL) 16a, contains anti-reflection coating (Si-ARC) 16b and the resist pattern 16c of silicon.In order accurately to control final silicon (Si) pattern, the hard mask layer of SiN layer 14 should be precisely defined on the Si substrate 12.For the intended shape (comprising CD value or live width) of the hard mask pattern of realizing SiN layer 14, can use three-decker 16 (16a, 16b and 16c) to come the hard mask pattern of etching SiN layer 14.More specifically; After the resist pattern 16c that forms expectation; Will be respectively for Si-ARC layer 16b, ODL layer 16a and hard mask silicon nitride (SiN) layer 14 execution sequence etch processes, with through coming Si substrate 12 is carried out etching and whole pattern is finally transferred on silicon (Si) substrate 12 as mask firmly via the pattern of SiN layer 14.In Fig. 1, also show final silicon (Si) underlay pattern 12 and have some residual SiN patterns 14.
Like what describe in the preceding text, owing to have the factor of not expecting, for example, the fluctuation of the condition of substrate surface, normal atmosphere and temperature and relative humidity, the live width of resist pattern 16c or critical size (CD) possibly not satisfy expected value.Therefore, the order etch processes may not provide Si-ARC, ODL, SiN and silicon (Si) substrate 12 with expectation target pattern.For to above-mentioned some assess, at first based on the replacement object construction made test sample.Make test sample receive traditional plasma etch process afterwards.Hereinafter, describe in detail after carrying out plasma etch process, have the replacement object construction of desired destination pattern.
Afterwards with reference to Fig. 2, show the alternative embodiment of the object construction 20 that is used to carry out plasma etch process.Object construction 20 is extra silicon oxide (SiO with the difference of object construction 10 2) layer 22 is inserted between layer-of-substrate silicon 12 and the hard mask silicon nitride (SiN) layer.Similar with object construction 10, on hard mask silicon nitride (SiN) layer 14, form three-decker 16.In this embodiment, the expectation critical size (CD) that is used for resist pattern 16c is set to about 40-45nm.Be appreciated that this concrete example to be for schematic purpose and not to be in order limiting.Also in Fig. 2, be shown schematically in the desired destination pattern after carrying out plasma etch process.
The sectional view of the test sample after silicon nitride (SiN) layer 14 is carried out patterning has been shown in Fig. 2.As shown in the figure, the critical size of silicon nitride pattern (CD) is about 33.4nm, and this has approached about 7nm than ideal critical size (CD).Distance between the measured pattern is about 65.7nm, and measured pattern height is about 49.9nm.
In traditional plasma etch process, most of mask material quilt is isotropic etching to a certain degree.This means that etching also flatly carries out in a way.Therefore, with plasma etch applications to such as organic dielectric layer (ODL) 16a the time, the vertical etching that lateral erosion is carved with ODL 16a side by side takes place.Therefore, the cross-sectional shape of the mask pattern of ODL 16a becomes away from the rectangular shape of expectation, and becomes the skirt shape of for example gradual change.Afterwards, the SiN layer through the ODL mask etching will can not become the target shape that is designed.Ideally, it is preferred not having the etched directional etch of horizontal direction.Yet in practice, the anisotropic etching that has littler etch-rate in the horizontal direction is an ideal.
As for the counter-measure of the lateral etches of ODL layer 16a and also for the critical size (CD) of the pattern of controlling SiN layer 14; The invention provides plasma body and cross etching (OE) processing; Wherein, When organic dielectric layer (ODL) 16a was carried out patterning, the hydrogen bromide of specified quantitative (HBr) was added to nitrogen and oxygen (N 2/ O 2) mixed atmosphere in.Studied about adding the various treatment condition of hydrogen bromide (HBr) gas.These researchs mainly are performed the processing of finding out ODL sidewall protection mechanism and also having set up control critical size (CD) when etching.The example of these treatment condition can comprise HBr flow velocity, etching period, etching gas type, the substrate bias power that is applied to substrate and their component ratio.
On the other hand, during plasma etch process of the present invention, can use different control methods so that high resolving power (tolerance range) pattern with predetermined critical size (CD) to be provided on silicon (Si) substrate 12.The example of these control methods can comprise that feed forward control is handled, feedback control is handled and dynamic (on-the-spot (in-situ)) control is handled.Hereinafter, will distinguish the above-mentioned control of specific explanations each in handling.
In one embodiment, feed-forward process control is used to obtain to have the pattern of predetermined critical size (CD).In this embodiment, at first use any device that can buy to measure live width or the critical size (CD) of resist pattern 16c.Can adopt integral measuring (IM) device with opticmeasurement, for example, scatterometer.As hereinafter further describe; In certain embodiments; Live width (CD) measuring apparatus is integrated in the coating developing machine; In this coating developing machine, before substrate transport is carried out etch processes subsequently in the etching system, the sub-image of the photo-resist after the measuring exposed or the CD value through developing.In other embodiments, when before the actual etch processes of beginning, carrying out under the situation of CD measurement, can in having combined the IM device of etching system, carry out CD and measure.In alternative embodiment, CD measures and can replace the IM instrument to carry out by the independent measurement system.Will further describe the specific descriptions of live width or CD measuring apparatus hereinafter.In the live width of measuring resist pattern 16c or critical size (CD) afterwards, judge the target value whether critical size (CD) of resist pattern 16c meets the expectation.Critical size (CD) at resist pattern 16c does not satisfy under the situation of its expectation target value, at first confirms about the flow velocity of plasma etching gas and the condition that suitably is provided with of type.Etch processes adjustment subsequently for Si-ARC layer 16c or ODL layer 16a is provided with condition in identical semiconducter substrate afterwards.
In alternative embodiment, feedback processing control is used to obtain to have the pattern of predetermined critical size (CD).In this alternative embodiment, at first studied live width or the critical size (CD) of Si-ARC pattern 16b or ODL layer 16a.Whether the critical size (CD) of judging ODL pattern 16a (Si-ARC pattern 16b) satisfies its desired destination value.Critical size (CD) at ODL pattern 16a (Si-ARC pattern 16b) does not satisfy under the situation of its desired destination value, confirms the suitable condition that is provided with about the flow velocity and the type of plasma etching gas.The substrate etch device of adjusting for another semiconducter substrate after the condition of setting is sent to; So that the mask pattern of predetermined critical size (CD) to be provided on silicon (Si) substrate 12, such as SiN hard mask pattern 14, ODL pattern 16a, Si-ARC pattern 16b and resist pattern 16c.
In another alternative embodiment, dynamichandling control (scene) can be used to obtain to have the pattern of predetermined critical size (CD).In the present embodiment; During etch processes, at first measure the live width or the critical size (CD) of ODL pattern 16a or SiN hard mask pattern 14; And during the plasma etch process of ODL layer 16a or SiN layer 14, dynamically adjust about the flow velocity of plasma etching gas and the condition that suitably is provided with of type.Hereinafter, will independently particularly explain etching system and live width or CD measurement.
Etching system:
Fig. 3 shows the synoptic diagram of the embodiment of plasma processing apparatus 30.As shown in the figure, plasma processing apparatus 30 comprises processing vessel 120, radiation frid 300, substrate keeper 140 and dielectric window 160.Processing vessel 120 can comprise bottom 17 (they are positioned at substrate keeper 140 belows) and cylindrical side wall 18 (17 periphery extends upward from the bottom for it).The upside of processing vessel 120 is open-ended.Dielectric window 160 is arranged to the upside that encircles 20 sealed containers 120 with substrate keeper 140 relatively and via O shape.Plasma processing apparatus 30 also comprises unshowned in the accompanying drawings unit, with the integrated operation of control treatment condition and device.
(for example, 2.45GHz) microwave power offers radiation frid 300 via coaxial waveguide 24 and slow-wave plate 28 to external microwave producer 15 with preset frequency.Coaxial waveguide 24 can comprise centre conductor 25 and periphery conductor 26.Sent to dielectric window 160 through a plurality of grooves 29 that are arranged on the radiation frid 300 after the microwave power.Microwave from microwave generator 15 produces electric field below dielectric window 160, itself then cause processing vessel 120 ionic medium gas (nitrogen (N 2) or argon gas (Ar)) excite.The depressed part 27 that is arranged on the inboard of dielectric window 160 makes it possible in processing vessel 120, carry out effective plasma generation.
External high frequency power supply 37 is connected to substrate keeper 140 via matching unit 38 and EPS electrode 39.High-frequency power supply 37 produces preset frequency, and (for example, RF substrate bias power 13.56MHz) is used to control the ion energy that attracted to substrate.Matching unit 38 makes the impedance of RF power power-supply 37 and the impedance phase of load (for example processing vessel 120) mate.Electrostatic chuck 41 is arranged on the upper surface of substrate keeper 30, is used for keeping substrate via DC power power-supply 46 through electrostatic attraction.
Plasma processing apparatus 30 also comprises reactant gases supply section 13.The enlarged view of reactant gases supply section 13 also has been shown in Fig. 3.As shown in the figure, reactant gases supply section 13 can be included in dielectric window 160 internal-phase ratio are positioned at going-back position in the lower surface 63 of dielectric window 160 base portion injector 61.Reactant gases supply section 13 also is included in thickness direction and passes dielectric window 160 to keep the base portion keeper 64 of base portion injector 61.The plat of base portion injector 61 also has been shown in Fig. 3.As shown in the figure, a plurality of supply orifices 66 be arranged on the relatively localized flat wall surfaces 67 of substrate keeper 140 on.A plurality of supply orifices 66 are positioned at the central authorities of flat wall surfaces 67 radially.
Reactant gases supply section 13 also comprises gas pipeline 68.As shown in Figure 3, gas pipeline 68 is penetrated into a plurality of supply orifices 66 through centre conductor 25, radiation frid 300 and dielectric window 160 respectively from coaxial waveguide 24.Gas supply system 72 is connected to the gas inlet orifice 69 of the upper end that is formed on centre conductor 25.Gas supply system 72 can comprise open and close valve 70 and flow speed controller 71 (for example, mass flow control device).
In addition, can reactant gases be fed to processing vessel 120 through two other gas pipeline 89 that is arranged on the cylindrical side wall 18.Should be noted that reactant gases is at least one in plasma exciatiaon gas or the material gas.Through the flow velocity of adjustment, can in processing vessel 120, realize optimum material gas disassociation from the reactant gases of gas pipeline 68 and 89 supplies.
Live width or CD measuring apparatus:
Use wire width measuring device to come measurements and calculations resist pattern 16c, contain the live width of anti-reflection coating (Si-ARC) 16b, organic dielectric layer (ODL) 16a or silicon nitride (SiN) layer 14 of silicon.This device can be self, be integrated into the type (being called IM (integral measuring appearance)) in the coating developing machine or be integrated into any in the type in the etching system.When wire width measuring device is built in the coating developing machine, can after processing, measure the sub-image of the resist after developing or the live width of resist immediately.When wire width measuring device is built in the etching system, can before etching and after the etching, measure live width.On the other hand, can use the independent measurement system to carry out live width or CD measurement.Hereinafter, each in specific explanations the foregoing description independently.
(1) is integrated into the wire width measuring device that is coated with in the developing machine
Fig. 4 shows the synoptic diagram of the embodiment of the wire width measuring device 402-A in the entire structure that is integrated into photo-resist formation device 40-A.For ease, simplified the one-piece construction of photo-resist formation device 40-A.As shown in Figure 4, the one-piece construction of photo-resist forming device 40-A can comprise coating developing machine 400-A and exposure sources 420.Coating developing machine 400-A is installed to exposure sources 420, this exposure sources 420 can then be connected to etching system 440.
Photo-resist forms device 40-A can comprise wire width measuring device 402-A, a plurality of processing unit (coater unit or) 404-A and two substrate transport unit 406-A.A plurality of processing unit 404-A can also comprise coater unit and/or developing cell.Substrate transport unit 406-A has the function of transmission substrate between the different adjacent parts in the entire structure of photo-resist formation device 40-A.In addition, substrate transport unit 406-A be up and down with the structure that moves forward and backward, and can rotate around vertical axes.
After carrying out development treatment, measure the live width or the critical size (CD) of resist pattern.In next procedure, calculate the suitable condition that is provided with based on measured live width, for example, the flow velocity of etching gas.Afterwards, the suitable condition that is provided with is fed forward to etching system 440 from coating developing machine 400-A.In certain embodiments, measured raw data can be sent to etching system 440 from coating developing machine 400-A, and is processed to obtain suitable etching condition.In these embodiment, use treatment condition DBs (not shown in the accompanying drawings) to calculate the suitable condition that is provided with through measured raw data.These treatment condition DBs have been stored various treatment condition in the storer of computingmachine 442.
(2) be integrated into wire width measuring device in the etching system:
With reference to Fig. 5, show the synoptic diagram that photo-resist forms the integrally-built embodiment of device 40-B.As shown in the figure, the difference of the one-piece construction of photo-resist formation device 40-B and the structure of 40-A is that wire width measuring device 402-B is integrated among the etching system 440-B, rather than is integrated in the coating developing machine 400.Other assemblies are basic identical with the structure of 40-A.In this embodiment, can three all control methods be used to control underlay pattern, these three control methods comprise: (1) feed forward control is handled, and (2) feedback control is handled and (3) dynamically (scene) control processing.
In feed forward control is handled; With after the substrate transport of developing is in etching system 440-B; In etching system 440-B, pass through the live width that wire width measuring device 402-B measures the resist pattern, and calculate the suitable condition that is provided with, such as the flow velocity of etching gas based on measured live width.Afterwards, in etching system 440-B, adjust the suitable condition that is provided with for etch processes.
In feedback control is handled, through the live width of wire width measuring device 402-B measurement resist pattern, and based on the measured suitable condition that is provided with of live width calculating, such as the flow velocity of etching gas.Therefore, can make the etch processes optimization that is used for another substrate through under the suitable condition that is provided with, carrying out etch processes.
In dynamically (scene) control is handled, measure the live width of resist pattern through wire width measuring device 402-B, and in etching treatment procedure, dynamically adjust the suitable condition that is provided with, such as the flow velocity of etching gas.Be to be understood that; In all above-mentioned control is handled; Use treatment condition DBs (not shown in Fig. 5) to calculate the suitable condition that is provided with through measured raw data, these treatment condition DBs have been stored various treatment condition in the storer of computingmachine 442-B.
According to an aspect of the present invention, possibly need etching multilayered structure continuously.In this embodiment, at first measure the live width of first patterned layer.Afterwards, for the second layer that is formed on the first layer below suitable etching condition is set.In next procedure, use optimized etching condition to come the second layer is carried out etching.Afterwards, measure the live width of second etch layer, and for the 3rd layer suitable etching condition is set afterwards.This processing can be proceeded for a plurality of layers in the multilayered structure.In this way, the live width (CD value) of final etched pattern is near the desired destination value.The measurement of live width (CD value) can be carried out through the wire width measuring device that is installed in the outer IM module of chamber or be installed in the chamber.Through being installed to the wire width measuring device of etching chamber, can after main etching (ME) is handled, measure CD and can adjust be used for etching (OE) processing preferred etching condition accurately to control CD.
As an example, the object construction shown in Fig. 1 10 can be considered to multilayered structure.In order to carry out the etch processes of processing each layer, that basis is described in the preceding paragraph, can understand following processing with reference to the structure of (Fig. 6): the first, from a plurality of HBr/O 2Ratio (condition) (shown in Figure 12) obtains the CD changing value (Δ CD) of unit time and it is stored as form.The second, measured the live width (CD) of Si-ARC layer 16b.In third step, calculate measured Si-ARC live width (CDs) and poor (CDt-CDs) between the live width target value (CDt).At last, obtain HBr/O based on poor (CDt-CDs) and time period that crosses etching (OE) of being used for ODL layer (T) 2The optimization flow velocity.Afterwards at optimized HBr/O 2Carry out etching under the flow velocity.In this way, the shape of the final ODL pattern 16a of acquisition is near target live width (CDt).Note, using photoresist mask 16c to come to optimize CF according to above-mentioned processing under the situation of etching Si-ARC layer 16b 4/ CHF 3Flow velocity, and the CF that is optimizing 4/ CHF 3Flow velocity is carried out etching down.The two changes the CD value flow rate (flow velocity) and etching period that also can be through the adjustment etching gas.
When the difference between the live width of the resist pattern on target CDt value and the measured Si-ARC layer 16b exceeds predetermined threshold amount (that is, adjustment capability (trim capability)), the flow velocity ratio (HBr/O in concrete example 2And CF 4/ CHF 3Ratio) can be optimized to when accomplishing Si-ARC and ODL layer, obtain target CDt value.When those skilled in the art through to beginning before the etching measured resist CD and target CD compare when estimating when the Si-ARC etch processes finishes, can not reach the estimating target value, can obtain predetermined threshold amount.In this way, when the etch processes of two successive layerss of Si-ARC and ODL is accomplished, can reach target value for live width.In the present embodiment, through considering that various parameters (such as the etching shape of, etching period and each layer) confirm HBr/O 2And CF 4/ CHF 3Flow velocity.In the present embodiment, be provided with the target value of Si-ARC live width and the target value of ODL live width in advance.
(3) independent wire width measuring device
Fig. 7 shows the synoptic diagram of embodiment of independent wire width measuring device 402-C that photo-resist forms the entire structure of device 40-C.As shown in the figure, the entire structure that photo-resist forms device 40-C and the structure of 40-A and 40-B are distinguished and are that wire width measuring device 402C is not integrated in any device and as independent measuring apparatus and carry out work.Other assembly is basic identical with the structure of 40-A.In the present embodiment, used unshowned substrate container (being commonly referred to as FOUP) in Fig. 7.Each substrate can or be transferred in the container after etch processes after development treatment, and for example use guides transportation means (AGV) automatically and is transferred to wire width measuring device 402-C.In each substrate, at first measure the live width of each substrate, and calculate the suitable condition that is provided with afterwards.Measured CD value and the suitable condition that is provided with are sent to etching system 440.
Test sample:
In order to assess the influence of hydrogen bromide (HBr), and also in order to set up the processing that is used for Control Critical size (CD), several test samples that have like Fig. 1 or same target structure shown in Figure 2 have been made for the sidewall protection mechanism.Test sample receives according to plasma etch process of the present invention afterwards, and wherein in etching (OE) step excessively of organic dielectric layer (ODL), the hydrogen bromide of appropriate amount (HBr) is added to nitrogen and oxygen (N 2/ O 2) mixed atmosphere in.Hereinafter, result that will these assessments of specific explanations.
With reference to Fig. 8, after each the concrete layer place of object construction at them carries out plasma etch process, show the sectional view of two test samples.The first test sample characteristic is intensive or nested array pattern, and second test sample is represented isolated pattern.The sectional view of these two patterns is illustrated in upside and the downside of Fig. 8 respectively.As shown in the figure, after carrying out etching step, obtain sectional view for each mask layer.For these two test samples, the row 1-5 of their sectional view corresponds respectively to resist pattern, Si-ARC pattern, ODL master's etching (ME) pattern, ODL and crosses etching (OE) pattern and hard mask SiN pattern.Table I has been summed up the etching condition that is applied to each mask layer.
Table I: the etching condition that is used for test sample
Figure BPA00001443590100141
As shown in Figure 8, critical size (CD) reduces in Si-ARC and ODL master's etching (ME) step.Through adding hydrogen bromide (HBr) to nitrogen and oxygen (N crossing in etching (OE) step of ODL layer 2/ O 2) mixed atmosphere in, critical size intensive and isolated pattern can increase.As shown in Figure 8, the critical size (CD) that ODL crosses the closely spaced array pattern in etching (OE) layer is about 46nm, and the critical size of the isolated patterns in identical layer (CD) is about 115nm.Think that the increase of critical size (CD) is because thin bromination carbon (CBr x) layer deposition, this layer is protected as sidewall for etching.
After carrying out hard mask SiN etching step, final critical size (CD) is 40nm for intensive pattern and is 119nm for isolated patterns.Adjustment capability is after carrying out etching step, makes critical size (CD) thickening of mask layer or the scope of attenuation through adjustment flow conditions (gas ratio, overall flow rate etc.).Fig. 8 shows the CD value and in intensive (nested) pattern and isolated patterns, changes.
Hereinafter, studied the influence of each parameter (for example, HBr flow velocity, the temporal correlation of crossing etching (OE) step, etching gas type and composition ratio) for the critical size (CD) of ODL layer.For this purpose, various test samples under different etching conditions, have been formed with intensive (nested) and isolated patterns.Only if hereinafter describe in addition, following etching condition is used to the ODL layer of each test sample is carried out patterning: the pressure of (1) main etching (ME) condition: 10mTorr, the N of 400sccm/20sccm 2/ O 2Flow velocity, the microwave power of 3kW, main etching (ME) time period of the RF power of 200W and 40 seconds; And the pressure of etching (OE) condition: 10mTorr, the N of 400sccm/4sccm are crossed in (2) 2/ O 2Flow velocity, the RF power of the microwave power of 3kW and 200W.
In order to assess critical size (CD) and the dependency of crossing the etching period section, two groups of test samples have been made.In every group, formed test sample with same mask pattern.Similar with afore-mentioned, the characteristic of first group of test sample is the closely spaced array pattern, and second group of test sample represented isolated patterns.In plasma treatment appts 30, carry out the main etching (ME) of ODL layer and cross etching (OE).The main etching (ME) that is used for the ODL layer is carried out patterning with cross etching (OE) condition with describe at the preceding paragraph identical.For this assessment, the HBr flow velocity is set to 60sccm.In addition, in every group, in following crossing under the processing of etching (OE) time three test samples are carried out patterning: 0 second, 20 seconds and 40 seconds.
Fig. 9 representes the sectional view of test sample and with the critical size (CD) of crossing etching (OE) time processing variation.As shown in the figure, can handle and made that critical size (CD) was thicker through prolonging etching (OE) time.Can expect that this prolongation that mainly was due to the fact that etching (OE) time period has increased byproduct of reaction (for example, the bromination carbon (CBr on the ODL pattern x)) deposition.
Afterwards with reference to Figure 10, show the sectional view of test sample and with the critical size (CD) of HBr change in flow.With formerly embodiment is similar, formed two groups of samples that all have three samples, these samples have similar pattern.The characteristic of first group of test sample is intensive (nested) array pattern, and second group of test sample represented isolated patterns.In plasma treatment appts 30, carry out the main etching (ME) of ODL layer and cross etching (OE).The main etching (ME) that is used for the ODL layer is carried out patterning with cross etching (OE) condition identical with in the 15th page the 2nd section description of this specification sheets.For this assessment, cross etching (OE) time treatment condition and all be set to 20 seconds.In addition, each in every group three test samples is all carried out patterning: 0sccm, 60sccm and 120sccm respectively under following HBr flow conditions.
Shown in figure 10, critical size (CD) increases along with the increase of HBr flow velocity.The mechanism that can expect being used to control the critical size (CD) of ODL layer is described below: through at nitrogen and oxygen (N 2/ O 2) mixture in add hydrogen bromide (HBr), hydrogen (H) has reduced the oxygen (O) in the surface of ODL layer.In other words, oxygen (O) atom is extracted from ODL.Therefore, produced the organic dielectric layer (ODL) that has high carbon content on the surface.Therefore C-C increases, and this makes that organic dielectric layer (ODL) is more firm.The firmness of ODL layer plays a role as sidewall protection, and therefore this prevented etching.
On the other hand, the high-carbon content that also can expect the ODL layer has increased the bromo-carbon bond at the near surface of ODL pattern.Also we can say the thin layer bromination carbon (CBr that is deposited on ODL pattern top x) play a role as sidewall protection, therefore this prevented etching.Through increasing hydrogen bromide (HBr) flow velocity, bromination carbon (CBr x) deposition increase owing to the increase of Br nucleic, this then cause the critical size (CD) of ODL to increase.On the other hand, through reducing the HBr flow velocity, the CD thickening becomes littler.In this way, can realize better controllability for the preset value that obtains critical size (CD).
Can use the etching gas of other types to control the critical size (CD) of ODL layer, such as chlorine (Cl 2).For the etching gas of assessing another kind of type is the controllability that how to influence critical size (CD), two groups of test samples have been made.In every group, two test samples have been formed with same mask pattern.With formerly embodiment is similar, the characteristic of first group of test sample is the closely spaced array pattern, and second group of test sample represented isolated patterns.In every group, first and second test samples at first receive main etching (ME) step under the etching condition identical with the etching condition of the 15th page of the 2nd section description of this specification sheets.Receive through hydrogen bromide (HBr) is added at nitrogen and oxygen (N after every group first test sample 2/ O 2) mixture in and carry out cross etching (OE) step.Yet every group second test sample receives through with chlorine (Cl 2) add at nitrogen and oxygen (N 2/ O 2) mixture in and carry out cross etching (OE) step.For ease, HBr and CL 2Flow velocity all be set to 60sccm.In addition, in each test group, cross etching (OE) time treatment condition and be set to 20 seconds.
Figure 11 shows the sectional view for the test sample of various etching gas types.As shown in the figure, for these two kinds of etching gas types (HBr and Cl 2), the critical size (CD) of the ODL layer in crossing etching (OE) step has increased than main etching (ME) step.Though at chlorine (Cl 2) situation under to be used for controlling the accurate mechanism of critical size (CD) of ODL layer also unknown, but about the similar result that had increased access to of critical size (CD).Yet, in this embodiment, observe other unfavorable result.For example, the hard mask silicon nitride of lower floor (SiN) layer is cut to be scraped, and makes the height of its mask descend (gradually thin shape).
In alternative embodiment, through at argon gas and oxygen (Ar/O 2) mixed atmosphere in add hydrogen bromide (HBr) and realize the critical size (CD) expected.In alternative embodiment, argon oxygen (Ar/HBr/O 2) series is used to carry out ODL master's etching (ME) step.With formerly embodiment is similar, formed two groups of test samples that all have three samples, these samples have similar pattern.The characteristic of first group of test sample is the closely spaced array pattern, and second group of test sample represented isolated patterns.More specifically, the small pieces substrate (section substrate, also be known as section) that has a structure shown in Fig. 1 is used in this test.When carrying out Si-ARC and ODL master's etching (ME), section is fixed on the substrate of complete painting photoresist on it.When execution ODL crossed etching (OE), section was fixed on another substrate of complete deposited silicon nitride (SiN) on it.ODL crosses etching (OE) and carried out 15 seconds.Table I I has summed up the etching condition at Si-ARC and ODL layer place.
Table I I: the etching condition that is used for test sample
After carrying out Si-ARC and ODL master's etching (ME) step, use plasma treatment appts 30 to carry out etching (OE) and handle.Etching (OE) step excessively of first, second of every group and the 3rd test sample is respectively at following Ar/HBr/O 2100/150/20,100/150/10,100/150/5sccm carries out under the flow velocity:.
Afterwards with reference to Figure 12, show the sectional view of test sample and with HBr/O 2The critical size of ratio vary (CD).As shown in the figure, the critical size of ODL layer (CD) is along with HBr/O 2The increase of ratio and increasing.In other words, the critical size of ODL layer (CD) is at oxygen (O 2) increase when flow velocity reduces.
In traditional plasma etch process, there is such problem: after carrying out etching step, in pattern form, have some variations.For fear of the variation of pattern form, the variation of the size through the etched pattern considering to be accomplished is designed for the mask of photoetching purpose.Yet, can not avoid the problems referred to above fully through this solution.
Plasma etch process of the present invention provides the solution that is used for the problems referred to above.Through at N 2/ O 2Or Ar/O 2Mixture in add hydrogen bromide (HBr), can expect that hydrogen (H) has reduced the oxygen (O) in the surface of ODL layer.In other words, oxygen (O) atom is extracted from ODL.Therefore, produced the organic dielectric layer (ODL) that has high carbon content on the surface.Therefore C-C increases, and this makes that organic dielectric layer (ODL) is more firm.The firmness of ODL layer plays a role as sidewall protection, and therefore this prevented etching.
In addition, the high-carbon content that also can expect the ODL layer has increased the bromo-carbon bond at the near surface of ODL pattern.Therefore, above the ODL pattern, deposited thin layer bromination carbon (CBr x), it plays a role as sidewall protection.The lateral etches direction that therefore, can suppress the ODL layer.In addition, through increasing hydrogen bromide (HBr) flow velocity, bromination carbon (CBr x) deposition increase owing to the increase of Br nucleic, this has increased the critical size (CD) of ODL.On the other hand, through reducing the HBr flow velocity, CD thickening speed becomes littler.In this way, through selecting appropriate H Br flow velocity, can realize better controllability for the preset value that obtains critical size (CD).
In order to assess the variation of pattern form and their critical dimension homogeneity, made two groups of test samples, every group of sample all has different pattern (pattern of intensive (being also referred to as " nested ") and isolated pattern).In every group, two test samples have been formed with similar pattern.Table I II has summed up the etching condition in each mask layer that is used in test sample.
Table I II: the etching condition that is used for test sample
For this test, the etching period in Si-ARC and ODL master's etching (ME) step is set to 16 and 40.8 seconds respectively.In crossing etching (OE) step, the etching period that is used for a test sample is set to 20 seconds, and is set to 40 seconds for the etching period of another test sample.
Figure 13 shows the sectional view and their critical size (CD) of test sample.For each test sample, got sectional view along central authorities and edge (they are defined as " central authorities " and " edge " respectively in Figure 13) of substrate respectively.As shown in the figure, do not depend on the processing of etching (OE) time for all sample critical sizes (CD).In addition, on all samples, all not observing pattern form changes.
That Figure 14 shows is time dependent, microwave power, RF power and the RF voltage of each mask layer.Transverse axis is represented the treatment time, and left length axis is represented microwave power and RF substrate bias power, and right length axis is represented the RF bias voltage.This test for data shown in Figure 14 is represented such example: the etching step of wherein in the same treatment container 120 of plasma processing apparatus 30, carrying out multilayered structure continuously.Should be noted that each treatment step begin to locate on microwave power be applied to δ (delta) function, generate to handle to light plasma body.
RF bias voltage (following Vpp) is applied to substrate keeper 140 from plasma processing apparatus (with reference to Fig. 3).As stated, this RF bias voltage control attracted to the ion energy of substrate.Shown in figure 14, the RF bias voltage is next mask layer and reducing along with etch processes proceeds to.Thus, the energy of ions of contact substrate is along with etch processes is carried out forward and reduced towards lower floor's mask layer.
In addition, observed another problem in traditional plasma etch process: resist pattern or the zone of intensive (nested) isolated and forming unevenly according to pattern.In other words, be isolated (being also referred to as coarse) or nested (being also referred to as meticulous) according to the resist pattern, there are some variations of pattern form.For fear of coarse and meticulous change in shape, change the mask that is designed for the photoetching purpose through considering these.Yet the problems referred to above can not be avoided through this solution fully.Also can observe variation coarse and precise shape takes place when Control Critical size (CD).
Can, treatment in accordance with the present invention avoid coarse and meticulous change in shape when carrying out patterning to the anti-reflection coating (Si-ARC) that contains silicon.In the present embodiment, through adjustment tetrafluoro-methane and trifluoromethane (CF 4/ CHF 3) ratio of gas, control live width or the critical size (CD) of final pattern (for example, hard mask SiN) via the Si-ARC layer.Through in the Si-ARC etching step, adjusting CF 4/ CHF 3Ratio, the critical size of Si-ARC pattern can be by thickening or attenuation, make with final critical size (CD) be controlled at pact-2nm arrive+scope of 10nm in.
The Si-ARC pattern is mainly by silicon (Si) and carbon (C) atomic building.The carbon content that can expect the Si-ARC layer helps on the surface of Si-ARC layer, to produce a plurality of carbon-fluorine bonds.Therefore, through the CF in the adjustment Si-ARC layer 4/ CHF 3Ratio is because CF 4Gas and CHF 3The difference of the bound energy of inter gas, CF xThe veneer of series membranes is on the Si-ARC pattern.Therefore, treatment in accordance with the present invention is through the CF in the adjustment Si-ARC etching step 4/ CHF 3Ratio can suppress the lateral etches direction of Si-ARC layer and can increase the critical size (CD) of Si-ARC pattern.
In order to assess etching step through the Si-ARC layer, various test samples have been made for the controllability of critical size (CD) and also in order to study coarse and meticulous change in shape.With formerly embodiment is similar, formed two test samples, they have different pattern (intensive pattern and isolated patterns) respectively.Table I V sums up the etching condition in each mask layer that is used in test sample.For this test, the etching period that Si-ARC, ODL master's etching (ME) step, ODL cross in etching (OE) step, SiN and the cineration step was set to respectively 17.7,40.8,20 and 30 seconds.In addition, CF 4/ CHF 3Ratio be set to 1 (180/180).
Table I V: the etching condition that is used for test sample
With reference to Figure 15, show the sectional view of test sample and their critical size (CD).Shown in figure 15, on all test samples, vertically very near 90 degree, this shows does not almost have coarse and meticulous change in shape to profile.In addition, the critical size of Si-ARC pattern (CD) on all test samples, show from expectation target pattern generating subtle change (± 0nm to ± 2nm).In this test, be set to 45nm and 75nm respectively with expectation target pattern isolated patterns for intensive.
Also changing CF for each test sample 4/ CHF 3Studied etching step through the Si-ARC layer during ratio for the controllability of critical size (CD) and coarse and meticulous change in shape.Equally, made two groups of test samples, they have different pattern (intensive pattern and isolated patterns) respectively.In every group, three test samples have been formed.Be used in etching condition in each mask layer of each test sample with in table I V, to sum up etching condition identical.Yet, in every group of test sample, for first, second and the 3rd test sample, CF 4/ CHF 3Ratio be set to (210/150), (180/180) and (150/210) respectively.
With reference to Figure 16, show the cross-sectional shape of test sample and their critical size (CD) afterwards.As shown in the figure, on all test samples, vertically very near 90 degree, this shows does not almost have coarse and meticulous change in shape to profile.In addition, the critical size of Si-ARC pattern (CD) on all test samples, show from initial target pattern generating subtle change (3nm to ± 12nm).Maximum variation about pattern is+2nm.In this test, be set to 45nm and 75nm respectively with initial target pattern isolated patterns for intensive.
Though combine concrete equipment/apparatus and method to describe principle of the present disclosure in the preceding text, can understand clearly that these descriptions are only as an example and not as the restriction of scope of the present invention.

Claims (19)

1. method that substrate is handled, the pattern that it is used for after on said substrate, forming mask pattern forming through etch processes expectation said method comprising the steps of:
On said substrate, form two layers, said two layers comprise silicon nitride layer and organic dielectric layer;
Measure in said mask pattern or said two layers width of one etched pattern; And
Adjust in HBr and other gases any one flow velocity based on measured width, HBr and said other gases are used in the said etch processes.
2. method according to claim 1, further comprising the steps of: based on the width of measured said mask pattern and under the flow velocity of adjusting, one in two layers of same substrate are carried out etching.
3. method according to claim 1, further comprising the steps of: based on the width of measured said mask pattern or said etched pattern and under the flow velocity of adjusting, one in two layers of another substrate are carried out etching.
4. method according to claim 1; Further comprising the steps of: and under the flow velocity of adjusting based on the width of measured said etched pattern; In two layers of same substrate one are carried out etching, wherein, during said etch processes, carry out said measuring process and said set-up procedure.
5. method according to claim 1; Wherein, Said set-up procedure comprises: when measured width increases the flow velocity ratio of HBr and said other gases during less than desired width, and reduce the flow velocity ratio of HBr and said other gases during greater than desired width when measured width.
6. method according to claim 2 wherein, is carried out etching to said organic dielectric layer in said etching step.
7. method according to claim 6, wherein, said set-up procedure comprises: when measured width increases etching period during less than desired width, and reduce etching period during greater than desired width when measured width.
8. method according to claim 6, wherein, said etching step comprises the etching excessively after main etching and the said main etching, and HBr is used in said the mistake in the etching.
9. method according to claim 8, wherein, said set-up procedure comprises: when measured width increases etching period during less than desired width, and reduce etching period during greater than desired width when measured width.
10. method according to claim 1, wherein, said set-up procedure comprises: when measured width increases the RF substrate bias power that is applied to said substrate during less than desired width, and reduce the RF substrate bias power during greater than desired width when measured width.
11. method according to claim 1, wherein, said other gases comprise N 2And O 2
12. method according to claim 1, wherein, said other gases comprise Ar and O 2
13. the method that substrate is handled, the pattern that it is used for after on said substrate, forming mask pattern forming through etch processes expectation said method comprising the steps of:
On said substrate, form three layers, said three layers comprise silicon nitride layer, organic dielectric layer and contain the anti-reflection coating of silicon;
Measure in said mask pattern or said three layers width of one etched pattern; And
Width based on measured is adjusted CF 4And CHF 3In any one flow velocity, CF 4And CHF 3Be used in the said etch processes.
14. method according to claim 13 is further comprising the steps of: based on the width of measured said mask pattern and under the flow velocity of adjusting, one in three layers of same substrate are carried out etching.
15. method according to claim 13 is further comprising the steps of: based on the width of measured said mask pattern or said etched pattern and under the flow velocity of adjusting, one in three layers of another substrate are carried out etching.
16. method according to claim 13; Further comprising the steps of: and under the flow velocity of adjusting based on the width of measured said etched pattern; In three layers of same substrate one are carried out etching; Wherein, during said etch processes, carry out said measuring process and said set-up procedure.
17. method according to claim 13 is further comprising the steps of: based on the width of measured said mask pattern and under the flow velocity of adjusting, the said anti-reflection coating that contains silicon is carried out etching.
18. method according to claim 13, wherein, said set-up procedure comprises: when measured width increases CF during greater than desired width 4With CHF 3The flow velocity ratio, and reduce CF during less than desired width when measured width 4With CHF 3The flow velocity ratio.
19. method according to claim 13, wherein, said set-up procedure comprises: when measured width increases the RF substrate bias power that is applied to said substrate during less than desired width, and reduce the RF substrate bias power during greater than desired width when measured width.
CN2010800139349A 2009-03-24 2010-03-24 Plasma etching method Pending CN102365392A (en)

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