CN102339734A - Production method of cylindrical semiconductor device with cross section being circular ring - Google Patents

Production method of cylindrical semiconductor device with cross section being circular ring Download PDF

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Publication number
CN102339734A
CN102339734A CN2010102331960A CN201010233196A CN102339734A CN 102339734 A CN102339734 A CN 102339734A CN 2010102331960 A CN2010102331960 A CN 2010102331960A CN 201010233196 A CN201010233196 A CN 201010233196A CN 102339734 A CN102339734 A CN 102339734A
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layer
etching
many
amorphous silicon
silicon nitride
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CN102339734B (en
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洪中山
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

The invention provides a production method of a cylindrical semiconductor device with a cross section being a circular ring, which comprises the following steps that: firstly a silicon nitride layer is adopted as a mask to define the outer diameter of the circular ring, then a polycrystalline silicon layer or an amorphous silicon layer below the silicon nitride layer is oxidized, and the diameter width of the polycrystalline silicon layer or the amorphous silicon layer which is not oxidized below the silicon nitride layer is adopted as an inner-diameter width of the circular ring. The cylindrical semiconductor device with the cross section being the circular ring is finally formed through the etching technology. By adopting the method, a cylindrical graph with the cross section being the circular ring can be simply and accurately realized.

Description

The cross section is the manufacture method of the cylindrical semiconductor device of annulus
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of cross section is the manufacture method of the cylindrical semiconductor device of annulus.
Background technology
Magnetic RAM (MRAM) is a kind of nonvolatile memory, and it has for example incomparable advantages such as dynamic random access memory (DRAM), flash memory of legacy memory in many application.The magnetic memory cell of MRAM is MTJ (MTJ), and existing MTJ is a solid cylinder, shows through research, and MTJ is made into the cylinder that the cross section is an annulus, then can improve the electric property of MRAM greatly.Fig. 1 is the cylinder semiconductor device schematic perspective view of annulus for the cross section.Therefore, not only for MTJ, comprising that other need be made into the cylindrical semiconductor device that the cross section is an annulus, how to realize the pattern of this semiconductor device, is the problem that semiconductor manufacturing industry is being paid close attention to.
Summary of the invention
In view of this, the technical problem of the present invention's solution is: how making the cross section is the cylinder semiconductor device of annulus.
For solving the problems of the technologies described above, technical scheme of the present invention specifically is achieved in that
The invention discloses the manufacture method that a kind of cross section is the cylindrical semiconductor device of annulus, this method comprises:
Deposition-etch destination layer, many/amorphous silicon layer and silicon nitride layer successively on Semiconductor substrate; Said many/implication of amorphous silicon layer is polysilicon layer or amorphous silicon layer;
At the surface coated photoresistance glue-line of silicon nitride layer, and the said photoresistance glue-line of exposure imaging patterning, the photoresistance glue-line of said patterning is cylindrical, is used to define the external diameter width of annulus;
Photoresistance glue-line with patterning is a mask, and the said silicon nitride layer of etching forms the cylindrical silicon nitride layer of patterning;
After removing the photoresistance glue-line, be mask, many/amorphous silicon layer is carried out the silicon oxide layer that oxidation formation has first desired depth with the cylindrical silicon nitride layer of patterning; Wherein, the diameter width that is positioned at the not oxidized many/amorphous silicon layer in the below of cylindrical silicon nitride layer of patterning is the internal diameter width of annulus;
Cylindrical silicon nitride layer with said patterning is a mask, the silicon oxide layer that anisotropic etching has first desired depth is many to manifesting/and amorphous silicon layer;
After removing the cylindrical silicon nitride layer of said patterning, manifesting silicon oxide layer and not oxidized many/amorphous silicon layer under the cylindrical silicon nitride layer that is positioned at said patterning, anisotropic etching is many/and amorphous silicon layer is to manifesting etching target; The width of the said silica that manifests is the width of annulus, and the width of said annulus is the internal diameter width that the external diameter width of annulus deducts annulus;
With the silicon oxide layer that manifests is that mask carries out etching to etching target, and forming the cross section is the cylindrical semiconductor device of annulus.
Behind the said removal photoresistance glue-line; Cylindrical silicon nitride layer with patterning is a mask; Many/amorphous silicon layer is carried out oxidation to be formed and to have before the silicon oxide layer of first desired depth; This method further comprises: the cylindrical silicon nitride layer with patterning is a mask, etching is many/and the step of amorphous silicon layer to the second desired depth;
Said first desired depth is greater than second desired depth.
Said etching is many/and amorphous silicon layer is isotropic etching or anisotropic etching;
Said isotropic etching is many/and the gas of amorphous silicon layer comprises carbon tetrafluoride CF 4, sulphur hexafluoride SF 6Or Nitrogen trifluoride NF 3In a kind of, perhaps several kinds combination in any;
Said anisotropic etching is many/and the gas of amorphous silicon layer comprises CF 4, hydrogen bromide HBr or chlorine Cl 2In a kind of, perhaps several kinds combination in any.
The said method that is oxidized to thermal oxidation or plasma assisted oxidation.
Said anisotropic etching is many/and amorphous silicon layer to the etching gas that manifests etching target comprises hydrogen bromide HBr or chlorine Cl 2In a kind of, perhaps two kinds combination, when this etching gas carries out etching to many/amorphous silicon layer, can the etching oxidation silicon layer.
Between many/amorphous silicon layer of deposition and silicon nitride layer, this method further comprises the step of many/amorphous silicon layer being carried out ammonia annealing.
Visible by above-mentioned technical scheme; The present invention at first is the external diameter of mask definition annulus with the silicon nitride layer; Then polysilicon layer under it or amorphous silicon layer are carried out oxidation, the polysilicon layer that mask silicon nitride layer below is not oxidized or the diameter width of amorphous silicon layer are as the internal diameter width of annulus.In this process, utilize lithographic technique finally to form the cylindrical semiconductor device of cross section for annulus.Adopt method of the present invention can realize exactly simply that the cross section is the cylinder pattern of annulus; Even requiring under the very little situation of size of semiconductor device; Method of the present invention still can realize; Because method of the present invention does not rely on lithographic equipment, not can because of lithographic feature size near in addition surpassed the physics limit of optical lithography, and make lithographic equipment obtain the littler semiconductor pattern of size by exposure imaging.
Description of drawings
Fig. 1 is the cylinder semiconductor device schematic perspective view of annulus for the cross section.
Fig. 2 makes the method flow sketch map that the cross section is the cylindrical semiconductor device of annulus for the present invention.
Fig. 2 a to Fig. 2 g makes the concrete generalized section that the cross section is the cylindrical semiconductor device of annulus for the present invention.
Fig. 3 a to Fig. 3 h is that preferred embodiment of the present invention making cross section is the concrete generalized section of the cylindrical semiconductor device of annulus.
Embodiment
For make the object of the invention, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, to further explain of the present invention.
It is that the method flow sketch map of cylindrical semiconductor device of annulus is as shown in Figure 2 that the present invention makes the cross section, and it may further comprise the steps, and describes below in conjunction with Fig. 2 a to Fig. 2 g.
Step 21, see also Fig. 2 a, deposition-etch destination layer 101, polysilicon layer 102 and silicon nitride layer 103 successively on Semiconductor substrate 100.
Polysilicon layer 102 can also replace with amorphous silicon among the present invention; Why adopt polysilicon or amorphous silicon; Be because the lattice that it has well and levels is mated; And follow-up when polysilicon or amorphous silicon are carried out oxidation, have oxidation effectiveness preferably, make that polysilicon or amorphous silicon can be by oxidations equably.Adopt silicon nitride layer 103 among the present invention, follow-up when aerating oxygen carries out oxidation to polysilicon layer 102 in reaction chamber, silicon nitride character is more stable, can guarantee that silicon nitride layer is not oxidized in the oxidation polysilicon;
Step 22, see also Fig. 2 b, at the surface coated photoresistance glue-line 104 of silicon nitride layer 103, and the said photoresistance glue-line 104 of exposure imaging patterning, the photoresistance glue-line 104 of said patterning is cylindrical, its columniform diameter has defined the outer diameter A of annulus;
Step 23, seeing also Fig. 2 c, is mask with the photoresistance glue-line 104 of patterning, and the said silicon nitride layer 103 of etching forms the cylindrical silicon nitride layer 103 of patternings.
The gas of etch silicon nitride layer 103 is mainly carbon tetrafluoride (CF 4);
Step 24, see also Fig. 2 d, remove photoresistance glue-line 104 after, be mask with the cylindrical silicon nitride layer 103 of patterning, polysilicon layer 102 is carried out oxidation forms silicon oxide layer 105 with first desired depth.Being specially aerating oxygen in reaction chamber, is silica with polysilicon oxidation, and the volume of therefore original polysilicon can increase, the height of silicon nitride layer 103 bottom surfaces of a little higher than patterning of height meeting of silica.The method of oxidation has multiple, can be thermal oxidation, also can be the plasma assisted oxidation.After the oxidation, be positioned at the below of the cylindrical silicon nitride layer 103 of patterning, remain in the internal diameter that the width B of polysilicon layer 102 transversely is annulus.
Polysilicon layer 102 is carried out oxidation, make to remain in transversely after the oxidation that the diameter of polysilicon layer 102 is B, can control through predetermined oxidization time and predetermined oxygen flow.Under the situation that the annulus outer diameter A is confirmed, the amount of aerating oxygen is big more, and oxidization time is long more, and the B of formation is then more little.Specifically, at first select a slice to need the testing wafer (wafer) of oxidation, be formed with the structure identical on this wafer with the product wafer.Wherein, the product wafer is the wafer of the device that distributed on it, and finally can pass through multiple working procedure becomes finished product; Though and the testing wafer test structure is identical with the product wafer, after test, go out of use.Testing wafer carries out test of many times when oxidation; Preestablish oxidization time and oxygen flow at every turn; And the wafer after the oxidation is inserted the measurement board carry out dimensional measurement; Time and flow when finally reaching preset width B are as with batch predetermined oxidization time and the oxygen flow of wafer in this step;
Step 25, seeing also Fig. 2 e, is mask with the cylindrical silicon nitride layer 103 of said patterning, anisotropic etching silicon oxide layer 105 to polysilicon layer 102;
Step 26, see also Fig. 2 f, remove the cylindrical silicon nitride layer 103 of patterning after, anisotropic etching polysilicon layer 102 is to manifesting etching target 101, the cylinder mask that formed cross section of wanting required for the present invention this moment is annulus.After the cylindrical silicon nitride layer 103 of patterning is removed; Polysilicon layer 102 all reveals with silicon oxide layer 105; So this step adopts etch polysilicon to carry out etching with the selection of silica than very high gas; Select than generally reaching tens even hundreds of, promptly the etching polysilicon time, basically can etching oxidation silicon.Etching gas generally adopts a kind of in chlorine or the hydrogen bromide, perhaps two kinds combination.Wherein, the width of the silicon oxide layer that manifests is the width of annulus, and this width equals outer diameter A-internal diameter B;
Step 27, seeing also Fig. 2 g, is mask with above-mentioned pattern, and etching target 101 is carried out etching, and forming cross section of the present invention is the cylinder semiconductor device of annulus.This step is transferred to mask on the etching target 101 exactly.
So far, cross section of the present invention is the cylinder semiconductor device formation of annulus.
Above-mentioned in step 24; Accurate control to polysilicon layer 102 oxidations; Determined the width and the internal diameter of annulus, more accurate for the size that makes annulus, the preferred embodiment of the present invention is after step 24 is removed photoresistance glue-line 104; Polysilicon layer 102 is carried out before the oxidation, added the step of etch polysilicon layer 102.
It is the method for the cylinder semiconductor device of annulus that the preferred embodiment of the present invention is made the cross section, may further comprise the steps, and describes below in conjunction with Fig. 3 a to Fig. 3 h.
Step 31, see also Fig. 3 a, deposition-etch destination layer 101, polysilicon layer 102 and silicon nitride layer 103 successively on Semiconductor substrate 100.
Polysilicon layer 102 can also replace with amorphous silicon among the present invention; Why adopt polysilicon or amorphous silicon; Be because the lattice that it has well and levels is mated; And follow-up when polysilicon or amorphous silicon are carried out oxidation, have oxidation effectiveness preferably, make that polysilicon or amorphous silicon can be by oxidations equably.Adopt silicon nitride layer 103 among the present invention, follow-up when aerating oxygen carries out oxidation to polysilicon layer 102 in reaction chamber, silicon nitride character is more stable, can guarantee that silicon nitride layer is not oxidized in the oxidation polysilicon;
Step 32, see also Fig. 3 b, at the surface coated photoresistance glue-line 104 of silicon nitride layer 103, and the said photoresistance glue-line 104 of exposure imaging patterning, the photoresistance glue-line 104 of said patterning is cylindrical, its columniform diameter has defined the outer diameter A of annulus;
Step 33, seeing also Fig. 3 c, is mask with the photoresistance glue-line 104 of patterning, and the said silicon nitride layer 103 of etching forms the cylindrical silicon nitride layer 103 of patternings.
The gas of etch silicon nitride layer 103 is mainly CF 4
Step 34, see also Fig. 3 d, remove photoresistance glue-line 104 after, be mask with the cylindrical silicon nitride layer 103 of patterning, etch polysilicon layer 102 to second desired depth.
Wherein, can be isotropic etching to the etching of polysilicon layer 102, the etching of the certain width and the degree of depth is promptly all arranged on horizontal and vertical, etching gas can comprise carbon tetrafluoride (CF 4), sulphur hexafluoride (SF 6) or Nitrogen trifluoride (NF 3) in a kind of, or above-mentioned several kinds combination in any; Also can be anisotropic etching, the etching of certain depth is promptly only arranged in the vertical, etching gas can comprise CF 4, hydrogen bromide (HBr) or chlorine (Cl 2) in a kind of, or above-mentioned several kinds combination in any.
Also is to control through predetermined etch period for polysilicon layer 102 in the etching size on horizontal perhaps vertical.Testing wafer carries out test of many times when etching; Preestablish etch period at every turn and carry out etching; And the wafer after the etching inserted measure board and carry out dimensional measurement, the etch period when finally reaching predetermined etching size is as with batch predetermined etch period of wafer in this step.
In this step after the control etching transverse width L of polysilicon layer 102 account for patterning silicon nitride layer 103 width 1/2～1.Vertical depth H during control etch polysilicon layer 102 accounts for 0～1 of polysilicon layer 102 height.If incorgruous etching; Then etching can be to horizontal extension; Be etching only along the cylindrical silicon nitride layer 103 downward etchings of patterning, can not etch into polysilicon partly under the cylindrical silicon nitride layer 103 of patterning, L is identical with cylindrical silicon nitride layer 103 width B of patterning; If lateral etching, then etching is not only carried out downwards along the cylindrical silicon nitride layer 103 of patterning, and can etch into the polysilicon of part under the cylindrical silicon nitride layer 103 of patterning, makes L reduce.The width of L can not be too narrow, otherwise the back extended meeting is with the whole oxidations of the polysilicon in the L width; And H can have certain numerical value, and when H was big, the size in the time of can making subsequent oxidation is rule more, thus the characteristic size (CD) of etch polysilicon in the controlled step 27 more accurately;
Step 35, seeing also Fig. 3 e, is mask with the cylindrical silicon nitride layer 103 of patterning, polysilicon layer 102 is carried out oxidation form the silicon oxide layer 105 with first desired depth.Being specially aerating oxygen in reaction chamber, is silica with polysilicon oxidation, and the volume of therefore original polysilicon can increase, and silica is filled the sunk part of etching in the step 34 full.The method of oxidation has multiple, can be thermal oxidation, also can be the plasma assisted oxidation.After the oxidation, be positioned at the below of the cylindrical silicon nitride layer 103 of patterning, remain in the internal diameter that the width B of polysilicon layer 102 transversely is annulus.
Be oxidized to silicon oxide layer for polysilicon layer 102, can control through predetermined oxidization time with first desired depth.Owing to have on the basis of second desired depth at the etch polysilicon layer, carry out oxidation, so first desired depth is greater than second desired depth of etching;
Step 36, seeing also Fig. 3 f, is mask with the cylindrical silicon nitride layer 103 of said patterning, anisotropic etching silicon oxide layer 105 to polysilicon layer 102;
Step 37, see also Fig. 3 g, remove the cylindrical silicon nitride layer 103 of patterning after, anisotropic etching polysilicon layer 102 is to manifesting etching target 101, the cylinder mask that formed cross section of wanting required for the present invention this moment is annulus.After the cylindrical silicon nitride layer 103 of patterning is removed; Polysilicon layer 102 all reveals with silicon oxide layer 105; So this step adopts etch polysilicon to carry out etching with the selection of silica than very high gas; Select than generally reaching tens even hundreds of, promptly the etching polysilicon time, basically can etching oxidation silicon.Etching gas generally adopts a kind of in chlorine or the hydrogen bromide, perhaps two kinds combination.Wherein, the width of the silicon oxide layer that manifests is the width of annulus, and this width equals outer diameter A-internal diameter B;
Step 38, seeing also Fig. 3 h, is mask with above-mentioned pattern, and etching target 101 is carried out etching, and forming cross section of the present invention is the cylinder semiconductor device of annulus.This step is transferred to mask on the etching target 101 exactly.
So far, the cross section of the preferred embodiment of the present invention is the cylinder semiconductor device formation of annulus.
Between deposit spathic silicon layer 102 and silicon nitride layer 103, may further include the step of polysilicon layer 102 being carried out ammonia annealing.During oxidation polysilicon layer 102; Owing to have grain structure in the polysilicon layer 102; And the oxidation rate of locating at granule boundary (grain boundary) is more a lot of soon than the oxidation rate of granule interior, so adopt ammonia that polysilicon layer 102 is annealed, helps reducing the oxidation at granule boundary place; Make the oxidation rate in the polysilicon layer 102 reach unanimity, form uniform silicon oxide layer.For amorphous silicon, the method for above-mentioned ammonia annealing stands good.
Between deposition-etch destination layer 101 and polysilicon layer 102, may further include the step that deposition forms hard mask layer; Hard mask layer can be silicon nitride, silicon oxynitride etc.; Have certain rigidity, be used to protect the uniformity of etching target 101 etching size.If between etching target 101 and polysilicon layer 102, add hard mask layer, then remove silicon nitride layer 103 after, etch polysilicon layer 102 is etched to hard mask layer then and manifests etching target 101 to manifesting hard mask layer.
In sum, cross section of the present invention is the formation method of the cylindrical semiconductor device of annulus, and crucial is; Polysilicon or amorphous silicon are carried out oxidation; Adopt silica as mask pattern, the circular mask that forms is transferred on the destination layer, thereby formed above-mentioned pattern.
The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being made, is equal to replacement, improvement etc., all should be included within the scope that the present invention protects.

Claims (6)

1. manufacture method that the cross section is the cylindrical semiconductor device of annulus, this method comprises:
Deposition-etch destination layer, many/amorphous silicon layer and silicon nitride layer successively on Semiconductor substrate; Said many/implication of amorphous silicon layer is polysilicon layer or amorphous silicon layer;
At the surface coated photoresistance glue-line of silicon nitride layer, and the said photoresistance glue-line of exposure imaging patterning, the photoresistance glue-line of said patterning is cylindrical, is used to define the external diameter width of annulus;
Photoresistance glue-line with patterning is a mask, and the said silicon nitride layer of etching forms the cylindrical silicon nitride layer of patterning;
After removing the photoresistance glue-line, be mask, many/amorphous silicon layer is carried out the silicon oxide layer that oxidation formation has first desired depth with the cylindrical silicon nitride layer of patterning; Wherein, the diameter width that is positioned at the not oxidized many/amorphous silicon layer in the below of cylindrical silicon nitride layer of patterning is the internal diameter width of annulus;
Cylindrical silicon nitride layer with said patterning is a mask, the silicon oxide layer that anisotropic etching has first desired depth is many to manifesting/and amorphous silicon layer;
After removing the cylindrical silicon nitride layer of said patterning, manifesting silicon oxide layer and not oxidized many/amorphous silicon layer under the cylindrical silicon nitride layer that is positioned at said patterning, anisotropic etching is many/and amorphous silicon layer is to manifesting etching target; The width of the said silica that manifests is the width of annulus, and the width of said annulus is the internal diameter width that the external diameter width of annulus deducts annulus;
With the silicon oxide layer that manifests is that mask carries out etching to etching target, and forming the cross section is the cylindrical semiconductor device of annulus.
2. the method for claim 1; It is characterized in that; Behind the said removal photoresistance glue-line, be mask, many/amorphous silicon layer carried out oxidation form and have before the silicon oxide layer of first desired depth with the cylindrical silicon nitride layer of patterning; This method further comprises: the cylindrical silicon nitride layer with patterning is a mask, etching is many/and the step of amorphous silicon layer to the second desired depth;
Said first desired depth is greater than second desired depth.
3. method as claimed in claim 2 is characterized in that, and said etching is many/and amorphous silicon layer is isotropic etching or anisotropic etching;
Said isotropic etching is many/and the gas of amorphous silicon layer comprises carbon tetrafluoride CF 4, sulphur hexafluoride SF 6Or Nitrogen trifluoride NF 3In a kind of, perhaps several kinds combination in any;
Said anisotropic etching is many/and the gas of amorphous silicon layer comprises CF 4, hydrogen bromide HBr or chlorine Cl 2In a kind of, perhaps several kinds combination in any.
4. like claim 1,2 or 3 described methods, it is characterized in that the said method that is oxidized to thermal oxidation or plasma assisted oxidation.
5. method as claimed in claim 4 is characterized in that, and said anisotropic etching is many/and amorphous silicon layer to the etching gas that manifests etching target comprises hydrogen bromide HBr or chlorine Cl 2In a kind of, perhaps two kinds combination, when this etching gas carries out etching to many/amorphous silicon layer, can the etching oxidation silicon layer.
6. according to claim 1 or claim 2 method is characterized in that, between many/amorphous silicon layer of deposition and silicon nitride layer, this method further comprises carries out the step that ammonia is annealed to many/amorphous silicon layer.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104303273A (en) * 2012-06-12 2015-01-21 东京毅力科创株式会社 Etching method and plasma processing device
CN105719964A (en) * 2014-12-05 2016-06-29 中国科学院微电子研究所 Method of planarization
CN107851712A (en) * 2015-07-30 2018-03-27 斯平转换技术公司 For processing the polishing stop layer of semiconductor device array

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US6706571B1 (en) * 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
CN1619774A (en) * 2003-11-19 2005-05-25 旺宏电子股份有限公司 Semi conductor element having reduced spacing and its forming method
US20070170521A1 (en) * 2006-01-12 2007-07-26 International Business Machines Corporation Method and structure to process thick and thin fins and variable fin to fin spacing
KR100807074B1 (en) * 2005-11-24 2008-02-25 주식회사 하이닉스반도체 Method for fabrication a semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6706571B1 (en) * 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
CN1619774A (en) * 2003-11-19 2005-05-25 旺宏电子股份有限公司 Semi conductor element having reduced spacing and its forming method
KR100807074B1 (en) * 2005-11-24 2008-02-25 주식회사 하이닉스반도체 Method for fabrication a semiconductor device
US20070170521A1 (en) * 2006-01-12 2007-07-26 International Business Machines Corporation Method and structure to process thick and thin fins and variable fin to fin spacing

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104303273A (en) * 2012-06-12 2015-01-21 东京毅力科创株式会社 Etching method and plasma processing device
CN105719964A (en) * 2014-12-05 2016-06-29 中国科学院微电子研究所 Method of planarization
CN107851712A (en) * 2015-07-30 2018-03-27 斯平转换技术公司 For processing the polishing stop layer of semiconductor device array
CN107851712B (en) * 2015-07-30 2021-10-29 芯成半导体(开曼)有限公司 Polishing stop layer for processing semiconductor element array

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