CN102315117A - Etching method for Mo base/TaN metal grid lamination structure - Google Patents
Etching method for Mo base/TaN metal grid lamination structure Download PDFInfo
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- CN102315117A CN102315117A CN2010102233489A CN201010223348A CN102315117A CN 102315117 A CN102315117 A CN 102315117A CN 2010102233489 A CN2010102233489 A CN 2010102233489A CN 201010223348 A CN201010223348 A CN 201010223348A CN 102315117 A CN102315117 A CN 102315117A
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Abstract
The invention discloses an etching method for a Mo base/TaN metal grid laminated structure. The method comprises the steps of: firstly, sequentially forming an interface SiO2 layer, a high-K grid dielectric layer, a Mo-base metal grid, a TaN metal grid, a silicon grid layer and a hard mask layer on a semiconductor substrate; then performing photoetching and etching a hard mask; removing photoresist, and performing anisotropic etching with high selection ratio on the silicon grid layer by using a dry-mehtod etching process by using the hard mask for shielding, and performing anisotropic etching with high selection ratio on the TaN metal grid, the Mo-base metal grid and high-K dielectric by using a dry-method etching process. The etching method for the Mo base/TaN metal grid lamination structure, provided by the invention, meets the requirement for high-K/metal grid integration in a nanoscale CMOS (Complementary Metal Oxide Semiconductor) device, and provides necessary guarantee for the high-K/metal grid integration.
Description
Technical field
The present invention relates to the ic manufacturing technology field, relate in particular to the lithographic method of a kind of Mo base/TaN metal gate stack structure.
Background technology
Along with after the characteristic size of semiconductor device enters into the 45nm technology node; In order to reduce the grid tunnelling current; Reduce the power consumption of device; And eliminate thoroughly that B penetrates the integrity problem that causes in depletion of polysilicon effect and the P type metal-oxide semiconductor fieldeffect transistor (PMOSFET), and alleviate the fermi level pinning effect, adopt high-k (K)/metal gate material to replace traditional SiO
2/ poly (polysilicon) structure has become inevitable choice.The Mo metal gate is owing to have low resistivity (5 * 10
-6Ω .cm), the Mo metal gate in high fusing point (greater than 2600 ℃) and (100) crystal orientation shows near the work function the 5eV, makes Mo Base Metal grid become the strong candidate of P pipe metal gate material.
In order to reduce the difficulty of etching, increase the complexity of original CMOS technology with exceeding, generally adopt the laminated construction (being the laminated construction of Si-gate/metal gate) of plug-in type metal gate to replace the simple metal gate electrode to realize the integrated of high K, metal gate material.But since directly on Mo Base Metal grid the pyroprocess during the deposit Si-gate cause Mo Base Metal grid and Si-gate to react, the very high TaN barrier layer of adding one deck thermal stability improves thermal stability between Mo Base Metal grid and Si-gate.In addition; Adopt the bimetal gate Integrated Solution of deposit-corrosion-deposit again to realize high K; When the bimetal gate material is integrated, if when adopting Mo Base Metal grid, TaN metal gate respectively as the metal gate material of P pipe and N pipe, the alternative Mo Base Metal grid of removing first deposit; And then deposit TaN metal gate; So just form the N pipe and have the TaN metal gate, the P pipe has the structure of Mo base/TaN lamination metal grid, therefore in follow-up metal gate etching process, also will run into the etching of Mo base/TaN metal gate stack structure.It is thus clear that; No matter be in order to improve the thermal stability between Mo Base Metal grid and Si-gate or from adopting the bimetal gate Integrated Solution angle of deposit of deposit-corrosion-again, the etching that solves Mo base/TaN metal gate stack structure is to realize that P manages the integrated strong guarantees of Mo Base Metal grid.
Summary of the invention
The technical problem that (one) will solve
The nano-scale CMOS device that the present invention is directed to prepares introduces high K in the process, after the metal gate material, for realizing the integrated purpose of high K/ metal gate, the lithographic method of a kind of Mo base/TaN metal gate stack structure is provided.
(2) technical scheme
For achieving the above object, the invention provides the lithographic method of a kind of Mo base/TaN metal gate stack structure, this method forms earlier interface SiO successively on Semiconductor substrate
2Layer, high-K gate dielectric layer, Mo Base Metal grid, TaN metal gate, silicon gate layer and hard mask layer; Carry out the etching of photoetching and hard mask then; After removing photoresist, for sheltering, silicon gate layer is carried out the anisotropic etching of high selectivity through dry etch process with hard mask; TaN metal gate, Mo Base Metal grid and high K medium are carried out the anisotropic etching of high selectivity through dry etch process.
In the such scheme, described Mo Base Metal gate electrode layer is made up of the laminated construction of any two kinds of materials among Mo, MoN, MoAlN or MoAlN, MoN, the Mo.
In the such scheme, said silicon gate layer is polysilicon or amorphous silicon, and said hard mask layer is made up of silica, silicon nitride or silica/silicon nitride stack structure.
In the such scheme, when being carried out etching, TaN metal gate, Mo Base Metal grid and high K medium adopt BCl
3The base etching gas is as etching gas.
In the such scheme, said BCl
3The base etching gas is except comprising BCl
3Also comprise Cl outward,
2, SF
6, O
2, one or more gases among the Ar are as etching gas.
In the such scheme, said BCl
3The base etching gas is BCl
3, Cl
2, O
2With the mist of Ar, or BCl
3, SF
6, O
2Mist with Ar.
In the such scheme, said BCl
3, Cl
2, O
2With Cl in the mist of Ar
2With BCl
3Ratio be 1: 10 to 1: 3, O
2With BCl
3Ratio be 1: 20 to 1: 5, Ar and BCl
3Ratio be 1: 5 to 1: 2.
In the such scheme, said BCl
3, SF
6, O
2With SF in the mist of Ar
6With BCl
3Ratio be 1: 9 to 1: 4, O
2With BCl
3Ratio be 1: 20 to 1: 6, Ar and BCl
3Ratio be 1: 5 to 1: 2.
In the such scheme, the dry etch process condition of said TaN metal gate, Mo Base Metal grid and high K dielectric stack structure is: upper electrode power is 120W to 500W, and lower electrode power is 40W to 220W, and pressure is 4mt to 15mt, BCl
3The total flow of base etching gas is 40sccm to 120sccm, and the temperature of cavity and electrode is controlled at 50 ℃ to 80 ℃.
(3) beneficial effect
The invention has the beneficial effects as follows: the lithographic method of this Mo base/TaN metal gate stack structure that the present invention proposes; Simply, practicality; The etching of TaN metal gate and Mo Base Metal grid is accomplished through a step etching; Etching technics through optimizing TaN, Mo Base Metal grid and high K dielectric stack structure not only obtains steep etching section, and very little to the loss of Si substrate, for realizing the integrated necessary guarantee that provides of high K/ metal gate.In addition, this lithographic method and existing C MOS processing compatibility are higher.
Description of drawings
Fig. 1 is the lithographic method flow chart of this Mo base/TaN metal gate stack structure of the present invention's proposition;
Fig. 2 is for adopting BCl according to the embodiment of the invention
3/ Cl
2/ O
2Sem photograph behind the/Ar mist etching MoAlN/TaN laminated construction;
Fig. 3 is for adopting BCl according to the embodiment of the invention
3/ SF
6/ O
2Sem photograph behind the/Ar mist etching MoAlN/TaN laminated construction.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, to further explain of the present invention.
As shown in Figure 1, Fig. 1 is the lithographic method flow chart of this Mo base provided by the invention/TaN metal gate stack structure, and this method forms earlier interface SiO successively on Semiconductor substrate
2Layer, high-K gate dielectric layer, Mo Base Metal grid, TaN metal gate, silicon gate layer and hard mask layer; Carry out the etching of photoetching and hard mask then; After removing photoresist, for sheltering, silicon gate layer is carried out the anisotropic etching of high selectivity through dry etch process with hard mask; TaN metal gate, Mo Base Metal grid and high K medium are carried out the anisotropic etching of high selectivity through dry etch process.
Wherein, described Mo Base Metal gate electrode layer is made up of the laminated construction of any two kinds of materials among Mo, MoN, MoAlN or MoAlN, MoN, the Mo.Said silicon gate layer is polysilicon or amorphous silicon, and said hard mask layer is made up of silica, silicon nitride or silica/silicon nitride stack structure.When being carried out etching, TaN metal gate, Mo Base Metal grid and high K medium adopt BCl
3The base etching gas is as etching gas.
Said BCl
3The base etching gas is except comprising BCl
3Also comprise Cl outward,
2, SF
6, O
2, one or more gases among the Ar are as etching gas.Said BCl
3The base etching gas is BCl
3, Cl
2, O
2With the mist of Ar, or BCl
3, SF
6, O
2Mist with Ar.Said BCl
3, Cl
2, O
2With Cl in the mist of Ar
2With BCl
3Ratio be 1: 10 to 1: 3, O
2With BCl
3Ratio be 1: 20 to 1: 5, Ar and BCl
3Ratio be 1: 5 to 1: 2.Said BCl
3, SF
6, O
2With SF in the mist of Ar
6With BCl
3Ratio be 1: 9 to 1: 4, O
2With BCl
3Ratio be 1: 20 to 1: 6, Ar and BCl
3Ratio be 1: 5 to 1: 2.
The dry etch process condition of said TaN metal gate, Mo Base Metal grid and high K dielectric stack structure is: upper electrode power is 120W to 500W, and lower electrode power is 40W to 220W, and pressure is 4mt to 15mt, BCl
3The total flow of base etching gas is 40sccm to 120sccm, and the temperature of cavity and electrode is controlled at 50 ℃ to 80 ℃.
Embodiment
On the Si substrate, generate interface SiO through rapid thermal oxidation (RTO) technology
2Layer, the high K medium of HfSiAlON that adopts physical vapor deposition process to form then; After 900 ℃ of high-temperature process, forming thickness through physical vapor deposition process is the MoAlN metal gate of 10nm, and the TaN metal gate layer of deposit 5.0nm on the throne; Adopting low-pressure chemical vapor phase deposition technology to form thickness is the polysilicon of 110 nanometers, and to adopt low thermal oxidation technology to form thickness above that be the hard mask of silicon dioxide of 65 nanometers.After the photoetching, respectively hard mask and polysilicon gate are carried out the anisotropic etching of high selectivity.
After adopting the hard mask of optimizing and polycrystalline silicon etching process etching, through optimizing BCl
3/ Cl
2/ O
2Upper/lower electrode power, pressure and the cavity of the ratio of/Ar mist, etching technics and the parameters such as temperature of electrode are carried out the anisotropic etching etching of high selectivity to TaN metal gate, MoAlN metal gate and high K dielectric stack structure, and be as shown in Figure 2.As can beappreciated from fig. 2, after the etching, the etching section of polysilicon and metal gate all is steep, and no etching is remaining, and this etching technics is less to the loss of Si substrate.
After adopting the hard mask of optimizing and polycrystalline silicon etching process etching, through optimizing BCl
3/ SF
6/ O
2Upper/lower electrode power, pressure and the cavity of the ratio of/Ar mist, etching technics and the parameters such as temperature of electrode are carried out the anisotropic etching etching of high selectivity to TaN metal gate, MoAlN metal gate and high K dielectric stack structure, and be as shown in Figure 3.As can beappreciated from fig. 3, after the etching, the etching section of polysilicon and metal gate all is steep, and no etching is remaining, and this etching technics is less to the loss of Si substrate.
Therefore, the lithographic method of provided by the present invention kind of Mo base/TaN metal gate stack structure is suitable for the integrated needs of high-K metal gate in the nano-scale CMOS device, for realizing the integrated necessary guarantee that provides of high K/ metal gate.
Above-described specific embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, and institute it should be understood that the above is merely specific embodiment of the present invention; Be not limited to the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. the lithographic method of Mo base/TaN metal gate stack structure is characterized in that, this method forms earlier interface SiO successively on Semiconductor substrate
2Layer, high-K gate dielectric layer, Mo Base Metal grid, TaN metal gate, silicon gate layer and hard mask layer; Carry out the etching of photoetching and hard mask then; After removing photoresist, for sheltering, silicon gate layer is carried out the anisotropic etching of high selectivity through dry etch process with hard mask; TaN metal gate, Mo Base Metal grid and high K medium are carried out the anisotropic etching of high selectivity through dry etch process.
2. the lithographic method of Mo base according to claim 1/TaN metal gate stack structure is characterized in that, described Mo Base Metal gate electrode layer is made up of the laminated construction of any two kinds of materials among Mo, MoN, MoAlN or MoAlN, MoN, the Mo.
3. the lithographic method of Mo base according to claim 1/TaN metal gate stack structure is characterized in that said silicon gate layer is polysilicon or amorphous silicon, and said hard mask layer is made up of silica, silicon nitride or silica/silicon nitride stack structure.
4. the lithographic method of Mo base according to claim 1/TaN metal gate stack structure is characterized in that, adopts BCl when TaN metal gate, Mo Base Metal grid and high K medium are carried out etching
3The base etching gas is as etching gas.
5. the lithographic method of Mo base according to claim 4/TaN metal gate stack structure is characterized in that said BCl
3The base etching gas is except comprising BCl
3Also comprise Cl outward,
2, SF
6, O
2, one or more gases among the Ar are as etching gas.
6. according to the lithographic method of claim 4 or 5 described Mo base/TaN metal gate stack structures, it is characterized in that said BCl
3The base etching gas is BCl
3, Cl
2, O
2With the mist of Ar, or BCl
3, SF
6, O
2Mist with Ar.
7. the lithographic method of Mo base according to claim 6/TaN metal gate stack structure is characterized in that said BCl
3, Cl
2, O
2With Cl in the mist of Ar
2With BCl
3Ratio be 1: 10 to 1: 3, O
2With BCl
3Ratio be 1: 20 to 1: 5, Ar and BCl
3Ratio be 1: 5 to 1: 2.
8. the lithographic method of Mo base according to claim 6/TaN metal gate stack structure is characterized in that said BCl
3, SF
6, O
2With SF in the mist of Ar
6With BCl
3Ratio be 1: 9 to 1: 4, O
2With BCl
3Ratio be 1: 20 to 1: 6, Ar and BCl
3Ratio be 1: 5 to 1: 2.
9. the lithographic method of Mo base according to claim 1/TaN metal gate stack structure; It is characterized in that; The dry etch process condition of said TaN metal gate, Mo Base Metal grid and high K dielectric stack structure is: upper electrode power is 120W to 500W; Lower electrode power is 40W to 220W, and pressure is 4mt to 15mt, BCl
3The total flow of base etching gas is 40sccm to 120sccm, and the temperature of cavity and electrode is controlled at 50 ℃ to 80 ℃.
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|---|---|---|---|
| CN 201010223348 CN102315117B (en) | 2010-06-30 | 2010-06-30 | Etching method for Mo base/TaN metal grid lamination structure |
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|---|---|---|---|
| CN 201010223348 CN102315117B (en) | 2010-06-30 | 2010-06-30 | Etching method for Mo base/TaN metal grid lamination structure |
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| CN102315117B CN102315117B (en) | 2013-05-22 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109160487A (en) * | 2018-08-14 | 2019-01-08 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of tri- axis AMR magnetometric sensor of MEMS |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1177204A (en) * | 1996-09-10 | 1998-03-25 | 株式会社日立制作所 | Etching method |
| US20020086507A1 (en) * | 2000-12-29 | 2002-07-04 | Park Dae Gyu | Method of forming a metal gate in a semiconductor device |
| CN1667817A (en) * | 2004-03-10 | 2005-09-14 | 国际商业机器公司 | Method for manufacturing tungsten/polysilicon word line structure in vertical DRAM and device manufactured thereby |
| CN101667541A (en) * | 2008-09-05 | 2010-03-10 | 台湾积体电路制造股份有限公司 | Method for making metal gate stacks of a semiconductor device |
-
2010
- 2010-06-30 CN CN 201010223348 patent/CN102315117B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1177204A (en) * | 1996-09-10 | 1998-03-25 | 株式会社日立制作所 | Etching method |
| US20020086507A1 (en) * | 2000-12-29 | 2002-07-04 | Park Dae Gyu | Method of forming a metal gate in a semiconductor device |
| CN1667817A (en) * | 2004-03-10 | 2005-09-14 | 国际商业机器公司 | Method for manufacturing tungsten/polysilicon word line structure in vertical DRAM and device manufactured thereby |
| CN101667541A (en) * | 2008-09-05 | 2010-03-10 | 台湾积体电路制造股份有限公司 | Method for making metal gate stacks of a semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109160487A (en) * | 2018-08-14 | 2019-01-08 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of tri- axis AMR magnetometric sensor of MEMS |
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|---|---|
| CN102315117B (en) | 2013-05-22 |
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