CN102299057A - Method for manufacturing fine patterns on semiconductor device - Google Patents
Method for manufacturing fine patterns on semiconductor device Download PDFInfo
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- CN102299057A CN102299057A CN2010102178072A CN201010217807A CN102299057A CN 102299057 A CN102299057 A CN 102299057A CN 2010102178072 A CN2010102178072 A CN 2010102178072A CN 201010217807 A CN201010217807 A CN 201010217807A CN 102299057 A CN102299057 A CN 102299057A
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Abstract
The invention provides a method for manufacturing fine patterns on a semiconductor device. The method comprises the following steps: taking a patterned light resistance adhesive layer as first masking patterns; oxidizing polycrystalline silicon or noncrystalline silicon; and adopting silicon oxides as second masking patterns, and transferring repeated fine patterns to a target layer, thus forming small-sized fine patterns. On the premise of keeping existing photoetching infrastructures unchanged, the limit of the photoetching is increased.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of delicate pattern of semi-conductor device.
Background technology
Along with constantly dwindling of dimensions of semiconductor devices, lithographic feature size moves closer to even has surpassed the physics limit of optical lithography, promptly utilize existing lithographic equipment to obtain the littler semiconductor pattern of size by exposure imaging, proposed stern challenge more to semiconductor fabrication especially photoetching technique thus.Therefore, be used to form that substrate is reached the standard grade (line) and at interval in the photoetching process of (space) pattern, because there is restriction in the restriction of photoetching technique to the fine pattern that forms desired smaller szie.
Summary of the invention
In view of this, the technical problem of the present invention's solution is: the fine pattern that forms smaller szie.
For solving the problems of the technologies described above, technical scheme of the present invention specifically is achieved in that
The invention discloses a kind of manufacture method of delicate pattern of semi-conductor device, described fine pattern is interval and a line alternately, and this method comprises:
Deposition-etch destination layer, many/amorphous silicon layer and silicon nitride layer successively on Semiconductor substrate; Described many/implication of amorphous silicon layer is polysilicon layer or amorphous silicon layer;
At the surface coated photoresistance glue-line of silicon nitride layer, and the described photoresistance glue-line of exposure imaging patterning, the interval of definition fine pattern;
Photoresistance glue-line with patterning is a mask, and the described silicon nitride layer of etching forms the silicon nitride layer of patterning;
After removing the photoresistance glue-line, be mask, many/amorphous silicon layer is carried out the silicon oxide layer that oxidation formation has first preset width and first desired depth with the silicon nitride layer of patterning;
Silicon nitride layer with described patterning is a mask, the silicon oxide layer that anisotropic etching has first desired depth is many to manifesting/and amorphous silicon layer;
After removing the silicon nitride layer of described patterning, manifesting silicon oxide layer under the silicon nitride layer that is positioned at described patterning and not oxidized many/amorphous silicon layer, anisotropic etching is many/and amorphous silicon layer is to manifesting etching target; Described anisotropic etching is many/and the width of amorphous silicon layer is the interval of fine pattern;
With the silicon oxide layer that manifests is that mask carries out etching to etching target, forms fine pattern; The width of the described silicon oxide layer that manifests is the line of fine pattern; Its center line is with at interval alternately, and 2 times live width adds and equals described first preset width at interval.
Behind the described removal photoresistance glue-line, silicon nitride layer with patterning is a mask, many/amorphous silicon layer is carried out oxidation to be formed and to have before the silicon oxide layer of first preset width and first desired depth, this method further comprises: the silicon nitride layer with patterning is a mask, etching is many/and the step of amorphous silicon layer to the second desired depth and second preset width;
Described first preset width is greater than second preset width, and first desired depth is greater than second desired depth.
Described etching is many/and amorphous silicon layer is isotropic etching or anisotropic etching;
Described isotropic etching is many/and the gas of amorphous silicon layer comprises carbon tetrafluoride (CF
4), sulphur hexafluoride (SF
6) or Nitrogen trifluoride (NF
3) in a kind of, perhaps several combination in any;
Described anisotropic etching is many/and the gas of amorphous silicon layer comprises CF
4, hydrogen bromide (HBr) or chlorine (Cl
2) in a kind of, perhaps several combination in any.
The described method that is oxidized to thermal oxidation or plasma assisted oxidation.
Described anisotropic etching is many/and amorphous silicon layer to the etching gas that manifests etching target comprises hydrogen bromide (HBr) or chlorine (Cl
2) in a kind of, perhaps two kinds combination, when this etching gas carries out etching to many/amorphous silicon layer, can the etching oxidation silicon layer.
Between many/amorphous silicon layer of deposition and silicon nitride layer, this method further comprises the step of many/amorphous silicon layer being carried out ammonia annealing.
As seen from the above technical solutions, the present invention adopts digraph case technology, under the prerequisite that does not change existing photoetching infrastructure, has increased the limit of photoetching.The present invention with the photoresistance glue-line of patterning as the mask pattern first time, then polysilicon or amorphous silicon are carried out oxidation, adopt silica as the mask pattern second time, the fine pattern that repeats is transferred on the destination layer, thereby formed the littler fine pattern of size.
Description of drawings
Fig. 1 makes the method flow schematic diagram of fine pattern for the present invention.
Fig. 1 a to Fig. 1 g makes the concrete generalized section of fine pattern for the present invention.
Fig. 2 a to Fig. 2 h is the concrete generalized section that the preferred embodiment of the present invention is made fine pattern.
Embodiment
For make purpose of the present invention, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
Core concept of the present invention is that employing digraph case technology has increased the limit of photoetching under the prerequisite that is not changing existing photoetching infrastructure.So-called digraph case technology mainly is the mask pattern that utilizes twice formation, carries out etching, and mask pattern is transferred on the destination layer.For fine pattern,, form the repetition fine pattern of spacing (pitch)=line+space by method of the present invention with line and space.
The method flow schematic diagram that the present invention makes fine pattern as shown in Figure 1, it may further comprise the steps, and describes below in conjunction with Fig. 1 a to Fig. 1 g.
Here fine pattern can be a grating, or other have the fine pattern of line and space.Exposure imaging patterning photoresistance glue-line 104 promptly forms mask pattern the first time in the digraph case technology;
The gas of etch silicon nitride layer 103 is mainly carbon tetrafluoride (CF
4);
Be oxidized to silicon oxide layer for polysilicon layer 102, can control by predetermined oxidization time with first preset width and first desired depth.Specifically, at first select a slice to need the testing wafer (wafer) of oxidation, be formed with the structure identical on this wafer with the product wafer.Wherein, the product wafer is the wafer of the device that distributed on it, finally can become finished product through multiple working procedure; Though and the testing wafer test structure is identical with the product wafer, after test, go out of use.Testing wafer carries out test of many times when oxidation, preestablish oxidization time at every turn, and the wafer after the oxidation inserted measure board and carry out dimensional measurement, the time when finally reaching predetermined oxidation size is as with batch predetermined oxidization time of wafer in this step.
This step has formed the mask pattern in the digraph case technology for the second time, and this mask pattern is not the photoresistance glue of patterning, but oxidized polysilicon, promptly silicon oxide layer 105.Therefore, follow-up is mask with the silicon oxide layer 105 of repeated arrangement just, and etching target gets final product;
So far, fine pattern of the present invention forms.
Above-mentioned in step 14, accurate control to polysilicon layer 102 oxidations, the line and the space of fine pattern have been determined, for the size that makes line and space more accurate, the preferred embodiment of the present invention is after step 14 is removed photoresistance glue-line 104, polysilicon layer 102 is carried out before the oxidation, added the step of etch polysilicon layer 102.
The preferred embodiment of the present invention is made the method for fine pattern, may further comprise the steps, and describes below in conjunction with Fig. 2 a to Fig. 2 h.
Step 21, see also Fig. 2 a, deposition-etch destination layer 101, polysilicon layer 102 and silicon nitride layer 103 successively on Semiconductor substrate 100.
Step 22, see also Fig. 2 b, at the surface coated photoresistance glue-line 104 of silicon nitride layer 103, and the described photoresistance glue-line 104 of exposure imaging patterning, the space of definition fine pattern.
Here fine pattern can be a grating, or other have the fine pattern of line and space.Exposure imaging patterning photoresistance glue-line 104 promptly forms mask pattern the first time in the digraph case technology;
Step 23, seeing also Fig. 2 c, is mask with the photoresistance glue-line 104 of patterning, and the described silicon nitride layer 103 of etching forms the silicon nitride layer 103 of patternings.
The gas of etch silicon nitride layer 103 is mainly CF
4
Step 24, see also Fig. 2 d, remove photoresistance glue-line 104 after, be mask with the silicon nitride layer 103 of patterning, etch polysilicon layer 102 to second desired depth and second preset width.
Wherein, can be isotropic etching to the etching of polysilicon layer 102, the etching of the certain width and the degree of depth is promptly all arranged on horizontal and vertical, etching gas can comprise carbon tetrafluoride (CF
4), sulphur hexafluoride (SF
6) or Nitrogen trifluoride (NF
3) in a kind of, or above-mentioned several combination in any; Also can be anisotropic etching, the etching of certain depth is promptly only arranged in the vertical, etching gas can comprise CF
4, hydrogen bromide (HBr) or chlorine (Cl
2) in a kind of, or above-mentioned several combination in any.
For polysilicon layer 102 laterally or the etching size vertically also be to control by predetermined etch period.Testing wafer carries out test of many times when etching, preestablish etch period at every turn and carry out etching, and the wafer after the etching inserted measure board and carry out dimensional measurement, the etch period when finally reaching predetermined etching size is as with batch predetermined etch period of wafer in this step.
In this step after the control etching transverse width L of polysilicon layer 102 account for patterning silicon nitride layer 103 width 1/2～1.Vertical depth H during control etch polysilicon layer 102 accounts for 0～1 of polysilicon layer 102 height.If incorgruous etching, then etching can be to horizontal extension, and promptly etching is only along the silicon nitride layer 103 downward etchings of patterning, can not etch into polysilicon partly under the silicon nitride layer 103 of patterning, and L is identical with silicon nitride layer 103 width of patterning; If lateral etching, then etching is not only carried out downwards along the silicon nitride layer 103 of patterning, and can etch into the polysilicon of part under the silicon nitride layer 103 of patterning, makes L reduce.The width of L can not be too narrow, otherwise the back extended meeting is with the whole oxidations of the polysilicon in the L width; And H can have certain numerical value, and when H was big, the size in the time of can making subsequent oxidation is rule more, thus the characteristic size (CD) of etch polysilicon in the controlled step 27 more accurately;
Step 25, seeing also Fig. 2 e, is mask with the silicon nitride layer 103 of patterning, polysilicon layer 102 is carried out oxidation form the silicon oxide layer 105 with first preset width and first desired depth.Being specially aerating oxygen in reaction chamber, is silica with polysilicon oxidation, and the volume of therefore original polysilicon can increase, and silica is filled the sunk part of etching in the step 24 full.The method of oxidation has multiple, can be thermal oxidation, also can be the plasma assisted oxidation.Remaining in transversely after the oxidation, the width A of polysilicon layer 102 is space.
Be oxidized to silicon oxide layer for polysilicon layer 102, can control by predetermined oxidization time with first preset width and first desired depth.Owing to have on the basis of second preset width and second desired depth at the etch polysilicon layer, carry out oxidation, so that A reaches the width of space, thus first preset width greater than second preset width of etching, first desired depth is greater than second desired depth of etching;
Step 26, seeing also Fig. 2 f, is mask with the silicon nitride layer 103 of described patterning, and anisotropic etching silicon oxide layer 105 is to polysilicon layer 102;
Step 27, see also Fig. 2 g, remove silicon nitride layer 103 after, anisotropic etching polysilicon layer 102 has formed the fine pattern mask of wanting required for the present invention this moment to manifesting etching target 101.After silicon nitride layer 103 is removed, polysilicon layer 102 and silicon oxide layer 105 all reveal, so this step adopts the etch polysilicon and the selection of silica to carry out etching than very high gas, select than generally reaching tens even hundreds of, when being the etching polysilicon, substantially can etching oxidation silicon.Etching gas generally adopts a kind of in chlorine or the hydrogen bromide, perhaps two kinds combination.Wherein, the width of anisotropic etching polysilicon layer is the space of fine pattern; The width of the silicon oxide layer that manifests is the line of fine pattern; From Fig. 2 e and Fig. 2 f as can be seen, 2 times line adds first preset width after space equals oxidation;
Step 28, see also Fig. 2 h,, etching target 101 is carried out etching, form fine pattern of the present invention with described fine pattern mask.This step is transferred to the fine pattern mask on the etching target 101 exactly.
So far, the fine pattern of the preferred embodiment of the present invention forms.For instance, when needing the space=line of fine pattern, make in the step 24 the transverse width L of polysilicon layer 102 after the etching account for patterning silicon nitride layer 103 width 2/3, the vertical depth H during etch polysilicon layer 102 accounts for 1/3 of polysilicon layer 102 height; After in the step 25 polysilicon layer after the etching 102 being carried out oxidation, remain in the width A of polysilicon layer 102 transversely (A＜L) account for patterning silicon nitride layer 103 width 1/3, A has defined the width of space.First desired depth after oxidation this moment also can be greater than second desired depth after the etching.Simultaneously according to the above description, the interval between the silicon nitride layer 103 of patterning has also defined the width of space, so the width of line is identical with space, account for patterning silicon nitride layer 103 width 1/3.
Between deposit spathic silicon layer 102 and silicon nitride layer 103, may further include the step of polysilicon layer 102 being carried out ammonia annealing.During oxidation polysilicon layer 102, owing to have grain structure in the polysilicon layer 102, and the oxidation rate of locating at granule boundary (grain boundary) is more a lot of soon than the oxidation rate of granule interior, so adopting ammonia anneals to polysilicon layer 102, help reducing the oxidation at granule boundary place, make the oxidation rate in the polysilicon layer 102 reach unanimity, form uniform silicon oxide layer.For amorphous silicon, the method for above-mentioned ammonia annealing stands good.
Between deposition-etch destination layer 101 and polysilicon layer 102, may further include the step that deposition forms hard mask layer; hard mask layer can be silicon nitride, silicon oxynitride etc.; have certain rigidity, be used to protect the uniformity of etching target 101 etching size.If between etching target 101 and polysilicon layer 102, add hard mask layer, then remove silicon nitride layer 103 after, etch polysilicon layer 102 is etched to hard mask layer then and manifests etching target 101 to manifesting hard mask layer.
In sum, the formation method of fine pattern of the present invention has adopted digraph case technology.And crucial is, polysilicon or amorphous silicon are carried out oxidation, adopts silica as mask pattern, the fine pattern that repeats is transferred on the destination layer, thereby formed the littler fine pattern of size.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being made, is equal to replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (6)
1. the manufacture method of a delicate pattern of semi-conductor device, described fine pattern is interval and a line alternately, this method comprises:
Deposition-etch destination layer, many/amorphous silicon layer and silicon nitride layer successively on Semiconductor substrate; Described many/implication of amorphous silicon layer is polysilicon layer or amorphous silicon layer;
At the surface coated photoresistance glue-line of silicon nitride layer, and the described photoresistance glue-line of exposure imaging patterning, the interval of definition fine pattern;
Photoresistance glue-line with patterning is a mask, and the described silicon nitride layer of etching forms the silicon nitride layer of patterning;
After removing the photoresistance glue-line, be mask, many/amorphous silicon layer is carried out the silicon oxide layer that oxidation formation has first preset width and first desired depth with the silicon nitride layer of patterning;
Silicon nitride layer with described patterning is a mask, the silicon oxide layer that anisotropic etching has first desired depth is many to manifesting/and amorphous silicon layer;
After removing the silicon nitride layer of described patterning, manifesting silicon oxide layer under the silicon nitride layer that is positioned at described patterning and not oxidized many/amorphous silicon layer, anisotropic etching is many/and amorphous silicon layer is to manifesting etching target; Described anisotropic etching is many/and the width of amorphous silicon layer is the interval of fine pattern;
With the silicon oxide layer that manifests is that mask carries out etching to etching target, forms fine pattern; The width of the described silicon oxide layer that manifests is the line of fine pattern; Its center line is with at interval alternately, and 2 times live width adds and equals described first preset width at interval.
2. the method for claim 1, it is characterized in that, behind the described removal photoresistance glue-line, silicon nitride layer with patterning is a mask, many/amorphous silicon layer is carried out oxidation to be formed and to have before the silicon oxide layer of first preset width and first desired depth, this method further comprises: the silicon nitride layer with patterning is a mask, etching is many/and the step of amorphous silicon layer to the second desired depth and second preset width;
Described first preset width is greater than second preset width, and first desired depth is greater than second desired depth.
3. method as claimed in claim 2 is characterized in that, and described etching is many/and amorphous silicon layer is isotropic etching or anisotropic etching;
Described isotropic etching is many/and the gas of amorphous silicon layer comprises carbon tetrafluoride CF
4, sulphur hexafluoride SF
6Or Nitrogen trifluoride NF
3In a kind of, perhaps several combination in any;
Described anisotropic etching is many/and the gas of amorphous silicon layer comprises CF
4, hydrogen bromide HBr or chlorine Cl
2In a kind of, perhaps several combination in any.
4. as claim 1,2 or 3 described methods, it is characterized in that the described method that is oxidized to thermal oxidation or plasma assisted oxidation.
5. method as claimed in claim 4 is characterized in that, and described anisotropic etching is many/and amorphous silicon layer to the etching gas that manifests etching target comprises hydrogen bromide HBr or chlorine Cl
2In a kind of, perhaps two kinds combination, when this etching gas carries out etching to many/amorphous silicon layer, can the etching oxidation silicon layer.
6. method as claimed in claim 1 or 2 is characterized in that, between many/amorphous silicon layer of deposition and silicon nitride layer, this method further comprises the step of many/amorphous silicon layer being carried out ammonia annealing.
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| CN 201010217807 CN102299057B (en) | 2010-06-28 | 2010-06-28 | Method for manufacturing fine patterns on semiconductor device |
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| CN 201010217807 CN102299057B (en) | 2010-06-28 | 2010-06-28 | Method for manufacturing fine patterns on semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105719964A (en) * | 2014-12-05 | 2016-06-29 | 中国科学院微电子研究所 | Method of planarization |
| CN116207039A (en) * | 2023-04-28 | 2023-06-02 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5942787A (en) * | 1996-11-18 | 1999-08-24 | Advanced Micro Devices, Inc. | Small gate electrode MOSFET |
| US6706571B1 (en) * | 2002-10-22 | 2004-03-16 | Advanced Micro Devices, Inc. | Method for forming multiple structures in a semiconductor device |
| US20040266155A1 (en) * | 2003-06-30 | 2004-12-30 | Chartered Semiconductor Manufacturing Ltd. | Formation of small gates beyond lithographic limits |
-
2010
- 2010-06-28 CN CN 201010217807 patent/CN102299057B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5942787A (en) * | 1996-11-18 | 1999-08-24 | Advanced Micro Devices, Inc. | Small gate electrode MOSFET |
| US6706571B1 (en) * | 2002-10-22 | 2004-03-16 | Advanced Micro Devices, Inc. | Method for forming multiple structures in a semiconductor device |
| US20040266155A1 (en) * | 2003-06-30 | 2004-12-30 | Chartered Semiconductor Manufacturing Ltd. | Formation of small gates beyond lithographic limits |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105719964A (en) * | 2014-12-05 | 2016-06-29 | 中国科学院微电子研究所 | Method of planarization |
| CN116207039A (en) * | 2023-04-28 | 2023-06-02 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
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| CN102299057B (en) | 2013-04-24 |
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