CN101964912A

CN101964912A - Method for fast calculating run length by run length coding in MPEG2

Info

Publication number: CN101964912A
Application number: CN2010105080930A
Authority: CN
Inventors: 邓伟; 褚震宇; 高上
Original assignee: Beijing Dayang Technology Development Inc
Current assignee: Beijing Dayang Technology Development Inc
Priority date: 2010-10-15
Filing date: 2010-10-15
Publication date: 2011-02-02

Abstract

The invention relates to a method for fast calculating run length by run length coding in motion picture experts group 2 (MPEG2), which is a method for computer image processing and a data compressing method for digitalized video image. The method is realized by the following steps of configuring nFlags; judging whether nFlags is zero or not; calculating the number of continuous zero digits in nFlags; and ending. In the method, a 64-bit integer nFlags is established, the correspondence between the nFlags and 64 coefficients of an 8*8 square pixel block subjected to transform quantitative rearrangement is established, and the length of each run length is calculated by using central processing unit (CPU) instruction 'BSF' during the run length coding; therefore, the conditional branch is greatly reduced, the execution efficiency of the CPU in MPEG2 video image coding is effectively improved, and the MPEG2 video image coding is quicker.

Description

A kind of in MPEG2 Run-Length Coding calculate the method for run length fast

Technical field

The present invention relates to the method that Run-Length Coding among a kind of MPEG2 calculates run length fast, is a kind of method of Computer Image Processing, is a kind of data compression method of digitized video image.

Background technology

For the ease of editor, making, storage and the transmission of digitized video image, to carry out data compression to video image usually.The data compression of video image has multiple mode, and wherein the most frequently used is the MPEG2 coding.Must be in the MPEG2 encoding video pictures through the Variable Length Code process.Variable Length Code comprises two kinds of Run-Length Coding and entropy codings in the MPEG2 coding standard.Usually more through the null value in the image transform coefficient after quantizing, null value can be done further lossless compress by Run-Length Coding.

Run-Length Coding (RLE, run-length encoding) claims again " run length coding " or " run-length encoding ", is that an item number is according to the lossless compression-encoding technology.It is applicable to the compression of class data, and these class data are made up of a string symbol, in this string symbol, repeatedly occurs identical symbol continuously.For example:

The basic principle of Run-Length Coding is: with a string data of forming by same-sign, with the length of this string symbol and value of symbol form several to representing (continuous symbol has constituted one section continuous " distance of swimming ", and Run-Length Coding hence obtains one's name).Like this, the coding result of above-mentioned example is:

(8,0)(6,5)(5,7)(3,3)(4,2)(7,1)

The figure place of coding result is far fewer than the figure place of former symbol string, and this has just reached the purpose of packed data.

The base unit of Variable Length Code is the residual image zone (8 * 8) of 8 * 8 squares of pixels in MPEG2.8 * 8 results behind dct transform are 64 conversion coefficients, with coefficient quantization and rearrange (press low frequency coefficient preceding, high frequency coefficient back).Among its result, continuous null value is more, is suitable for doing Run-Length Coding.MPEG2 only does Run-Length Coding to the null value in 64 coefficients.Add up the number (if be nonzero coefficient still before this nonzero coefficient, then remembering before this nonzero coefficient has 0 continuous zero valued coefficients) of the continuous zero valued coefficients that is close to it before any one nonzero coefficient, with this numerical value therewith nonzero coefficient form several right.Statistics finishes that all are so several right successively, has promptly finished the Run-Length Coding among the MPEG2.For example, certain 8 * 8 through dct transform, quantifications and 64 coefficients after resetting be:

Result through Run-Length Coding is:

(4,1)(6,13)(3,5)(0,-7)(9,12)(0,6)(8,3)(11,-6)

Continuous null value for end in the former ordered series of numbers is no longer encoded.

The CPU of computer is the binary command (machine instruction) that program code is resolved into a rule when working procedure, then by the specified order execution command.The process of CPU execution command is will instruct earlier to read the internal memory from hard disk, reads again in the Instructions Cache of CUP, and then the instruction in the buffer memory that executes instruction one by one.Instruction is read internal memory from hard disk, carries out the time of an instruction again from Instructions Cache to the needed time of the process of Instructions Cache far more than CPU.Therefore, CPU can be as far as possible early when carrying out other instructions and the instruction that will promptly will be performed as much as possible read the Instructions Cache from hard disk, carry out subsequently in order to CPU.This needs CPU that the instruction queue that promptly will be performed is simply judged, to arrange the order that instruction will be performed.If (just CPU is when carrying out this instruction in Conditions decision instruction in the instruction queue, according to state at that time, could select the instruction that will be performed subsequently, this situation is called as conditional branching), CPU can't judge the instruction that will be performed subsequently in advance, also just can't in advance the instruction after the condition judgment instruction be read in the Instructions Cache of CPU.This can reduce the execution efficient of CPU, and it is many more that conditional branching occurs, and the execution efficient of CPU can be low more.Therefore, the appearance of minimizing conditional branching is to improve the important means that CPU carries out efficient.

Have a large amount of conditional branchings in the run length encoding method among traditional MPEG2, well-known, conditional branching influences the execution efficient of CPU, and it is many more that conditional branching occurs, and the execution efficient of CPU can be low more.Therefore, reducing conditional branching is to improve the important means that CPU carries out efficient.Video image handles one to the burdensome task that is CPU, and Run-Length Coding is a large amount of work in the cataloged procedure of MPEG2, if can reduce conditional branching wherein, and the execution efficient of CPU in the MPEG2 video image is handled will improve greatly.

Summary of the invention

In order to overcome prior art problems, the present invention proposes the method that Run-Length Coding among a kind of MPEG2 calculates run length fast.Described method has reduced conditional branching by the quick number of calculating continuous zero valued coefficients of plain mode, has improved the execution efficient of CPU in the MPEG2 video image is handled.

The object of the present invention is achieved like this: a kind of in MPEG2 Run-Length Coding calculate the method for run length fast, in the MPEG2 cataloged procedure, 64 coefficients after dct transform, the conversion are done through quantizing and rearrange in the residual image zone of 8 * 8 squares of pixels, will be through quantification and the step of doing Run-Length Coding of 64 coefficients after rearranging as follows:

The step of structure nFlags: be used to construct 64 integers, be designated as nFlags, each of nFlags is corresponding one by one with certain coefficient in 64 coefficients, corresponding order is: from lowest order, the 1st of nFlags, the 1st coefficient in corresponding 64 coefficients, it is the lowest frequency coefficient, the 2nd coefficient in 64 coefficients of the 2nd correspondence of nFlags, by that analogy, last 1 coefficient in 64 coefficients of last 1 correspondence of nFlags, promptly high frequency coefficient, the rule of structure is: if corresponding coefficient is 0, then corresponding with it position is made as " 0 " among the nFlags, if corresponding coefficient is non-0, then corresponding with it position is made as " 1 " among the nFlags;

Judge that whether nFlags is 0 step: be used to judge whether nFlags is 0, if nFlags equals 0, promptly each of nFlags is " 0 ", illustrate in 64 coefficients and do not had nonzero coefficient, enter the step of end,, enter next step if nFlags is non-0;

Calculate the step of continuous " 0 " position number among the nFlags: be used for by calling cpu instruction " BSF ", lowest order from nFlags, calculate the figure place of the position that is " 0 " continuously, this bit value is the number of continuous zero valued coefficients just, be the length of the distance of swimming, be designated as n, the several of coefficient composition from low level n+1 position correspondence among n and the nFlags are got up to preservation, with nFlags logic shift right n+1 position, promptly high-order mend " 0 ", corresponding relation is also corresponding to be moved, and gets back to " judging that whether nFlags is 0 step " afterwards;

The step that finishes: be used to finish the process of Run-Length Coding,, promptly obtain the result that 64 coefficients are done Run-Length Coding with several sequencing by the holding time being arranged that all have been preserved.

The beneficial effect that the present invention produces is: the present invention is by making up 64 Integer n Flags, set up corresponding relation with 64 coefficients, it is long to use " BSF " instruction to calculate the distance of swimming fast, significantly reduced conditional branching, improve the execution efficient of CPU in the MPEG2 encoding video pictures, and then improved MPEG2 encoding video pictures speed.

Description of drawings

The invention will be further described below in conjunction with drawings and Examples.

Fig. 1 is the method flow block diagram that Run-Length Coding calculates run length fast among embodiments of the invention one described a kind of MPEG2.

Embodiment

Embodiment one:

Present embodiment is the method that Run-Length Coding calculates distance of swimming number fast among a kind of MPEG2, and flow chart as shown in Figure 1.

Traditional MPEG2 Run-Length Coding process:

In MPEG2, after 8 * 8 done dct transform, quantification and reset, the common performing step of 64 coefficients of result being done Run-Length Coding was:

1., current location is located at first coefficient (original position p=0), the number with current continuous zero valued coefficients is made as 0(n=0).

2., whether the coefficient of judging current location is 0.If be 0, with the number of the current continuous zero valued coefficients 1(n=n+1 that adds up); If coefficient is non-0, with the number of current continuous zero valued coefficients and current coefficient value form several to and preserve, and then the number of current continuous zero valued coefficients is made as 0(n=0);

3., whether the coefficient of judging current location is last coefficient (the 64th coefficient).If last coefficient has been finished Run-Length Coding; If not, current location is located at next coefficient (p=p+1), the 2. repeat then, 3. step.

The C code is embodied as:

void?8x8Block_RLE_Old(__int16?*pCoefficient,?int?(*pRLE)[2])

// input: pCoefficient points to the memory address of preserving 64 coefficients

// output: pRLE points to the memory address of saving result number to formation

{

int?n?=?0;

for?(int?p?=?0;?p?<?64;?p++)

{

if?(pCoefficient[p]?==?0)

{

n++;

}

else

{

(*pRLE)[0]?=?n;

(*pRLE)[1]?=?pCoefficient[p];

pRLE++;

n?=?0;

}

In above-mentioned C code was realized, " for " Do statement and " if " can structure condition branches when conditional statement is compiled into machine instruction, and 64 coefficients are done Run-Length Coding and experienced 128 conditional branchings altogether.

The implementation method of Run-Length Coding among the described MPEG2 of present embodiment:

In MPEG2, after 8 * 8 done dct transform, quantification and reset, the performing step of 64 coefficients of result being done Run-Length Coding was:

1,64 Integer n Flags(of structure in fact, 64 bit platforms are with 64 integers, 32 bit platforms are with two 32 integers), each of nFlags is corresponding one by one with certain coefficient in 64 coefficients.Corresponding order is: from lowest order, and the 1st coefficient (lowest frequency coefficient) in nFlags the 1st (lowest order) corresponding 64 coefficients; The 2nd coefficient in 64 coefficients of the 2nd correspondence of nFlags; By that analogy, last 1 coefficient in nFlags last 1 (highest order) corresponding 64 coefficients (the 64th coefficient, also be high frequency coefficient).Corresponding formation rule is: if coefficient correlation be " 0 ", then among the nFlags therewith corresponding of coefficient also be " 0 "; If coefficient correlation non-" 0 ", then among the nFlags therewith the corresponding position of coefficient be " 1 ";

2, judge whether nFlags is 0.If nFlags equals 0, illustrating does not have nonzero coefficient, finishes Run-Length Coding; If nFlags is non-0, carried out for the 3rd step;

3, by calling a cpu instruction " BSF " (Bit Scan Forward), can obtain the lowest order from nFlags, be the figure place (if the lowest order of nFlags is non-0, then the figure place of " 0 " value is 0) of the position of " 0 " continuously.This bit value is the number (being run length) of continuous zero valued coefficients just, is designated as n.The several of coefficient composition from low level n+1 position correspondence among n and the nFlags are got up to preservation.With (high-order mend " 0 ", nFlags logic shift right n+1 position; Corresponding relation is also corresponding to be moved, for example n+2 the coefficient of first correspondence of the nFlags behind the logic shift right n+1 position), repeated for the 2nd step.

The C code is embodied as under 64 bit platforms:

void?8x8Block_RLE_New_64(__int16?*pCoefficient,?int?(*pRLE)[2])

{

unsigned?__int64?nFlags?=?Construct_nFlags_64(pCoefficient);

int?p?=?0;

while?(nFlags?!=?0)

{

int?n?=?Bit_Scan_Forward_64(nFlags);

(*pRLE)[0]?=?n;

(*pRLE)[1]?=?pCoefficient[p?+?n];

pRLE++;

p?+=?(n?+?1);

nFlags?>>=?(n?+?1);

}

Wherein, the inline assembler of function C onstruct_nFlags_64 and Bit_Scan_Forward_64 is realized being respectively:

unsigned?__int64?Construct_nFlags_64(__int16?*pCoefficient)

{

char?bOne[16]?=?{ 1,?1,?1,?1,?1,?1,?1,?1,?1,?1,?1,?1,?1,?1,?1,?1?};

__asm?{

movdqu xmm0,[rcx]

packuswb?xmm0,[rcx+16]

pminub xmm0,[bOne]

psllw xmm0,7

pmovmskb?rax,xmm0

movdqu xmm0,[rcx+32]

packuswb?xmm0,[rcx+48]

pminub xmm0,[bOne]

psllw xmm0,7

pmovmskb?rdx,xmm0

shl rdx,16

or rax,rdx

movdqu xmm0,[rcx+64]

packuswb?xmm0,[rcx+80]

pminub xmm0,[bOne]

psllw xmm0,7

pmovmskb?rdx,xmm0

shl rdx,32

or rax,rdx

movdqu xmm0,[rcx+96]

packuswb?xmm0,[rcx+112]

pminub xmm0,[bOne]

psllw xmm0,7

pmovmskb?rdx,xmm0

shl rdx,48

or rax,rdx

}

int?Bit_Scan_Forward_64(__int64?nFlags)

{

__asm?bsf rax,nFlags;

}

This enforcement described " BSF " instruction:

Under the Intel, the basic syntax of assembly instruction is:

The instruction destination operand, source operand

For example:

bsf eax,nFlags

Instruction is operated source operand, and the result is kept in the target operand." BSF " instruction is to seek the least significant bit of source operand (least significant bit is meant from lowest order, first position of non-0) position, because minimum bit position is 0 in the specifies operands, therefore actual calculate the position of least significant bit just equal the number of " 0 " value before the least significant bit.

In the present embodiment, if in 64 coefficients m nonzero coefficient arranged, then under 64 bit platforms, these 64 coefficients are done Run-Length Coding and are experienced m+1 conditional branching altogether;

In actual conditions, the overwhelming majority is zero valued coefficients (nonzero coefficient approximately only accounts for about 20%) in 64 coefficients, and therefore, m+1 can be far fewer than 128.Although seem that the common implementation method of Run-Length Coding is simpler, because the loop body in its code has been called 64 times, the instruction number of the actual execution of CPU will need the instruction number of CPU execution far more than new algorithm in addition!

In addition, the Run-Length Coding that adopts in H261, H262, MPEG1, Joint Photographic Experts Group is consistent with MPEG2.Run-Length Coding and MPEG2 basically identical that H263, MPEG4 adopt, that just last nonzero coefficient need be formed is several to make marks (be labeled as " 1 " and represent that this is last non-" 0 " coefficient in 64 coefficients), and implementation method is hardly with changing.Therefore, present embodiment also can be applied in the Run-Length Coding of H261, H262, MPEG1, JPEG, H263, MPEG4.Present embodiment is applicable in the Run-Length Coding of only adding up " 0 " value number in other words.

Embodiment two:

Present embodiment is the improvement of embodiment one, be embodiment one about structure nFlags the refinement of step.In the step of the described structure of present embodiment nFlags, in 64 bit platforms, make up 64 integers; Make up two 32 integers in 32 bit platforms, two 32 integers are combined into 64 integers.

Though the nFlags of structure is 64 for integer, present embodiment promptly can be applied on 64 bit platforms, also can be applied in 32 on the platform.As long as connect two nFlags32 position integers, promptly can realize.

The C code is embodied as under 32 bit platforms:

void?8x8Block_RLE_New_32(__int16?*pCoefficient,?int?(*pRLE)[2])

{

unsigned?int?nFlags_01_32?=?Construct_nFlags_32(pCoefficient);

unsigned?int?nFlags_33_64?=?Construct_nFlags_32(pCoefficient?+?32);

int?p?=?0,?n?=?0;

if?(nFlags_01_32?!=?0)

while?(nFlags_01_32?!=?0)

{

n?=?Bit_Scan_Forward_32(nFlags_01_32);

(*pRLE)[0]?=?n;

(*pRLE)[1]?=?pCoefficient[p?+?n];

pRLE++;

p?+=?(n?+?1);

nFlags_01_32?>>=?(n?+?1);

}

if?(nFlags_33_64?!=?0)

{

n?=?Bit_Scan_Forward_32(nFlags_33_64);

nFlags_33_64?>>=?(n?+?1);

n?+=?32?-?p;

(*pRLE)[0]?=?n;

(*pRLE)[1]?=?pCoefficient[p?+?n];

pRLE++;

p?+=?(n?+?1);

}

while?(nFlags_33_64?!=?0)

{

n?=?Bit_Scan_Forward_32(nFlags_33_64);

(*pRLE)[0]?=?n;

(*pRLE)[1]?=?pCoefficient[p?+?n];

pRLE++;

p?+=?(n?+?1);

nFlags_33_64?>>=?(n?+?1);

}

Wherein, the inline assembler of function C onstruct_nFlags_32 and Bit_Scan_Forward_32 is realized being respectively:

unsigned?int?Construct_nFlags_32(__int16?*pCoefficient)

{

char?bOne[16]?=?{1,?1,?1,?1,?1,?1,?1,?1,?1,?1,?1,?1,?1,?1,?1,?1};

__asm?{

movdqu xmm0,[ecx]

packuswb?xmm0,[ecx+16]

pminub xmm0,[bOne]

psllw xmm0,7

pmovmskb?eax,xmm0

movdqu xmm0,[ecx+32]

packuswb?xmm0,[ecx+48]

pminub xmm0,[bOne]

psllw xmm0,7

pmovmskb?edx,xmm0

shl edx,16

or eax,edx

}

int?Bit_Scan_Forward_32(int?nFlags)

{

__asm?bsf eax,nFlags;

}

In the present embodiment, if in 64 coefficients m nonzero coefficient arranged, then under 32 bit platforms, these 64 coefficients are done Run-Length Coding and are experienced m+2 conditional branching altogether.

In actual conditions, the overwhelming majority is zero valued coefficients (nonzero coefficient approximately only accounts for about 20%) in 64 coefficients, and therefore, m+2 can be far fewer than 128.Although seem that the common implementation method of Run-Length Coding is simpler, because the loop body in its code has been called 64 times, the instruction number of the actual execution of CPU will need the instruction number of CPU execution far more than new algorithm in addition!

It should be noted that at last, below only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to the preferred arrangement scheme, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention (such as replacing between each step etc.), and not break away from the spirit and scope of technical solution of the present invention.

Claims

One kind in MPEG2 Run-Length Coding calculate the method for run length fast, in the MPEG2 cataloged procedure, 64 coefficients after dct transform, the conversion are done through quantizing and rearranging in the residual image zone of 8 * 8 squares of pixels, it is characterized in that, will through quantification and rearrange after 64 coefficients step of doing Run-Length Coding as follows:

The step of structure nFlags: be used to construct 64 integers, be designated as nFlags, each of nFlags is corresponding one by one with certain coefficient in 64 coefficients, corresponding order is: from lowest order, the 1st of nFlags, the 1st coefficient in corresponding 64 coefficients, it is the lowest frequency coefficient, the 2nd coefficient in 64 coefficients of the 2nd correspondence of nFlags, by that analogy, last 1 coefficient in 64 coefficients of last 1 correspondence of nFlags, promptly high frequency coefficient, the rule of structure is: if corresponding coefficient is 0, then corresponding with it position is made as " 0 " among the nFlags, if corresponding coefficient is non-0, then corresponding with it position is made as " 1 " among the nFlags;

Judge that whether nFlags is 0 step: be used to judge whether nFlags is 0, if nFlags equals 0, promptly each of nFlags is " 0 ", illustrate in 64 coefficients and do not had nonzero coefficient, enter the step of end,, enter next step if nFlags is non-0;

Calculate the step of continuous " 0 " position number among the nFlags: be used for by calling cpu instruction " BSF ", lowest order from nFlags, calculate the figure place of the position that is " 0 " continuously, this bit value is the number of continuous zero valued coefficients just, be the length of the distance of swimming, be designated as n, the several of coefficient composition from low level n+1 position correspondence among n and the nFlags are got up to preservation, with nFlags logic shift right n+1 position, promptly high-order mend " 0 ", corresponding relation is also corresponding to be moved, and gets back to " judging that whether nFlags is 0 step " afterwards;

The step that finishes: be used to finish the process of Run-Length Coding,, promptly obtain the result that 64 coefficients are done Run-Length Coding with several sequencing by the holding time being arranged that all have been preserved.
2. method according to claim 1 is characterized in that, in the step of described structure nFlags, makes up 64 integers in 64 bit platforms; Make up two 32 integers in 32 bit platforms, these two 32 integers are combined into 64 integers.