CN101958284B - Method for improving current carrier migration rate of MOS transistor - Google Patents
Method for improving current carrier migration rate of MOS transistor Download PDFInfo
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- CN101958284B CN101958284B CN2009100549728A CN200910054972A CN101958284B CN 101958284 B CN101958284 B CN 101958284B CN 2009100549728 A CN2009100549728 A CN 2009100549728A CN 200910054972 A CN200910054972 A CN 200910054972A CN 101958284 B CN101958284 B CN 101958284B
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Abstract
The invention provides a method for improving the current carrier migration rate of a metal-oxide semiconductor (MOS) transistor. The method comprises the following steps of: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a grid; forming an oxide layer which covers the grid and the upper surfaces, on the two sides of the grid, of the semiconductor substrate by a low pressure chemical vapor deposition (LPCVD) method by taking TEOS and O2 as raw materials, wherein when the semiconductor substrate is going to form an N-metal-oxide semiconductor (NMOS) transistor, the stress of a reaction chamber is greater than 1.88 torr, and when the semiconductor substrate is going to form a P-metal-oxide semiconductor (PMOS) transistor, the stress of the reaction chamber is less than 1.88 torr; etching the oxide layer to form a side wall structure of the grid; and doping foreign ions in the grid and the semiconductor substrate on the two sides of the side wall structure of the grid. The method improves the current carrier migration rate of the MOS transistor.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly improve the method for MOS transistor carrier mobility.
Background technology
In field of semiconductor manufacture, the known stress film that on doped region, forms can produce mechanical stress to the doped region of its lower floor, thereby makes the interior stress that produces of doped region increase the related semiconductor component speeds.Such stress has been promoted the mobility of impurity.Electric charge carrier in the impurity that mobility increases can make semiconductor element, and for example transistor has higher running speed, and therefore the applied stress film is useful in the various suitable application.
Between more than ten years in the past; Utilize reduction MOS transistor (Metal-Oxide-SemiconductorField-Effect-Transistors; MOSFET) mode of size; So as to the component density and the cost of the service speed of each function element of improving integrated circuit constantly, usefulness performance, circuit, the method for reduction mainly comprises the thickness of reduction of gate length and grid oxic horizon.Make the MOS transistor element in order further to promote transistorized usefulness, utilize the strained channel zone that is arranged in the part of the semiconductor-based end.
For the CMOS transistor, nmos pass transistor wherein or PMOS transistor all can use the strained channel zone to improve the mobility of charge carrier rate, to increase the usefulness of element.For example; Publication number discloses a kind of CMOS transistor with compartmentalization stress structure in the Chinese patent of " CN1770425A "; This CMOS transistor is on the direction of source electrode one drain electrode; In the n of nmos pass transistor type passage, form the tensile stress film, in the transistorized p type of PMOS passage, form the compression stress film, can increase the mobility of charge carrier rate.Fig. 1 is the existing transistorized structural representation of CMOS with film of tensile stress and compression stress.As shown in Figure 1, form the film 13 of compression stress at the film 11 that forms tensile stress on the nmos pass transistor 10 with on PMOS transistor 12, can increase the mobility of charge carrier rate.
Along with the reduction of process node, what use is made of stress increases that the mobility of charge carrier rate becomes the problem that paid close attention to by people in the MOS transistor.
Summary of the invention
The purpose of this invention is to provide a kind of method that improves the MOS transistor carrier mobility, thereby improved mobility of charge carrier rate in the MOS transistor.
In order to achieve the above object, the invention provides a kind of method that improves the MOS transistor carrier mobility, comprise step:
The semiconductor-based end, be provided, have grid at said the semiconductor-based end;
With TEOS and O
2Be raw material; Utilize the method for LPCVD form to cover the oxide skin(coating) of the semiconductor upper surface of substrate of said grid and said grid both sides; When the said semiconductor-based end, will form nmos pass transistor; Then reaction chamber stress is greater than 1.88torr, and when the said semiconductor-based end will form the PMOS transistor, then reaction chamber stress was less than 1.88torr;
The said oxide skin(coating) of etching, the side wall construction of formation grid;
Impurity ion in the semiconductor-based end of said grid and said side wall construction both sides thereof.
Optional, form in the step of said oxide skin(coating), when the said semiconductor-based end will form nmos pass transistor, reaction chamber stress was 1.9torr to 2.2torr.
Optional, form in the step of said oxide skin(coating), when the said semiconductor-based end will form nmos pass transistor, temperature was 550 ℃ to 700 ℃ in the chamber.
Optional, form in the step of said oxide skin(coating), when the said semiconductor-based end will form nmos pass transistor, wherein the flow of TEOS was 200sccm, O
2Flow be 5sccm to 10sccm.
Optional, form in the step of said oxide skin(coating), when the said semiconductor-based end will form the PMOS transistor, reaction chamber stress was 1.6torr to 1.8torr.
Optional, form in the step of said oxide skin(coating), when the said semiconductor-based end will form the PMOS transistor, temperature was 550 ℃ to 700 ℃ in the chamber.
Optional, in the step of said formation oxide skin(coating), when the said semiconductor-based end will form the PMOS transistor, wherein the flow of TEOS was 200sccm, O
2Flow be 15sccm to 20sccm.
The advantage that technique scheme of the present invention is compared with prior art is:
The step of the oxide skin(coating) when the present invention forms the gate lateral wall structure through improving, thus make the stress in the oxide skin(coating) that forms to adjust according to required.For example in nmos pass transistor; Can be through reaction chamber stress greater than 1.88torr, the stress that makes this oxide skin(coating) is tension stress, in the PMOS transistor; Can be through reaction chamber stress less than 1.88torr; Making the stress of oxide is compression, thereby makes the carrier mobility in the MOS transistor increase, thereby reaches the effect that improves device speed.
Description of drawings
Through the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, characteristic and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by actual size equal proportion convergent-divergent.
Fig. 1 is the existing transistorized structural representation of CMOS with film of tensile stress and compression stress;
Fig. 2 is the sketch map of the stress of oxide skin(coating) in the grid side wall construction with the STRESS VARIATION of reaction chamber;
Fig. 3 is the flow chart of manufacturing approach one embodiment of semiconductor device of the present invention;
Fig. 4 to Fig. 7 is the sketch map of manufacturing approach one embodiment of semiconductor device of the present invention.
Embodiment
Along with the decline of process node, the characteristic size of semiconductor device is more and more littler, and stress is increasing to the influence of mobility of charge carrier rate like this.If the inventor finds with TEOS and O after research
2Be raw material, utilize the method for LPCVD (low-pressure chemical vapor phase deposition) to form in the step of oxide skin(coating) in the gate lateral wall structure, the chamber pressure during through adjustment LPCVD also can be so that the stress of the oxide skin(coating) that forms changes.Concrete, the stress of the oxide-film that reaction chamber stress generates during greater than 1.88torr is tension stress, and the stress of the oxide-film that generates during less than 1.88torr when reaction chamber stress is compression.The sketch map that is the stress of oxide skin(coating) in the grid side wall construction with the STRESS VARIATION of reaction chamber shown in Figure 2; Wherein ordinate is represented stress, and wherein negative value is a tensile stress, on the occasion of being compression stress; Abscissa is a reaction chamber pressure; Wherein Fig. 2 has reacted along with the pressure rising tensile stress in the reaction chamber increases, increase along with reaction chamber pressure reduces compression stress, and when pressure in reaction chamber during at 1.6torr to 2.2torr above-mentioned variation more remarkable.
Therefore, the invention provides a kind of method that improves the MOS transistor carrier mobility, comprise step:
The semiconductor-based end, be provided, have grid at said the semiconductor-based end;
With TEOS and O
2Be raw material; Utilize the method for LPCVD form to cover the oxide skin(coating) of the semiconductor upper surface of substrate of said grid and said grid both sides; When the said semiconductor-based end, will form nmos pass transistor; Then reaction chamber stress is greater than 1.88torr, and when the said semiconductor-based end will form the PMOS transistor, then reaction chamber stress was less than 1.88torr;
The said oxide skin(coating) of etching, the side wall construction of formation grid;
Impurity ion in the semiconductor-based end of said grid and said side wall construction both sides thereof.
Optional, form in the step of said oxide skin(coating), when the said semiconductor-based end will form nmos pass transistor, reaction chamber stress was 1.9torr to 2.2torr.
Optional, form in the step of said oxide skin(coating), when the said semiconductor-based end will form nmos pass transistor, temperature was 550 ℃ to 700 ℃ in the chamber.
Optional, form in the step of said oxide skin(coating), when the said semiconductor-based end will form nmos pass transistor, wherein the flow of TEOS was 200sccm, O
2Flow be 5sccm to 10sccm.
Optional, form in the step of said oxide skin(coating), when the said semiconductor-based end will form the PMOS transistor, reaction chamber stress was 1.6torr to 1.8torr.
Optional, form in the step of said oxide skin(coating), when the said semiconductor-based end will form the PMOS transistor, temperature was 550 ℃ to 700 ℃ in the chamber.
Optional, in the step of said formation oxide skin(coating), when the said semiconductor-based end will form the PMOS transistor, wherein the flow of TEOS was 200sccm, O
2Flow be 15sccm to 20sccm.
The step of the oxide skin(coating) when the present invention forms the gate lateral wall structure through improving, thus make the stress in the oxide skin(coating) that forms to adjust according to required.For example in nmos pass transistor; Can be through reaction chamber stress greater than 1.88torr, the stress that makes this oxide skin(coating) is tension stress, in the PMOS transistor; Can be through reaction chamber stress less than 1.88torr; Making the stress of oxide is compression, thereby makes the carrier mobility in the MOS transistor increase, thereby reaches the effect that improves device speed.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
A lot of details have been set forth in the following description so that make much of the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed practical implementation.
Secondly, the present invention utilizes sketch map to be described in detail, when the embodiment of the invention is detailed; For ease of explanation; The profile of expression device architecture can be disobeyed general ratio and done local the amplification, and said sketch map is instance, and it should not limit the scope of the present invention's protection at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 3 is the flow chart of manufacturing approach one embodiment of semiconductor device of the present invention.Fig. 4 to Fig. 7 is the sketch map of manufacturing approach one embodiment of semiconductor device of the present invention.
As shown in Figure 3, the method for the raising nmos pass transistor carrier mobility in the present embodiment comprises step:
S1: the semiconductor-based end is provided, has grid at said the semiconductor-based end.
With reference to figure 4; Concrete, silicon that the semiconductor-based end 100 can be monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) they also can be silicon-on-insulators (SOI); The material that perhaps can also comprise other, for example indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide.Though in these several examples of having described the material that can form the semiconductor-based end 100, any material that can be used as the semiconductor-based end all falls into the spirit and scope of the present invention.
Subsequently; Can utilize method well known to those skilled in the art on the semiconductor-based end, to form grid; Can specifically adopt following method in the present embodiment: at first, utilize ald (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) technology to form grid oxic horizon (not shown) on surface, the semiconductor-based ends 100.Then, at grid oxic horizon surface deposition polysilicon layer (not shown), for example can utilize PECVD or high-density plasma chemical vapor deposition (HDP-CVD) technology at substrate surface deposit polysilicon layer.Polysilicon layer surface in deposition also need form a hard mask layer (not shown), and for example silicon nitride adopts the pecvd process deposit to form above-mentioned silicon nitride usually.Be coated with photoresist (not shown) and patterning photoresist position then, utilize photoresist and silicon nitride subsequently, adopt plasma etching method etch polysilicon layer to form the grid 110 of MOS transistor as mask with the definition grid.Remove remaining photoresist and hard mask silicon nitride then, cineration technics is adopted in the removal of photoresist, and hard mask silicon nitride adopts the phosphoric acid wet method to remove.
Afterwards, can preferably comprise the foreign ion injection of semiconductor substrate 100 being carried out low dosage, form the light dope structure (LDD, Lightly Doped Drain) 112 of source area and drain region.
S2: with TEOS and O
2Be raw material; Utilize the method for LPCVD form to cover the oxide skin(coating) of the semiconductor upper surface of substrate of said grid and said grid both sides; When the said semiconductor-based end, will form nmos pass transistor; Then reaction chamber stress is greater than 1.88torr, and when the said semiconductor-based end will form the PMOS transistor, then reaction chamber stress was less than 1.88torr.
When the position of nmos pass transistor formed oxide skin(coating), reaction chamber stress was greater than 1.88torr, because the too little meeting of chamber pressure makes that the oxide density that generates is less, therefore in the present embodiment, preferred 1.9torr to 2.2torr.When the transistorized position of PMOS formed oxide skin(coating), reaction chamber stress was less than 1.88torr because chamber pressure too conference make that the oxide density that generates is too big, therefore in the present embodiment, preferred 1.6orr to 1.8torr.In the present embodiment, utilize the method for LPCVD (low-pressure chemical vapor phase deposition) to form in the step of oxide skin(coating) in the gate lateral wall structure, the chamber pressure during through adjustment LPCVD also can be so that the stress of the oxide skin(coating) that forms changes.Concrete, the stress of the oxide-film that reaction chamber stress generates during greater than 1.88torr is tension stress, and the stress of the oxide-film that generates during less than 1.88torr when reaction chamber stress is compression.
The molecular formula of said TEOS is Si (OC
2H
5)
4
With reference to figure 5, concrete, in the method deposited oxide layer 120 of the surface by utilizing LPCVD of the semiconductor-based ends 100 of grid 110 and said grid 110 both sides, the material of oxide layer 120 can be silicon dioxide (SiO
2).
Method is in reative cell, to feed TEOS and O
2
Two kinds of reactions below in deposition process, existing, reaction equation is:
Si(OC
2H
5)
4+12O
2→SiO
2+8CO
2+10H
2O (1)
Si(OC
2H
5)
4→SiO
2+4C
2H
4+2H
2O (2)
The inventor finds after research through adjustment O
2With the flow-rate ratio of TEOS, just can be so that the stress of the oxide skin(coating) that forms changes.Work as O
2With the flow-rate ratio of TEOS be tension stress less than the stress of the oxide-film that formed in 7: 100 o'clock, work as O
2With the flow-rate ratio of TEOS be compression greater than the stress of the oxide-film that generated in 7: 100 o'clock.Therefore in the present embodiment, the preferred 200sccm of the flow of TEOS.When the position of nmos pass transistor formed oxide skin(coating), the flow of O2 was less than 14sccm.Because O
2If the very little meeting of flow make reaction speed slow down, preferred therefore in the present embodiment, O
2Flow be specially 5sccm-10sccm, for example 6sccm, 7sccm, 8sccm, 9sccm, the flow of TEOS is 200sccm; When the transistorized position of PMOS formed oxide skin(coating), the flow of O2 was greater than 14sccm, because O
2If flow very conference make O
2Waste, preferred therefore in the present embodiment, O
2Flow be specially 15sccm-20sccm, for example 16sccm, 17sccm, 18sccm, 19sccm, the flow of TEOS is 200sccm.
In addition, in the present embodiment, when forming oxide skin(coating) in the position of nmos pass transistor, temperature is 550 ℃ to 700 ℃ in the chamber.When the transistorized position of PMOS formed oxide skin(coating), temperature was 550 ℃ to 700 ℃ in the chamber.
Then, the thickness that forms oxide skin(coating) 120 is between
.
Preferably, can also adopt plasma-reinforced chemical vapor deposition process (PECVD) at oxide layer 120 surface deposition silicon nitride layers (not shown) subsequently.
S3: the said oxide skin(coating) of etching, the side wall construction of formation grid.
With reference to figure 6, adopt dry etching, for example reactive ion etching (RIE) technology etching oxidation silicon layer 120 forms gate lateral wall structure 120a.
S4: impurity ion in the semiconductor-based end of said grid and said side wall construction both sides thereof.
With reference to figure 7, this step can utilize method well known to those skilled in the art to mix, and for example ion injects, and forms source area 140 and drain region 150 in the both sides of grid and gate lateral wall structure 120a.Because the oxide skin(coating) 120 that in step S2, forms has stress, so oxide skin(coating) 120 has been applied to its stress at the semiconductor-based end 100 of its lower floor, just the position of source area 140 and drain region 150.Therefore, just the source area 140 to nmos pass transistor applies tensile stress with drain region 150, applies compression stress to the transistorized source area 140 of PMOS with drain region 150, makes that like this mobility of charge carrier rate at the semiconductor-based end 100 increases.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.
Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention, or are revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (7)
1. a method that improves the MOS transistor carrier mobility is characterized in that, comprises step:
The semiconductor-based end, be provided, have grid at said the semiconductor-based end;
With TEOS and O
2Be raw material; Utilize the method for LPCVD form to cover the oxide skin(coating) of the semiconductor upper surface of substrate of said grid and said grid both sides; When the said semiconductor-based end, will form nmos pass transistor; Then reaction chamber pressure is greater than 1.88torr, and when the said semiconductor-based end will form the PMOS transistor, then reaction chamber pressure was less than 1.88torr;
The said oxide skin(coating) of etching, the side wall construction of formation grid;
Impurity ion in the semiconductor-based end of said grid and said side wall construction both sides thereof.
2. the method for raising MOS transistor carrier mobility according to claim 1 is characterized in that, forms in the step of said oxide skin(coating), and when the said semiconductor-based end will form nmos pass transistor, reaction chamber pressure was 1.9torr to 2.2torr.
3. the method for raising MOS transistor carrier mobility according to claim 2 is characterized in that, forms in the step of said oxide skin(coating), and when the said semiconductor-based end will form nmos pass transistor, temperature was 550 ℃ to 700 ℃ in the chamber.
4. the method for raising MOS transistor carrier mobility according to claim 3 is characterized in that, forms in the step of said oxide skin(coating), and when the said semiconductor-based end will form nmos pass transistor, wherein the flow of TEOS was 200sccm, O
2Flow be 5sccm to 10sccm.
5. the method for raising MOS transistor carrier mobility according to claim 1 is characterized in that, forms in the step of said oxide skin(coating), and when the said semiconductor-based end will form the PMOS transistor, reaction chamber pressure was 1.6torr to 1.8torr.
6. the method for raising MOS transistor carrier mobility according to claim 5 is characterized in that, forms in the step of said oxide skin(coating), and when the said semiconductor-based end will form the PMOS transistor, temperature was 550 ℃ to 700 ℃ in the chamber.
7. the method for raising MOS transistor carrier mobility according to claim 6 is characterized in that, in the step of said formation oxide skin(coating), when the said semiconductor-based end will form the PMOS transistor, wherein the flow of TEOS was 200sccm, O
2Flow be 15sccm to 20sccm.
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6200865B1 (en) * | 1998-12-04 | 2001-03-13 | Advanced Micro Devices, Inc. | Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6200865B1 (en) * | 1998-12-04 | 2001-03-13 | Advanced Micro Devices, Inc. | Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate |
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