CN101726274B - Method for determining width offset of MOSFET BSIM model parameter by using MOSFET input and output characteristics - Google Patents

Abstract

The invention provides a method for determining width offset of a BSIM model parameter of a MOSFET device by utilizing MOSFET input and output properties. The method comprises the following steps: firstly, measuring at least three Ids-Vds output properties of the MOSFET device with the same channel length and different channel widths by using a semiconductor parameter tester; then, solving a two-order derivative Ids'' of drain current Ids to drain voltage Vds; and easily acquiring the accurate width offset Wint of the MOSFET device by extending a curve of the Ids'' and the MOSFET channel design width Wdrawn.

Description

Utilize the MOSFET input-output characteristic to determine the method for MOSFET BSIM model parameter width offset

Technical field

The present invention relates to a kind of MOSFET of utilization input-output characteristic and determine the method for MOSFET BSIM model parameter width offset, belong to microelectronic component modeling field.

Background technology

MOSFET is a kind of four port semiconductor device, applies different excitations at each port, and the drain current of device also can correspondingly change.By device is set up mathematical model, draw the mathematic(al) representation of input and output, circuit designers uses this model to carry out the SPICE emulation of circuit design.At present proposed multiple mathematical model about MOSFET, every kind of model all comprises a large amount of parameters.The BSIM model is the standard of device model, is extensive use of by each big semiconductor manufacturers.Channel width side-play amount W _IntBe one of them important parameters, the effective value of its decision raceway groove, greatly degree influences the input-output characteristic of device.Channel width skew is misfitting of the actual value that caused by various technological factors (photoetching error, diffusion etc.) again in manufacturing process of device and design load.Along with the progress of technology, especially when digital circuit was used, in order to improve circuit level, size of devices needed as much as possible little, and channel width is also in requisition for as much as possible little.We know, long channel MOS FET drain current I _DsComputing formula at linear zone is

$I_{\mathrm{ds}}={\mathrm{\&mu;}}_{\mathrm{eff}}{C}_{\mathrm{ox}}\frac{W_{\mathrm{eff}}}{L_{\mathrm{eff}}}(V_{\mathrm{gs}}-V_{\mathrm{th}}-\frac{A_{\mathrm{bulk}}}{2}{V}_{\mathrm{ds}}){\mathrm{<figure-callout\; id="1"\; label="V\; ds\; Equation"\; filenames="H2009101997261E00031.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{ds}}$ Equation 1

W _Eff=W _Drawn-2W _IntEquation 2

U wherein _EffBe charge carrier effective mobility, C _OxBe raceway groove place unit-area capacitance, W _EffBe device channel effective width, L _EffBe device channel effective length, V _ThBe device threshold voltage, A _BulkBe the volume charge factor, V _Gs, V _DsBe respectively grid voltage and drain voltage, W _DrawnBe channel width design load, W _IntBe width offset.

From equation 1 as can be seen, drain current I _DsWith raceway groove effective width W _EffProportional.When the deep submicron process level is arrived in technical development,, also can cause very big change to the input-output characteristic of device even channel width has minor shifts.Therefore, accurately determine the channel width side-play amount, great meaning is arranged for circuit design.At present, the method for determining device channel width side-play amount mainly is to carry out guestimate according to knowhow, and obviously there is bigger error in this method under deep sub-micron technique.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of method of determining MOSFET BSIM model parameter width offset more accurately.Be used to obtain more accurate device channel width offset.

For solving the problems of the technologies described above, the present invention adopts following technical scheme:

1) provides at least three same channel length L, wherein L 〉=10um, different channel width design load W _DrawndThe MOSFET device;

2) selected quick scanning voltage increases progressively range value Δ V _Ds, increase progressively range value Δ V according to this quick scanning voltage _Ds, use semiconductor parametric tester to measure the I of above-mentioned MOSFET device respectively _Ds-V _DsElectrology characteristic and drafting I separately _Ds-V _DsCurve;

3) adopt the drain current I of numerical value second-order differential method to gained _DsCarry out mathematic(al) manipulation, obtain drain current I _DsTo drain voltage V _DsSecond-order differential value I _Ds";

4) select drain voltage V _Ds, in rectangular coordinate system, draw all devices at this drain voltage V _DsUnder second-order differential value I _Ds" with channel width design load W _DrawnLinearity curve, this drain voltage V _DsSelection guarantee that the MOSFET device is operated in linear zone;

5) prolong linearity curve that step 4) obtains until with rectangular coordinate system in channel width design load W _DrawnIntersect, half of intersection value is width offset.

The present invention has the MOSFET device of different channel widths, same channel length by at first selecting one group (at least three).Utilize semiconductor parametric tester to test the I of all devices then _d-V _DsCurve.Obtain the second-order differential value of curve by mathematics manipulation.The linear zone second-order differential value under the drafting identical bias and the curve of channel width.Prolong and obtain curve and transverse axis (channel width design load W _Drawn) intersection point, half of intersection value is raceway groove side-play amount W _IntThereby obtain more accurate device channel width offset.

Description of drawings:

Fig. 1 is testing tool and the device schematic cross-section that the present invention relates to;

Fig. 2 is the device schematic top plan view that the present invention relates to;

Fig. 3 is the test data I that the present invention relates to _Ds-V _DsCurve;

Fig. 4 is the I that the present invention relates to _Ds" V _DsCurve;

Fig. 5 is the I that the present invention relates to _Ds" W _DrawnCurve.

Embodiment

The following example will help to understand the present invention, but not limit content of the present invention.Instance data is based on certain 0.09um manufacture craft, and its minimum channel width design load is 0.5um.

At first select one group to have same channel length L (L 〉=10um, this example is got 10um), the channel width design load is respectively the MOSFET device of 0.5um, 1um, 2um, 5um and 10um.

As the I of accompanying drawing 1 to all MOSFET devices of measurement shown in Figure 2 _Ds-V _DsThe electrology characteristic test mode.The source electrode 11 of MOSFET device 10 to be measured, drain electrode 12 are linked to each other with semiconductor parametric tester 21 (as K4200, B1500, HP4156 etc.) with 19 by probe 18,20 respectively with grid 16.

Semiconductor parametric tester 21 provides ground level for source electrode 11, for grid 16 provides 1.2V constant voltage excitation, is the 12 drain voltage V that 0-1.32V is provided that drain _Ds, this drain voltage V _DsThe amplitude of increasing progressively can be set, and (promptly scanning incremental voltage amplitude is Δ V fast _Ds, wherein, 0＜Δ V _Ds＜0.05V).The preferred scanning fast of present embodiment incremental voltage amplitude is Δ V _DsBe 0.02V, simultaneously according to drain voltage V _DsMeasure the drain electrode 12 respective drain electric current I of flowing through _DsAlso can obtain drain current I _DsThe amplitude that increases progressively be Δ I _Ds

Draw I according to The above results _Ds-V _DsCurve 24 (as shown in Figure 3).In the present embodiment, select the MOSFET device of 5 different channel width design loads for use, the I of gained _Ds-V _DsTotally five of curves 24, only signal among Fig. 3.

The channel width effective value 22 of MOSFET device and width offset 23 are respectively as shown in Figure 2.13,15,17 tagma, grid oxygen and the Spacer that are respectively the MOSFET device.

To equation

Distortion can get drain current I _DsTo drain voltage V _DsThe second derivative formula

$I_{\mathrm{ds}}^{\&prime;\&prime;}=\frac{{\&PartialD;}^2{I}_{\mathrm{ds}}}{{\&PartialD;\mathrm{<figure-callout\; id="2"\; label="V\; ds"\; filenames="H2009101997261E00031.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{ds}}^{}}=\frac{{\&PartialD;}^2}{{\&PartialD;V}_{\mathrm{ds}}^2}\left[{\mathrm{\&mu;}}_{\mathrm{eff}}{C}_{\mathrm{ox}}\frac{W_{\mathrm{eff}}}{L_{\mathrm{eff}}}(V_{\mathrm{gs}}-V_{\mathrm{th}}-\frac{A_{\mathrm{bulk}}}{2}{V}_{\mathrm{ds}})V_{\mathrm{ds}}\right]=-{\mathrm{\&mu;}}_{\mathrm{eff}}{C}_{\mathrm{ox}}{A}_{\mathrm{bulk}}\frac{W_{\mathrm{eff}}}{L_{\mathrm{eff}}}{V}_{\mathrm{ds}}$

Learn I _Ds" with device channel effective width W _EffHave good linear relationship, therefore, obtain MOSFET width offset W accurately _IntObtain comparatively accurate I _Ds" particularly important.

U wherein _EffBe charge carrier effective mobility, C _OxBe raceway groove place unit-area capacitance, W _EffBe device channel effective width, L _EffBe device channel effective length, V _ThBe device threshold voltage, A _BulkBe the volume charge factor, V _Gs, V _DsBe respectively grid voltage and drain voltage, W _DrawnBe channel width design load, W _IntBe width offset.

Adopt five Is of numerical value second-order differential method (utilize software programming or directly utilize the device modeling software) to accompanying drawing 3 gained _Ds-V _Ds Curve 24 carries out mathematic(al) manipulation.Thereby obtain comparatively accurate I _Ds".

Concrete, utilize following formula to obtain comparatively accurate I _Ds"

$I_d^{\&prime;\&prime;}=\frac{\mathrm{\&Delta;}{I}_{\mathrm{ds}}^{\&prime;}}{\mathrm{\&Delta;}{V}_{\mathrm{ds}}}=\frac{I_{\mathrm{ds}}^{\&prime;}(V_{\mathrm{ds}}+\mathrm{\&Delta;}{V}_{\mathrm{ds}})+I_{\mathrm{ds}}^{\&prime;}(V_{\mathrm{ds}}-\mathrm{\&Delta;}{V}_{\mathrm{ds}})-{2I}_{\mathrm{ds}}^{\&prime;}\left(V_{\mathrm{ds}}\right)}{{2\mathrm{\&Delta;V}}_{\mathrm{ds}}}$

$=\frac{I_{\mathrm{ds}}(V_{\mathrm{ds}}+{2\mathrm{\&Delta;V}}_{\mathrm{ds}})+I_{\mathrm{ds}}(V_{\mathrm{ds}}-{2\mathrm{\&Delta;V}}_{\mathrm{ds}})-{2I}_{\mathrm{ds}}\left(V_{\mathrm{ds}}\right)}{{\left(2{\mathrm{\&Delta;V}}_{\mathrm{ds}}\right)}^2}$

Wherein, Δ I _Ds' be drain current I _DsThe increment of derivative, Δ V _DsFor the quick scanning voltage that drains increases progressively range value,, V _DsBe drain voltage.

In the present embodiment, select the quick scanning incremental voltage amplitude, ao V of drain electrode _Ds=0.02V is accurate as far as possible to guarantee the numerical value second-order differential.The result who obtains according to following formula draws I respectively _Ds" V _DsCurve 25 (totally five, only signal among Fig. 4).

Select a certain drain voltage V _Ds, satisfy 0＜V _Ds＜(V _Gs-V _Th)/2, wherein V _GsBe grid voltage, V _ThBe the MOSFET device threshold voltage.Preferred V in the present embodiment _Ds=0.2V is operated in linear zone to guarantee device, satisfies equation

And W _Eff=W _Drawn-2W _Int

U wherein _EffBe charge carrier effective mobility, C _OxBe raceway groove place unit-area capacitance, W _EffBe device channel effective width, L _EffBe device channel effective length, V _ThBe device threshold voltage, A _BulkBe the volume charge factor, V _Gs, V _DsBe respectively grid voltage and drain voltage, W _DrawnBe channel width design load, W _IntBe width offset.

Draw this V _DsThe I of all MOSFET devices under the situation _Ds" value and channel width design load W _DrawnCurve.In the present embodiment, select V _Ds=0.2V obtains five I of MOSFET device under this situation _Ds" value and five channel width design load W _Drawn, draw this I _Ds" W _DrawnStraight line prolongs this straight line to transverse axis (channel width design load W _Drawn), obtain intersection point 27 (as shown in Figure 5).Half of intersection point 27 value corresponding is width offset W _IntThe W that obtains in this example _IntValue is 0.0885um.

The foregoing description just lists expressivity principle of the present invention and effect is described, but not is used to limit the present invention.Any personnel that are familiar with this technology all can make amendment to the foregoing description under spirit of the present invention and scope.Therefore, the scope of the present invention should be listed as claims.

Claims (7)

1. utilize the MOSFET input-output characteristic to determine the method for MOSFET BSIM model parameter width offset, it is characterized in that this method may further comprise the steps:

1) provides at least three same channel length L, wherein L 〉=10um, different channel width design load W _DrawndThe MOSFET device;

2) selected quick scanning voltage increases progressively range value Δ V _Ds, increase progressively range value Δ V according to this quick scanning voltage _Ds, use semiconductor parametric tester to measure the I of above-mentioned MOSFET device respectively _Ds-V _DsElectrology characteristic and drafting I separately _Ds-V _DsCurve;

3) adopt the drain current I of numerical value second-order differential method to gained _DsCarry out mathematic(al) manipulation, obtain drain current I _DsTo drain voltage V _DsSecond-order differential value I _Ds";

4) select drain voltage V _Ds, in rectangular coordinate system, draw all devices at this drain voltage V _DsUnder second-order differential value I _Ds" with channel width design load W _DrawnLinearity curve, this drain voltage V _DsSelection guarantee that the MOSFET device is operated in linear zone;

5) prolong linearity curve that step 4) obtains until with rectangular coordinate system in representative channel width design load W _DrawnTransverse axis intersect, half of intersection value is width offset;

The second-order differential value I that second-order differential method in the described step 3) is asked _Ds" be to adopt formula

$I_d^{\&prime;\&prime;}=\frac{\mathrm{\&Delta;}{I}_{\mathrm{ds}}^{\&prime;}}{\mathrm{\&Delta;}{V}_{\mathrm{ds}}}=\frac{I_{\mathrm{ds}}^{\&prime;}(V_{\mathrm{ds}}+\mathrm{\&Delta;}{V}_{\mathrm{ds}})+I_{\mathrm{ds}}^{\&prime;}(V_{\mathrm{ds}}-\mathrm{\&Delta;}{V}_{\mathrm{ds}})-{2I}_{\mathrm{ds}}^{\&prime;}\left(V_{\mathrm{ds}}\right)}{{2\mathrm{\&Delta;V}}_{\mathrm{ds}}}$

$=\frac{I_{\mathrm{ds}}(V_{\mathrm{ds}}+{2\mathrm{\&Delta;V}}_{\mathrm{ds}})+I_{\mathrm{ds}}(V_{\mathrm{ds}}-{2\mathrm{\&Delta;V}}_{\mathrm{ds}})-{2I}_{\mathrm{ds}}\left(V_{\mathrm{ds}}\right)}{{\left(2{\mathrm{\&Delta;V}}_{\mathrm{ds}}\right)}^2}$

Wherein, V _DsBe drain voltage, I _DsBe drain current, Δ I _Ds' be drain current I _DsThe increment of derivative, Δ V _DsFor the quick scanning voltage that drains increases progressively range value.

2. the MOSFET of utilization input-output characteristic as claimed in claim 1 is determined the method for MOSFET BSIM model parameter width offset, it is characterized in that described step 2) in adopt semiconductor parametric tester to test all MOSFET electric properties of devices.

3. the MOSFET of utilization input-output characteristic as claimed in claim 2 is determined the method for MOSFET BSIM model parameter width offset, it is characterized in that three probes of described semiconductor parametric tester test link to each other with source electrode, the drain and gate of MOSFET device to be measured respectively.

4. the MOSFET of utilization input-output characteristic as claimed in claim 1 is determined the method for MOSFET BSIM model parameter width offset, it is characterized in that described step 2) described in the drain electrode scanning voltage increase progressively range value 0＜Δ V _Ds＜0.05V.

5. the MOSFET of utilization input-output characteristic as claimed in claim 1 is determined the method for MOSFET BSIM model parameter width offset, it is characterized in that, the drain voltage V that selects in the described step 4) _DsSatisfy 0＜V _Ds＜(V _{- Gs}-V _Th)/2, wherein, V _GsBe grid voltage, V _DsBe drain voltage, V _ThBe the MOSFET device threshold voltage.

6. the MOSFET of utilization input-output characteristic as claimed in claim 5 is determined the method for MOSFET BSIM model parameter width offset, it is characterized in that, the drain voltage V that selects in the described step 4) _DsFor greater than 0 less than 1.32V.

7. determine the method for MOSFET BSIM model parameter width offset as claim 1 or the 5 described MOSFET of utilization input-output characteristics, it is characterized in that described step 2) described in the drain electrode scanning voltage increase progressively range value Δ V _DsBe 0.02V, the drain voltage V that selects in the described step 4) _DsBe 0.2V.

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